static irqreturn_t wkup_m3_txev_handler(int irq, void *unused) { writel(0x1, m3_eoi); if (m3_state == M3_STATE_RESET) { m3_state = M3_STATE_INITED; } else if (m3_state == M3_STATE_MSG_FOR_RESET) { m3_state = M3_STATE_INITED; omap_mbox_msg_rx_flush(m3_mbox); if (m3_mbox->ops->ack_irq) m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX); complete(&a8_m3_sync); } else if (m3_state == M3_STATE_MSG_FOR_LP) { omap_mbox_msg_rx_flush(m3_mbox); if (m3_mbox->ops->ack_irq) m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX); complete(&a8_m3_sync); } else if (m3_state == M3_STATE_UNKNOWN) { pr_err("IRQ %d with CM3 in unknown state\n", irq); omap_mbox_msg_rx_flush(m3_mbox); if (m3_mbox->ops->ack_irq) m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX); return IRQ_NONE; } writel(0x0, m3_eoi); return IRQ_HANDLED; }
static irqreturn_t wkup_m3_txev_handler(int irq, void *unused) { writel(0x1, m3_eoi); if (m3_state == M3_STATE_RESET) { m3_state = M3_STATE_INITED; m3_version = readl(ipc_regs + 0x8); m3_version &= 0x0000ffff; if (m3_version == M3_VERSION_UNKNOWN) { pr_warning("Unable to read CM3 firmware version\n"); } else { pr_info("Cortex M3 Firmware Version = 0x%x\n", m3_version); } } else if (m3_state == M3_STATE_MSG_FOR_RESET) { m3_state = M3_STATE_INITED; omap_mbox_msg_rx_flush(m3_mbox); if (m3_mbox->ops->ack_irq) m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX); complete(&a8_m3_sync); } else if (m3_state == M3_STATE_MSG_FOR_LP) { omap_mbox_msg_rx_flush(m3_mbox); if (m3_mbox->ops->ack_irq) m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX); complete(&a8_m3_sync); } else if (m3_state == M3_STATE_UNKNOWN) { pr_err("IRQ %d with CM3 in unknown state\n", irq); omap_mbox_msg_rx_flush(m3_mbox); if (m3_mbox->ops->ack_irq) m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX); return IRQ_NONE; } writel(0x0, m3_eoi); return IRQ_HANDLED; }