/* * Here we start the McBSP, by enabling transmitter, receiver or both. * If no transmitter or receiver is active prior calling, then sample-rate * generator and frame sync are started. */ void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx) { int enable_srg = 0; u16 w; if (mcbsp->st_data) omap_st_start(mcbsp); /* Only enable SRG, if McBSP is master */ w = MCBSP_READ_CACHE(mcbsp, PCR0); if (w & (FSXM | FSRM | CLKXM | CLKRM)) enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); if (enable_srg) { /* Start the sample generator */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); } /* Enable transmitter and receiver */ tx &= 1; w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | tx); rx &= 1; w = MCBSP_READ_CACHE(mcbsp, SPCR1); MCBSP_WRITE(mcbsp, SPCR1, w | rx); /* * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec * REVISIT: 100us may give enough time for two CLKSRG, however * due to some unknown PM related, clock gating etc. reason it * is now at 500us. */ udelay(500); if (enable_srg) { /* Start frame sync */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); } if (mcbsp->pdata->has_ccr) { /* Release the transmitter and receiver */ w = MCBSP_READ_CACHE(mcbsp, XCCR); w &= ~(tx ? XDISABLE : 0); MCBSP_WRITE(mcbsp, XCCR, w); w = MCBSP_READ_CACHE(mcbsp, RCCR); w &= ~(rx ? RDISABLE : 0); MCBSP_WRITE(mcbsp, RCCR, w); } /* Dump McBSP Regs */ omap_mcbsp_dump_reg(mcbsp); }
void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx) { int enable_srg = 0; u16 w; if (mcbsp->st_data) omap_st_start(mcbsp); w = MCBSP_READ_CACHE(mcbsp, PCR0); if (w & (FSXM | FSRM | CLKXM | CLKRM)) enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); if (enable_srg) { w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); } tx &= 1; w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | tx); rx &= 1; w = MCBSP_READ_CACHE(mcbsp, SPCR1); MCBSP_WRITE(mcbsp, SPCR1, w | rx); udelay(500); if (enable_srg) { w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); } if (mcbsp->pdata->has_ccr) { w = MCBSP_READ_CACHE(mcbsp, XCCR); w &= ~(tx ? XDISABLE : 0); MCBSP_WRITE(mcbsp, XCCR, w); w = MCBSP_READ_CACHE(mcbsp, RCCR); w &= ~(rx ? RDISABLE : 0); MCBSP_WRITE(mcbsp, RCCR, w); } omap_mcbsp_dump_reg(mcbsp); }
/* Start DMA * Do the initial set of work to initialize all the channels as required. * We shall then initate a transfer */ int omap_start_alsa_sound_dma(struct audio_stream *s, dma_addr_t dma_ptr, u_int dma_size) { int mode = s->stream_id; int ret = 0; #ifdef TWL_DUMP_REGISTERS_MCBSP printk(KERN_INFO "TRANSFER"); omap_mcbsp_dump_reg(AUDIO_MCBSP); #endif if (mode == SNDRV_PCM_STREAM_CAPTURE) { /* Capture Path to be implemented */ ret = omap2_mcbsp_receive_data(AUDIO_MCBSP, (void *)s, dma_ptr, dma_size); } else { ret = omap2_mcbsp_send_data(AUDIO_MCBSP, (void *)s, dma_ptr, dma_size); } return ret; }
/* * Here we start the McBSP, by enabling transmitter, receiver or both. * If no transmitter or receiver is active prior calling, then sample-rate * generator and frame sync are started. */ void omap_mcbsp_start(unsigned int id, int tx, int rx) { struct omap_mcbsp *mcbsp; int enable_srg = 0; u16 w; if (!omap_mcbsp_check_valid_id(id)) { printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); return; } mcbsp = id_to_mcbsp_ptr(id); if (cpu_is_omap34xx()) omap_st_start(mcbsp); /* Only enable SRG, if McBSP is master */ w = MCBSP_READ_CACHE(mcbsp, PCR0); if (w & (FSXM | FSRM | CLKXM | CLKRM)) enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); if (enable_srg) { /* Start the sample generator */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); } /* Enable transmitter and receiver */ tx &= 1; w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | tx); rx &= 1; w = MCBSP_READ_CACHE(mcbsp, SPCR1); MCBSP_WRITE(mcbsp, SPCR1, w | rx); /* * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec * REVISIT: 100us may give enough time for two CLKSRG, however * due to some unknown PM related, clock gating etc. reason it * is now at 500us. */ udelay(500); if (enable_srg) { /* Start frame sync */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); } if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { /* Release the transmitter and receiver */ w = MCBSP_READ_CACHE(mcbsp, XCCR); w &= ~(tx ? XDISABLE : 0); MCBSP_WRITE(mcbsp, XCCR, w); w = MCBSP_READ_CACHE(mcbsp, RCCR); w &= ~(rx ? RDISABLE : 0); MCBSP_WRITE(mcbsp, RCCR, w); } /* Dump McBSP Regs */ omap_mcbsp_dump_reg(id); }