static void osk_panel_disable(struct lcd_panel *panel)
{
/* Set PWL level to zero */
omap_writeb(0x00, OMAP_PWL_ENABLE);
/* Disable PWL unit */
omap_writeb(0x00, OMAP_PWL_CLK_ENABLE);
/* set GPIO2 low */
gpio_set_value(2, 0);
}
static int ams_delta_panel_enable(struct lcd_panel *panel)
{
ams_delta_latch2_write(AMS_DELTA_LATCH2_LCD_NDISP,
AMS_DELTA_LATCH2_LCD_NDISP);
ams_delta_latch2_write(AMS_DELTA_LATCH2_LCD_VBLEN,
AMS_DELTA_LATCH2_LCD_VBLEN);
omap_writeb(1, OMAP_PWL_CLK_ENABLE);
omap_writeb(AMS_DELTA_DEFAULT_CONTRAST, OMAP_PWL_ENABLE);
return 0;
}
static int osk_panel_enable(struct lcd_panel *panel)
{
/* configure PWL pin */
omap_cfg_reg(PWL);
/* Enable PWL unit */
omap_writeb(0x01, OMAP_PWL_CLK_ENABLE);
/* Set PWL level */
omap_writeb(0xFF, OMAP_PWL_ENABLE);
/* set GPIO2 high (lcd power enabled) */
gpio_set_value(2, 1);
return 0;
}
static void __init voiceblue_init(void)
{
/* mux pins for uarts */
omap_cfg_reg(UART1_TX);
omap_cfg_reg(UART1_RTS);
omap_cfg_reg(UART2_TX);
omap_cfg_reg(UART2_RTS);
omap_cfg_reg(UART3_TX);
omap_cfg_reg(UART3_RX);
/* Watchdog */
gpio_request(0, "Watchdog");
/* smc91x reset */
gpio_request(7, "SMC91x reset");
gpio_direction_output(7, 1);
udelay(2); /* wait at least 100ns */
gpio_set_value(7, 0);
mdelay(50); /* 50ms until PHY ready */
/* smc91x interrupt pin */
gpio_request(8, "SMC91x irq");
/* 16C554 reset*/
gpio_request(6, "16C554 reset");
gpio_direction_output(6, 0);
/* 16C554 interrupt pins */
gpio_request(12, "16C554 irq");
gpio_request(13, "16C554 irq");
gpio_request(14, "16C554 irq");
gpio_request(15, "16C554 irq");
set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
omap_board_config = voiceblue_config;
omap_board_config_size = ARRAY_SIZE(voiceblue_config);
omap_serial_init();
omap_usb_init(&voiceblue_usb_config);
omap_register_i2c_bus(1, 100, NULL, NULL, 0);
/* There is a good chance board is going up, so enable power LED
* (it is connected through invertor) */
omap_writeb(0x00, OMAP_LPG1_LCR);
omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */
}
static int ams_delta_lcd_set_contrast(struct lcd_device *dev, int value)
{
if ((value >= 0) && (value <= AMS_DELTA_MAX_CONTRAST)) {
omap_writeb(value, OMAP_PWL_ENABLE);
ams_delta_lcd &= ~AMS_DELTA_MAX_CONTRAST;
ams_delta_lcd |= value;
}
return 0;
}
static int ams_delta_lcd_set_power(struct lcd_device *dev, int power)
{
if (power == FB_BLANK_UNBLANK) {
if (!(ams_delta_lcd & AMS_DELTA_LCD_POWER)) {
omap_writeb(ams_delta_lcd & AMS_DELTA_MAX_CONTRAST,
OMAP_PWL_ENABLE);
omap_writeb(1, OMAP_PWL_CLK_ENABLE);
ams_delta_lcd |= AMS_DELTA_LCD_POWER;
}
} else {
if (ams_delta_lcd & AMS_DELTA_LCD_POWER) {
omap_writeb(0, OMAP_PWL_ENABLE);
omap_writeb(0, OMAP_PWL_CLK_ENABLE);
ams_delta_lcd &= ~AMS_DELTA_LCD_POWER;
}
}
return 0;
}
static int osk_panel_enable(struct lcd_panel *panel)
{
/* configure PWL pin */
omap_cfg_reg(PWL);
/* Enable PWL unit */
omap_writeb(0x01, OMAP_PWL_CLK_ENABLE);
/* Set PWL level */
omap_writeb(0xFF, OMAP_PWL_ENABLE);
/* configure GPIO2 as output */
omap_set_gpio_direction(2, 0);
/* set GPIO2 high */
omap_set_gpio_dataout(2, 1);
return 0;
}
/* Resets clock rates and reboots the system. Only called from system.h */
void omap_prcm_arch_reset(char mode, const char *cmd)
{
s16 prcm_offs;
omap2_clk_prepare_for_reboot();
if (cpu_is_omap24xx()) {
prcm_offs = WKUP_MOD;
prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
} else if (cpu_is_omap34xx()) {
u32 l;
/* Copy cmd into scratchpad memmory if any */
if(cmd != 0)
{
u16 counter = 0;
while((counter < (OMAP343X_SCRATCHPAD_BCB_SIZE-1)) && (cmd[counter]!='\0')) {
omap_writeb(cmd[counter], OMAP343X_SCRATCHPAD_BCB + counter);
counter++;
}
omap_writeb('\0', OMAP343X_SCRATCHPAD_BCB + counter);
}
prcm_offs = OMAP3430_GR_MOD;
l = ('B' << 24) | ('M' << 16) | mode;
/* Reserve the first word in scratchpad for communicating
* with the boot ROM. A pointer to a data structure
* describing the boot process can be stored there,
* cf. OMAP34xx TRM, Initialization / Software Booting
* Configuration. */
omap_writel(l, OMAP343X_SCRATCHPAD + 4);
omap3_configure_core_dpll_warmreset();
} else
WARN_ON(1);
}
static void __init voiceblue_init(void)
{
/* Watchdog */
omap_request_gpio(0);
/* smc91x reset */
omap_request_gpio(7);
omap_set_gpio_direction(7, 0);
omap_set_gpio_dataout(7, 1);
udelay(2); /* wait at least 100ns */
omap_set_gpio_dataout(7, 0);
mdelay(50); /* 50ms until PHY ready */
/* smc91x interrupt pin */
omap_request_gpio(8);
/* 16C554 reset*/
omap_request_gpio(6);
omap_set_gpio_direction(6, 0);
omap_set_gpio_dataout(6, 0);
/* 16C554 interrupt pins */
omap_request_gpio(12);
omap_request_gpio(13);
omap_request_gpio(14);
omap_request_gpio(15);
set_irq_type(OMAP_GPIO_IRQ(12), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(13), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(14), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(15), IRQT_RISING);
platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
omap_board_config = voiceblue_config;
omap_board_config_size = ARRAY_SIZE(voiceblue_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
/* There is a good chance board is going up, so enable power LED
* (it is connected through invertor) */
omap_writeb(0x00, OMAP_LPG1_LCR);
omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */
}
static int omap1610_irda_shutdown(struct omap1610_irda *si)
{
/* Disable all UART3 Interrupts */
omap_writeb(0, UART3_IER);
/* Disable UART3 and disable baud rate generator */
omap_writeb(0x07, UART3_MDR1); /* Put UART3 in reset mode */
omap_writeb((1 << 5), UART3_ACREG); /* set SD_MODE pin to high and Disable RX IR */
/* Clear DLH and DLL */
omap_writeb(1 << 7, UART3_LCR);
omap_writeb(0, UART3_DLL);
omap_writeb(0, UART3_DLH);
return 0;
}
static void ohci_context_restore(void)
{
int i;
if (is_sil_rev_less_than(OMAP3430_REV_ES3_1)) {
#if 0
/* FIXME: This was reported as not working. Temporarily
* disable this infinite loop pending investigation
*/
/* perform TLL soft reset, and wait until reset is complete */
omap_writel(1 << OMAP_USBTLL_SYSCONFIG_SOFTRESET_SHIFT,
OMAP_USBTLL_SYSCONFIG);
/* Wait for TLL reset to complete */
while (!(omap_readl(OMAP_USBTLL_SYSSTATUS) &
(1 << OMAP_USBTLL_SYSSTATUS_RESETDONE_SHIFT)));
#endif
omap_writel(ohci_context.usbtll_sysconfig,
OMAP_USBTLL_SYSCONFIG);
omap_writel(ohci_context.tll_shared_conf,
OMAP_TLL_SHARED_CONF);
for (i = 0; i < 3; i++) {
omap_writel(ohci_context.tll_channel_conf[i],
OMAP_TLL_CHANNEL_CONF(i));
omap_writeb(ohci_context.ulpi_interface_ctrl[i],
OMAP_TLL_ULPI_INTERFACE_CTRL(i));
omap_writeb(ohci_context.ulpi_function_ctrl[i],
OMAP_TLL_ULPI_FUNCTION_CTRL(i));
omap_writeb(ohci_context.ulpi_otg_ctrl[i],
OMAP_TLL_ULPI_OTG_CTRL(i));
omap_writeb(ohci_context.ulpi_usb_int_en_rise[i],
OMAP_TLL_ULPI_INT_EN_RISE(i));
omap_writeb(ohci_context.ulpi_usb_int_en_fall[i],
OMAP_TLL_ULPI_INT_EN_FALL(i));
omap_writeb(ohci_context.ulpi_usb_int_status[i],
OMAP_TLL_ULPI_INT_STATUS(i));
}
omap_writel(ohci_context.usbtll_irqenable,
OMAP_USBTLL_IRQENABLE);
}
}
static int omap1610_irda_set_speed(struct net_device *dev, int speed)
{
struct omap1610_irda *si = dev->priv;
int divisor;
__ECHO_IN;
/* Set IrDA speed */
if (speed <= 115200) {
/* SIR mode */
if (machine_is_omap_h2()) {
omap_set_gpio_dataout(OMAP1610_H2_FIRSEL_GPIO, 0);
}
if (machine_is_omap_h3())
set_h3_irda_mode(SIR_MODE);
printk("Set SIR Mode! Speed: %d\n", speed);
omap_writeb(1, UART3_MDR1); /* Set SIR mode */
omap_writeb(1, UART3_EBLR);
divisor = 48000000 / (16 * speed); /* Base clock 48 MHz */
HDBG2(1);
omap_writeb(1 << 7, UART3_LCR);
omap_writeb((divisor & 0xFF), UART3_DLL);
omap_writeb((divisor >> 8), UART3_DLH);
omap_writeb(0x03, UART3_LCR);
omap_writeb(0, UART3_MCR);
HDBG2(1);
} else if (speed <= 1152000) {
static void inline omapbl_send_intensity(int intensity)
{
omap_writeb(intensity, OMAP_PWL_ENABLE);
}
/**
* ehci_hcd_omap_probe - initialize TI-based HCDs
*
* Allocates basic resources for this USB host controller, and
* then invokes the start() method for the HCD associated with it
* through the hotplug entry's driver_data.
*/
static int ehci_hcd_omap_probe(struct platform_device *pdev)
{
struct uhhtll_apis *uhhtllp = pdev->dev.platform_data;
struct ehci_hcd_omap *omap;
struct usbhs_omap_platform_data *pdata;
struct usbhs_omap_resource *omapresp;
struct usb_hcd *hcd;
int ret = -ENODEV;
if (!uhhtllp) {
dev_dbg(&pdev->dev, "missing platform_data\n");
goto err_end;
}
if (usb_disabled())
goto err_end;
omap = kzalloc(sizeof(*omap), GFP_KERNEL);
if (!omap) {
ret = -ENOMEM;
goto err_end;
}
pdata = &omap->platdata;
if (uhhtllp->get_platform_data(pdata) != 0) {
ret = -EINVAL;
goto err_mem;
}
omapresp = &omap->res;
if (uhhtllp->get_resource(OMAP_EHCI, omapresp) != 0) {
ret = -EINVAL;
goto err_mem;
}
if (!omapresp->regs) {
dev_dbg(&pdev->dev, "failed to EHCI regs\n");
goto err_mem;
}
hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev,
dev_name(&pdev->dev));
if (!hcd) {
dev_dbg(&pdev->dev, "failed to create hcd with err %d\n", ret);
ret = -ENOMEM;
goto err_mem;
}
platform_set_drvdata(pdev, omap);
omap->dev = &pdev->dev;
omap->ehci = hcd_to_ehci(hcd);
omap->ehci->sbrn = 0x20;
hcd->rsrc_start = omapresp->start;
hcd->rsrc_len = omapresp->len;
hcd->regs = omapresp->regs;
/* we know this is the memory we want, no need to ioremap again */
omap->ehci->caps = hcd->regs;
ret = uhhtllp->store(OMAP_EHCI, OMAP_USB_HCD, hcd);
if (ret) {
dev_dbg(&pdev->dev, "failed to store hcd\n");
goto err_regs;
}
ret = uhhtllp->enable(OMAP_EHCI);
if (ret) {
dev_dbg(&pdev->dev, "failed to start ehci\n");
goto err_regs;
}
if (cpu_is_omap34xx()) {
/*
* An undocumented "feature" in the OMAP3 EHCI controller,
* causes suspended ports to be taken out of suspend when
* the USBCMD.Run/Stop bit is cleared (for example when
* we do ehci_bus_suspend).
* This breaks suspend-resume if the root-hub is allowed
* to suspend. Writing 1 to this undocumented register bit
* disables this feature and restores normal behavior.
*/
ehci_omap_writel(omap->res.regs, EHCI_INSNREG04,
EHCI_INSNREG04_DISABLE_UNSUSPEND);
/* Soft reset the PHY using PHY reset command over ULPI */
if (pdata->port_mode[0] == OMAP_EHCI_PORT_MODE_PHY)
omap_ehci_soft_phy_reset(omap, 0);
if (pdata->port_mode[1] == OMAP_EHCI_PORT_MODE_PHY)
omap_ehci_soft_phy_reset(omap, 1);
}
if (cpu_is_omap44xx()) {
/*
* Undocumented HW Errata for OMAP4 TLL
* the IDGND ULPI bits generate an interrupt when the
* controller is enabled from OFF mode. This causes the
* port status to be reported as disabled. Mask these
* interrupts since TLL does not require them.
*/
if (pdata->port_mode[0] == OMAP_EHCI_PORT_MODE_TLL) {
omap_writeb(0x10, USB_INT_EN_RISE_CLR_0);
omap_writeb(0x10, USB_INT_EN_FALL_CLR_0);
omap_writeb(0x01, OTG_CTRL_SET_0);
}
if (pdata->port_mode[1] == OMAP_EHCI_PORT_MODE_TLL) {
omap_writeb(0x10, USB_INT_EN_RISE_CLR_1);
omap_writeb(0x10, USB_INT_EN_FALL_CLR_1);
omap_writeb(0x01, OTG_CTRL_SET_1);
}
}
omap->ehci->regs = hcd->regs
+ HC_LENGTH(readl(&omap->ehci->caps->hc_capbase));
dbg_hcs_params(omap->ehci, "reset");
dbg_hcc_params(omap->ehci, "reset");
/* cache this readonly data; minimize chip reads */
omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params);
ret = usb_add_hcd(hcd, omapresp->irq, IRQF_DISABLED | IRQF_SHARED);
if (ret) {
dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
goto err_add_hcd;
}
/* root ports should always stay powered */
ehci_port_power(omap->ehci, 1);
return 0;
err_add_hcd:
uhhtllp->disable(OMAP_EHCI);
err_regs:
usb_put_hcd(hcd);
err_mem:
kfree(omap);
err_end:
return ret;
}
static int omap1610_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct omap1610_irda *si = dev->priv;
int speed = irda_get_next_speed(skb);
int mtt = irda_get_mtt(skb);
int xbofs = irda_get_next_xbofs(skb);
__ECHO_IN;
/*
* Does this packet contain a request to change the interface
* speed? If so, remember it until we complete the transmission
* of this frame.
*/
if (speed != si->speed && speed != -1)
si->newspeed = speed;
if (xbofs) {
/* Set number of addtional BOFS */
omap_writeb(xbofs + 1, UART3_EBLR);
}
/*
* If this is an empty frame, we can bypass a lot.
*/
if (skb->len == 0) {
if (si->newspeed) {
si->newspeed = 0;
omap1610_irda_set_speed(dev, speed);
}
dev_kfree_skb(skb);
return 0;
}
netif_stop_queue(dev);
/* Copy skb data to DMA buffer */
memcpy(si->tx_buf_dma_virt, skb->data, skb->len);
si->stats.tx_bytes += skb->len;
/* Set frame length */
omap_writeb((skb->len & 0xff), UART3_TXFLL);
omap_writeb((skb->len >> 8), UART3_TXFLH);
if (mtt > 1000)
mdelay(mtt / 1000);
else
udelay(mtt);
/* Start TX DMA transfer */
omap1610_start_tx_dma(si, skb->len);
/* We can free skb now because it's already in DMA buffer */
dev_kfree_skb(skb);
dev->trans_start = jiffies;
__ECHO_OUT;
return 0;
}
static int omap1610_irda_startup(struct net_device *dev)
{
__ECHO_IN;
/* Enable UART3 clock and set UART3 to IrDA mode */
omap_writel(omap_readl(MOD_CONF_CTRL_0) | (1 << 31) | (1 << 15),
MOD_CONF_CTRL_0);
if (machine_is_omap_h2()) {
// omap_cfg_reg(Y15_1610_GPIO17);
omap_writel(omap_readl(FUNC_MUX_CTRL_A) | 7, FUNC_MUX_CTRL_A);
omap_set_gpio_direction(OMAP1610_H2_FIRSEL_GPIO, 0);
omap_set_gpio_dataout(OMAP1610_H2_FIRSEL_GPIO, 0);
}
omap_writeb(0x07, UART3_MDR1); /* Put UART3 in reset mode */
/* Clear DLH and DLL */
omap_writeb(1 << 7, UART3_LCR);
omap_writeb(0, UART3_DLL);
omap_writeb(0, UART3_DLH);
omap_writeb(0xbf, UART3_LCR);
omap_writeb(1 << 4, UART3_EFR);
omap_writeb(1 << 7, UART3_LCR);
/* Enable access to UART3_TLR and UART3_TCR registers */
omap_writeb(1 << 6, UART3_MCR);
omap_writeb(0, UART3_SCR);
/* Set Rx trigger to 1 and Tx trigger to 1 */
omap_writeb(0, UART3_TLR);
/* Set LCR to 8 bits and 1 stop bit */
omap_writeb(0x03, UART3_LCR);
/* Clear RX and TX FIFO and enable FIFO */
/* Use DMA Req for transfers */
omap_writeb((1 << 2) | (1 << 1) | (1 << 3) | (1 << 4) | (1 << 6) | 1,
UART3_FCR);
omap_writeb(0, UART3_MCR);
omap_writeb((1 << 7) | (1 << 6), UART3_SCR);
/* Enable UART3 SIR Mode,(Frame-length method to end frames) */
omap_writeb(1, UART3_MDR1);
/* Set Status FIFO trig to 1 */
omap_writeb(0, UART3_MDR2);
/* Enables RXIR input */
/* and disable TX underrun */
/* SEND_SIP pulse */
// omap_writeb((1 << 7) | (1 << 6) | (1 << 4), UART3_ACREG);
omap_writeb((1 << 6) | (1 << 4), UART3_ACREG);
/* Enable EOF Interrupt only */
omap_writeb((1 << 7) | (1 << 5), UART3_IER);
/* Set Maximum Received Frame size to 2048 bytes */
omap_writeb(0x00, UART3_RXFLL);
omap_writeb(0x08, UART3_RXFLH);
omap_readb(UART3_RESUME);
__ECHO_OUT;
return 0;
}
/*
* Sets the Omap MUX and PULL_DWN registers based on the table
*/
int __init_or_module omap_cfg_reg(const unsigned long index)
{
static DEFINE_RAW_SPINLOCK(mux_spin_lock);
unsigned long flags;
struct pin_config *cfg;
unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
pull_orig = 0, pull = 0;
unsigned int mask, warn = 0;
if (!pin_table)
BUG();
if (index >= pin_table_sz) {
printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
index, pin_table_sz);
dump_stack();
return -ENODEV;
}
cfg = (struct pin_config *)&pin_table[index];
if (cpu_is_omap24xx()) {
u8 reg = 0;
reg |= cfg->mask & 0x7;
if (cfg->pull_val)
reg |= OMAP24XX_PULL_ENA;
if(cfg->pu_pd_val)
reg |= OMAP24XX_PULL_UP;
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
{
u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
u8 debug = 0;
#ifdef CONFIG_OMAP_MUX_DEBUG
debug = cfg->debug;
#endif
warn = (orig != reg);
if (debug || warn)
printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
cfg->name,
OMAP24XX_L4_BASE + cfg->mux_reg,
orig, reg);
}
#endif
omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
return 0;
}
/* Check the mux register in question */
if (cfg->mux_reg) {
unsigned tmp1, tmp2;
spin_lock_irqsave(&mux_spin_lock, flags);
reg_orig = omap_readl(cfg->mux_reg);
/* The mux registers always seem to be 3 bits long */
mask = (0x7 << cfg->mask_offset);
tmp1 = reg_orig & mask;
reg = reg_orig & ~mask;
tmp2 = (cfg->mask << cfg->mask_offset);
reg |= tmp2;
if (tmp1 != tmp2)
warn = 1;
omap_writel(reg, cfg->mux_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
/* Check for pull up or pull down selection on 1610 */
if (!cpu_is_omap1510()) {
if (cfg->pu_pd_reg && cfg->pull_val) {
spin_lock_irqsave(&mux_spin_lock, flags);
pu_pd_orig = omap_readl(cfg->pu_pd_reg);
mask = 1 << cfg->pull_bit;
if (cfg->pu_pd_val) {
if (!(pu_pd_orig & mask))
warn = 1;
/* Use pull up */
pu_pd = pu_pd_orig | mask;
} else {
if (pu_pd_orig & mask)
warn = 1;
/* Use pull down */
pu_pd = pu_pd_orig & ~mask;
}
omap_writel(pu_pd, cfg->pu_pd_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
}
/* Check for an associated pull down register */
if (cfg->pull_reg) {
spin_lock_irqsave(&mux_spin_lock, flags);
pull_orig = omap_readl(cfg->pull_reg);
mask = 1 << cfg->pull_bit;
if (cfg->pull_val) {
if (pull_orig & mask)
warn = 1;
/* Low bit = pull enabled */
pull = pull_orig & ~mask;
} else {
if (!(pull_orig & mask))
warn = 1;
/* High bit = pull disabled */
pull = pull_orig | mask;
}
omap_writel(pull, cfg->pull_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
if (warn) {
#ifdef CONFIG_OMAP_MUX_WARNINGS
printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
#endif
}
#ifdef CONFIG_OMAP_MUX_DEBUG
if (cfg->debug || warn) {
printk("MUX: Setting register %s\n", cfg->name);
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
if (!cpu_is_omap1510()) {
if (cfg->pu_pd_reg && cfg->pull_val) {
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pu_pd_name, cfg->pu_pd_reg,
pu_pd_orig, pu_pd);
}
}
if (cfg->pull_reg)
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pull_name, cfg->pull_reg, pull_orig, pull);
}
#endif
#ifdef CONFIG_OMAP_MUX_ERRORS
return warn ? -ETXTBSY : 0;
#else
return 0;
#endif
}
static void inline uart_reg_out(int idx, u8 val)
{
omap_writeb(val, idx);
}
static void inline omapbl_send_enable(int enable)
{
omap_writeb(enable, OMAP_PWL_CLK_ENABLE);
}
static void omap_usb_utmi_init(struct usb_hcd *hcd, u8 tll_channel_mask)
{
int i;
/* Use UTMI Ports of TLL */
omap_writel((1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)|
(1<<OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN_SHIFT)|
(1<<OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN_SHIFT)|
(1<<OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN_SHIFT)|
(0<<OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN_SHIFT),
OMAP_UHH_HOSTCONFIG);
/* Enusre bit is set */
while (!(omap_readl(OMAP_UHH_HOSTCONFIG)
& (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)))
cpu_relax();
dev_dbg(hcd->self.controller, "\nEntered UTMI MODE: success\n");
/* Program the 3 TLL channels upfront */
for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
/* Disable AutoIdle */
omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
~(1<<OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE_SHIFT),
OMAP_TLL_CHANNEL_CONF(i));
/* Disable BitStuffing */
omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
~(1<<OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF_SHIFT),
OMAP_TLL_CHANNEL_CONF(i));
/* SDR Mode */
omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
~(1<<OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE_SHIFT),
OMAP_TLL_CHANNEL_CONF(i));
}
/* Program Common TLL register */
omap_writel((1 << OMAP_TLL_SHARED_CONF_FCLK_IS_ON_SHIFT) |
(1 << OMAP_TLL_SHARED_CONF_USB_DIVRATION_SHIFT) |
(0 << OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN_SHIFT) |
(0 << OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN_SHFT),
OMAP_TLL_SHARED_CONF);
/* Enable channels now */
for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
/* Enable only the channel that is needed */
if (!(tll_channel_mask & 1<<i))
continue;
omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) |
(1<<OMAP_TLL_CHANNEL_CONF_CHANEN_SHIFT),
OMAP_TLL_CHANNEL_CONF(i));
omap_writeb(0xBE, OMAP_TLL_ULPI_SCRATCH_REGISTER(i));
dev_dbg(hcd->self.controller, "\nULPI_SCRATCH_REG[ch=%d]"
"= 0x%02x\n",
i+1, omap_readb(OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
}
}
