static bool __memory_parse(struct dt_node *root)
{
struct HDIF_common_hdr *ms_vpd;
const struct msvpd_ms_addr_config *msac;
const struct msvpd_total_config_ms *tcms;
unsigned int size;
ms_vpd = get_hdif(&spira.ntuples.ms_vpd, MSVPD_HDIF_SIG);
if (!ms_vpd) {
prerror("MS VPD: invalid\n");
op_display(OP_FATAL, OP_MOD_MEM, 0x0000);
return false;
}
if (be32_to_cpu(spira.ntuples.ms_vpd.act_len) < sizeof(*ms_vpd)) {
prerror("MS VPD: invalid size %u\n",
be32_to_cpu(spira.ntuples.ms_vpd.act_len));
op_display(OP_FATAL, OP_MOD_MEM, 0x0001);
return false;
}
prlog(PR_DEBUG, "MS VPD: is at %p\n", ms_vpd);
msac = HDIF_get_idata(ms_vpd, MSVPD_IDATA_MS_ADDR_CONFIG, &size);
if (!CHECK_SPPTR(msac) || size < sizeof(*msac)) {
prerror("MS VPD: bad msac size %u @ %p\n", size, msac);
op_display(OP_FATAL, OP_MOD_MEM, 0x0002);
return false;
}
prlog(PR_DEBUG, "MS VPD: MSAC is at %p\n", msac);
dt_add_property_u64(dt_root, DT_PRIVATE "maxmem",
be64_to_cpu(msac->max_configured_ms_address));
tcms = HDIF_get_idata(ms_vpd, MSVPD_IDATA_TOTAL_CONFIG_MS, &size);
if (!CHECK_SPPTR(tcms) || size < sizeof(*tcms)) {
prerror("MS VPD: Bad tcms size %u @ %p\n", size, tcms);
op_display(OP_FATAL, OP_MOD_MEM, 0x0003);
return false;
}
prlog(PR_DEBUG, "MS VPD: TCMS is at %p\n", tcms);
prlog(PR_DEBUG, "MS VPD: Maximum configured address: 0x%llx\n",
(long long)be64_to_cpu(msac->max_configured_ms_address));
prlog(PR_DEBUG, "MS VPD: Maximum possible address: 0x%llx\n",
(long long)be64_to_cpu(msac->max_possible_ms_address));
get_msareas(root, ms_vpd);
prlog(PR_INFO, "MS VPD: Total MB of RAM: 0x%llx\n",
(long long)be64_to_cpu(tcms->total_in_mb));
return true;
}
void ibm_fsp_init(void)
{
/* Early initializations of the FSP interface */
fsp_init();
map_debug_areas();
fsp_sysparam_init();
/* Get ready to receive E0 class messages. We need to respond
* to some of these for the init sequence to make forward progress
*/
fsp_console_preinit();
/* Get ready to receive OCC related messages */
occ_fsp_init();
/* Get ready to receive Memory [Un]corretable Error messages. */
fsp_memory_err_init();
/* Initialize elog access */
fsp_elog_read_init();
fsp_elog_write_init();
/* Initiate dump service */
fsp_dump_init();
/* Start FSP/HV state controller & perform OPL */
fsp_opl();
/* Preload hostservices lids */
hservices_lid_preload();
/* Initialize SP attention area */
fsp_attn_init();
/* Initialize monitoring of TOD topology change event notification */
fsp_chiptod_init();
/* Send MDST table notification to FSP */
op_display(OP_LOG, OP_MOD_INIT, 0x0000);
fsp_mdst_table_init();
/* Initialize the panel */
op_display(OP_LOG, OP_MOD_INIT, 0x0001);
fsp_oppanel_init();
/* Start the surveillance process */
op_display(OP_LOG, OP_MOD_INIT, 0x0002);
fsp_init_surveillance();
/* IPMI */
fsp_ipmi_init();
ipmi_opal_init();
/* Initialize sensor access */
op_display(OP_LOG, OP_MOD_INIT, 0x0003);
fsp_init_sensor();
/* LED */
op_display(OP_LOG, OP_MOD_INIT, 0x0004);
fsp_led_init();
/* Monitor for DIAG events */
op_display(OP_LOG, OP_MOD_INIT, 0x0005);
fsp_init_diag();
/* Finish initializing the console */
op_display(OP_LOG, OP_MOD_INIT, 0x0006);
fsp_console_init();
/* Read our initial RTC value */
op_display(OP_LOG, OP_MOD_INIT, 0x0008);
fsp_rtc_init();
/* Initialize code update access */
op_display(OP_LOG, OP_MOD_INIT, 0x0009);
fsp_code_update_init();
/* EPOW */
op_display(OP_LOG, OP_MOD_INIT, 0x000A);
fsp_epow_init();
/* EPOW */
op_display(OP_LOG, OP_MOD_INIT, 0x000B);
fsp_dpo_init();
/* Setup console */
if (fsp_present())
fsp_console_add_nodes();
if (proc_gen >= proc_gen_p9)
prd_init();
}
