static inline void mtu3d_otg_intr_handler(u32 dwOtgIntValue)
{
if (dwOtgIntValue & VBUS_CHG_INTR) {
os_printk(K_NOTICE, "OTG: VBUS_CHG_INTR\n");
os_setmsk(U3D_SSUSB_OTG_STS_CLR, SSUSB_VBUS_INTR_CLR);
}
//this interrupt is issued when B device becomes device
if (dwOtgIntValue & SSUSB_CHG_B_ROLE_B) {
os_printk(K_NOTICE, "OTG: CHG_B_ROLE_B\n");
os_setmsk(U3D_SSUSB_OTG_STS_CLR, SSUSB_CHG_B_ROLE_B_CLR);
//switch DMA module to device
os_printk(K_NOTICE, "Switch DMA to device\n");
os_clrmsk(U3D_SSUSB_U2_CTRL_0P, SSUSB_U2_PORT_HOST_SEL);
}
//this interrupt is issued when B device becomes host
if (dwOtgIntValue & SSUSB_CHG_A_ROLE_B) {
os_printk(K_NOTICE, "OTG: CHG_A_ROLE_B\n");
os_setmsk(U3D_SSUSB_OTG_STS_CLR, SSUSB_CHG_A_ROLE_B_CLR);
}
//this interrupt is issued when IDDIG reads B
if (dwOtgIntValue & SSUSB_ATTACH_B_ROLE) {
os_printk(K_NOTICE, "OTG: CHG_ATTACH_B_ROLE\n");
os_setmsk(U3D_SSUSB_OTG_STS_CLR, SSUSB_ATTACH_B_ROLE_CLR);
//switch DMA module to device
os_printk(K_NOTICE, "Switch DMA to device\n");
os_clrmsk(U3D_SSUSB_U2_CTRL_0P, SSUSB_U2_PORT_HOST_SEL);
}
}
static inline void mtu3d_u2_common_intr_handler(u32 dwIntrUsbValue)
{
if (dwIntrUsbValue & DISCONN_INTR) {
mu3d_hal_pdn_ip_port(1, 0, 1, 1);
os_printk(K_NOTICE, "[U2 DISCONN_INTR] Set SOFT_CONN=0\n");
os_clrmsk(U3D_POWER_MANAGEMENT, SOFT_CONN);
/*TODO-J: ADD musb_g_disconnect(musb);??*/
}
if (dwIntrUsbValue & LPM_INTR) {
u32 rmwake ;
rmwake = os_readl(U3D_POWER_MANAGEMENT);
os_printk(K_NOTICE, "[U2 LPM interrupt] last rmwake is 0x%x\n", rmwake & LPM_RWP);
if (!((os_readl(U3D_POWER_MANAGEMENT) & LPM_HRWE))) {
mu3d_hal_pdn_ip_port(0, 0, 0, 1);
}
#ifdef CONFIG_USBIF_COMPLIANCE
// SW word around for USBIF test with Fresco FL1100 with LPM L1C enabling
#if 0
if (rmwake & LPM_RWP){
os_writel(U3D_USB20_MISC_CONTROL, os_readl(U3D_USB20_MISC_CONTROL) | LPM_U3_ACK_EN);
os_writel(U3D_POWER_MANAGEMENT, os_readl(U3D_POWER_MANAGEMENT) | RESUME);
}
#endif
#endif
}
if (dwIntrUsbValue & LPM_RESUME_INTR) {
if (!(os_readl(U3D_POWER_MANAGEMENT) & LPM_HRWE)) {
mu3d_hal_pdn_ip_port(1, 0, 0, 1);
os_writel(U3D_USB20_MISC_CONTROL, os_readl(U3D_USB20_MISC_CONTROL) | LPM_U3_ACK_EN);
}
}
if(dwIntrUsbValue & SUSPEND_INTR) {
os_printk(K_NOTICE, "[U2 SUSPEND_INTR]\n");
mu3d_hal_pdn_ip_port(0, 0, 0, 1);
}
if (dwIntrUsbValue & RESUME_INTR) {
os_printk(K_NOTICE,"[U2 RESUME_INTR]\n");
mu3d_hal_pdn_ip_port(1, 0, 0, 1);
}
if (dwIntrUsbValue & RESET_INTR) {
os_printk(K_NOTICE,"[U2 RESET_INTR]\n");
}
}
static inline void mtu3d_u2_common_intr_handler(u32 dwIntrUsbValue)
{
if (dwIntrUsbValue & DISCONN_INTR) {
mu3d_hal_pdn_ip_port(1, 0, 1, 1);
os_printk(K_NOTICE, "[U2 DISCONN_INTR] Set SOFT_CONN=0\n");
os_clrmsk(U3D_POWER_MANAGEMENT, SOFT_CONN);
/*TODO-J: ADD musb_g_disconnect(musb);??*/
}
if (dwIntrUsbValue & LPM_INTR) {
os_printk(K_NOTICE, "[U2 LPM interrupt]\n");
if (!((os_readl(U3D_POWER_MANAGEMENT) & LPM_HRWE))) {
mu3d_hal_pdn_ip_port(0, 0, 0, 1);
}
}
if (dwIntrUsbValue & LPM_RESUME_INTR) {
if (!(os_readl(U3D_POWER_MANAGEMENT) & LPM_HRWE)) {
mu3d_hal_pdn_ip_port(1, 0, 0, 1);
os_writel(U3D_USB20_MISC_CONTROL, os_readl(U3D_USB20_MISC_CONTROL) | LPM_U3_ACK_EN);
}
}
if(dwIntrUsbValue & SUSPEND_INTR) {
os_printk(K_NOTICE, "[U2 SUSPEND_INTR]\n");
mu3d_hal_pdn_ip_port(0, 0, 0, 1);
}
if (dwIntrUsbValue & RESUME_INTR) {
os_printk(K_NOTICE,"[U2 RESUME_INTR]\n");
mu3d_hal_pdn_ip_port(1, 0, 0, 1);
}
if (dwIntrUsbValue & RESET_INTR) {
os_printk(K_NOTICE,"[U2 RESET_INTR]\n");
}
}
static inline void mtu3d_u3_ltssm_intr_handler(struct musb *musb, u32 dwLtssmValue)
{
static u32 soft_conn_num = 0;
if (dwLtssmValue & SS_DISABLE_INTR) {
os_printk(K_INFO, "LTSSM: SS_DISABLE_INTR [%d] & Set SOFT_CONN=1\n", soft_conn_num++);
//enable U2 link. after host reset, HS/FS EP0 configuration is applied in musb_g_reset
os_clrmsk(U3D_SSUSB_U2_CTRL_0P, SSUSB_U2_PORT_PDN);
os_setmsk(U3D_POWER_MANAGEMENT, SOFT_CONN);
}
if (dwLtssmValue & ENTER_U0_INTR) {
soft_conn_num = 0;
//do not apply U3 EP0 setting again, if the speed is already U3
//LTSSM may go to recovery and back to U0
if (musb->g.speed != USB_SPEED_SUPER) {
os_printk(K_INFO, "LTSSM: ENTER_U0_INTR %d\n", musb->g.speed);
musb_conifg_ep0(musb);
}
}
if (dwLtssmValue & VBUS_FALL_INTR) {
os_printk(K_INFO, "LTSSM: VBUS_FALL_INTR\n");
mu3d_hal_pdn_ip_port(1, 1, 1, 1);
mu3d_hal_u3dev_dis();
}
if (dwLtssmValue & VBUS_RISE_INTR) {
os_printk(K_INFO, "LTSSM: VBUS_RISE_INTR\n");
mu3d_hal_u3dev_en();
}
if (dwLtssmValue & ENTER_U3_INTR) {
os_printk(K_INFO, "LTSSM: ENTER_U3_INTR\n");
mu3d_hal_pdn_ip_port(0, 0, 1, 0);
}
if (dwLtssmValue & EXIT_U3_INTR) {
os_printk(K_INFO, "LTSSM: EXIT_U3_INTR\n");
mu3d_hal_pdn_ip_port(1, 0, 1, 0);
}
#ifndef POWER_SAVING_MODE
if (dwLtssmValue & U3_RESUME_INTR) {
os_printk(K_INFO, "LTSSM: RESUME_INTR\n");
mu3d_hal_pdn_ip_port(1, 0, 1, 0);
os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | UX_EXIT);
}
#endif
/*7.5.12.2 Hot Reset Requirements
* 1. A downstream port shall reset its Link Error Count as defined in Section 7.4.2.
* 2. A downstream port shall reset its PM timers and the associated U1 and U2 timeout values to zero.
* 3. The port Configuration information shall remain unchanged (refer to Section 8.4.6 for details).
* 4. The port shall maintain its transmitter specifications defined in Table 6-10.
* 5. The port shall maintain its low-impedance receiver termination (RRX-DC) defined in Table 6-13.
*/
if (dwLtssmValue & HOT_RST_INTR) {
DEV_INT32 link_err_cnt;
DEV_INT32 timeout_val;
os_printk(K_INFO, "LTSSM: HOT_RST_INTR\n");
/* Clear link error count */
link_err_cnt=os_readl(U3D_LINK_ERR_COUNT);
os_printk(K_INFO, "LTSSM: link_err_cnt=%x\n", link_err_cnt);
os_writel(U3D_LINK_ERR_COUNT, CLR_LINK_ERR_CNT);
/* Clear U1 & U2 Enable*/
os_clrmsk(U3D_LINK_POWER_CONTROL, (SW_U1_ACCEPT_ENABLE|SW_U2_ACCEPT_ENABLE));
musb->g.pwr_params.bU1Enabled = 0;
musb->g.pwr_params.bU2Enabled = 0;
/* Reset U1 & U2 timeout value*/
timeout_val = os_readl(U3D_LINK_UX_INACT_TIMER);
os_printk(K_INFO, "LTSSM: timer_val =%x\n", timeout_val);
timeout_val &= ~ (U1_INACT_TIMEOUT_VALUE | DEV_U2_INACT_TIMEOUT_VALUE);
os_writel(U3D_LINK_UX_INACT_TIMER, timeout_val);
}
if (dwLtssmValue & SS_INACTIVE_INTR) os_printk(K_INFO, "LTSSM: SS_INACTIVE_INTR\n");
if (dwLtssmValue & RECOVERY_INTR) os_printk(K_DEBUG, "LTSSM: RECOVERY_INTR\n");
/* A completion of a Warm Reset shall result in the following.
* 1. A downstream port shall reset its Link Error Count.
* 2. Port configuration information of an upstream port shall be reset to default values. Refer to
* Sections 8.4.5 and 8.4.6 for details.
* 3. The PHY level variables (such as Rx equalization settings) shall be reinitialized or retrained.
* 4. The LTSSM of a port shall transition to U0 through RxDetect and Polling.
*/
if (dwLtssmValue & WARM_RST_INTR) {
DEV_INT32 link_err_cnt;
os_printk(K_INFO, "LTSSM: WARM_RST_INTR\n");
/* Clear link error count */
link_err_cnt=os_readl(U3D_LINK_ERR_COUNT);
os_printk(K_INFO, "LTSSM: link_err_cnt=%x\n", link_err_cnt);
os_writel(U3D_LINK_ERR_COUNT, CLR_LINK_ERR_CNT);
}
if (dwLtssmValue & ENTER_U2_INTR) os_printk(K_DEBUG, "LTSSM: ENTER_U2_INTR\n");
if (dwLtssmValue & ENTER_U1_INTR) os_printk(K_DEBUG, "LTSSM: ENTER_U1_INTR\n");
if (dwLtssmValue & RXDET_SUCCESS_INTR) os_printk(K_INFO, "LTSSM: RXDET_SUCCESS_INTR\n");
}
