static int setoutmode(int val){
unsigned long ad;
unsigned long dioval,intval;
/* create int control value */
intval = (val & DO_MODE1_CASCADE)?0x0800:0 |
((val & DO_O_ACK_INT))?0x1:0;
/* create dio control val */
dioval = ((val & 0x03)?0x180:0x200) |
((val & DO_TRIG)?0x800:0x0 ) |
((val & DO_UND)?0x10000:0) |
((val & DO_CLEAR_FIFO)?0x400:0);
ad=iocard_base+IOCARD_INT_STATUS; outl_p(intval,ad);
ad=iocard_base+IOCARD_DIO_STATUS; outl_p(dioval,ad);
diovalsave=dioval;
return 0;
}
static void put_cmd640_reg_pci1(int reg_no, int val)
{
unsigned long flags;
save_flags(flags);
cli();
outl_p((reg_no & 0xfc) | cmd640_key, 0xcf8);
outb_p(val, (reg_no & 3) + 0xcfc);
restore_flags(flags);
}
static void output(int cs, int clock, int dataout)
{
uint32_t value = 0x10 /* enable outputs */ |
(cs ? 8 : 0) | (clock ? 4 : 0) | (dataout ? 2 : 0);
#if DEBUG
fprintf(stderr, " %c%c%c ", cs ? ' ' : '-', clock ? 'c' : ' ',
dataout ? '1' : '0');
#endif
outl_p(value, io_ports + 0x20);
}
static byte get_cmd640_reg_pci1(int reg_no)
{
byte b;
unsigned long flags;
save_flags(flags);
cli();
outl_p((reg_no & 0xfc) | cmd640_key, 0xcf8);
b = inb_p(0xcfc + (reg_no & 3));
restore_flags(flags);
return b;
}
static PyObject *
chwtest_outlw(PyObject *self, PyObject *args)
{
unsigned long int address;
unsigned long int value;
if (!PyArg_ParseTuple(args, "ll", &address, &value)) {
return NULL;
}
outl_p(value, address);
Py_RETURN_NONE;
}
static u8 get_cmd640_reg_pci1(u16 reg)
{
outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
return inb_p((reg & 3) | 0xcfc);
}
static void put_cmd640_reg_pci1(u16 reg, u8 val)
{
outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
outb_p(val, (reg & 3) | 0xcfc);
}
/* interrupt handler for minor device 2, 3 and 4 */
static irqreturn_t interrupt_handler(int irq, void *dev_id ){
/*, struct pt_regs *regs) { old style */
static unsigned long ad,intreg,ad1,ad2,intreg2,tmpval;
ad1=dma_engine_base+DMA_ENGINE_INTCSR;
intreg=inl(ad1); /* interrupt status reg */
if (intreg & S5933_INTCSR_int_asserted) {
spin_lock(&irq_lock);
/* check for extrnal input */
if ((intreg & S5933_INTCSR_write_complete) && (IOCARD_USAGE_MODE<4)) {
/* check if dma should continue to run */
if (dma_should_run) {
dma_int_use_counter++; /* once is enough since int handler is atomic */
/* set new physical address: */
ad=dma_engine_base+DMA_ENGINE_MWAR;
outl(next_to_use_ptr->physbuf,ad);
/* set size of dma transfer */
ad=dma_engine_base+DMA_ENGINE_MWTC;
outl(next_to_use_ptr->size,ad);
/* restart dma engine (nothing to do, was done writing size?? */
already_transfered_bytes+=next_to_use_ptr->previous->size;
next_to_use_ptr=next_to_use_ptr->next; /* prepare next buffer */
}
}
if ((intreg & S5933_INTCSR_read_complete)&&(IOCARD_USAGE_MODE>3)) {
/* check if dma should continue to run */
if (dma_should_run) {
dma_int_use_counter++; /* once is enough since int handler is atomic */
/* set new physical address: */
ad=dma_engine_base+DMA_ENGINE_MRAR;
outl(next_to_use_ptr->physbuf,ad);
/* set size of dma transfer */
ad=dma_engine_base+DMA_ENGINE_MRTC;
outl(next_to_use_ptr->size,ad);
/* restart dma engine (nothing to do, was done writing size?? */
already_transfered_bytes+=next_to_use_ptr->previous->size;
next_to_use_ptr=next_to_use_ptr->next; /* prepare next buffer */
}
}
/* irqs from the nudaq proprietary circuitry for minor device 3 */
if (intreg & S5933_INTCSR_incoming_mail) {
ad2=iocard_base+IOCARD_INT_STATUS; /* read in this irqreg */
intreg2=inl(ad2);
if (intreg2 & IOCARD_INT_STATMASK) { /* came from nudaq */
/* nudaq fpga interupt handler */
outl(intreg2 | IOCARD_INT_STATMASK, ad2);
/* disable data acquisition */
if (IOCARD_USAGE_MODE==3) {
tmpval=inl(iocard_base+IOCARD_DIGIOUT) & ~0x2;
outl(tmpval,iocard_base+IOCARD_DIGIOUT);
}
/* tell what happened */
kill_fasync(&my_async_queue, SIGIO, POLL_IN);
/* clear Nudaq proprietary irq source */
outl(intreg2,ad2);
}
}
/* now clear all irqs from the AMCC source */
outl_p(intreg, ad1);
spin_unlock(&irq_lock);
return IRQ_HANDLED;
}
return IRQ_NONE;
};
int main (int argc, char *argv[])
{
struct pci_access *pacc;
struct pci_dev *dev;
struct pci_filter filter;
char *msg;
uint16_t command;
int v1_1 = 0, i2c;
if (argc != 2 &&
((argc != 3) ||
(!(v1_1 = !strcmp(argv[2], "1.1")) && strcmp(argv[2], "1.0")))) {
fprintf(stderr,
"VT6307 OHCI mode config\n"
"Version 0.9\n"
"Copyright (C) 2007 Krzysztof Halasa <*****@*****.**>\n"
"\n"
"Usage: vt6307ohciver <pci_device> [ 1.0 | 1.1 ]\n");
exit(1);
}
if (iopl(3)) {
fprintf(stderr, "iopl() failed (must be root)\n");
exit(1);
}
pacc = pci_alloc();
pci_filter_init(pacc, &filter);
if ((msg = pci_filter_parse_slot(&filter, argv[1]))) {
fprintf(stderr, "Invalid pci_device\n");
exit(1);
}
filter.vendor = VENDOR_ID;
filter.device = DEVICE_ID;
pci_init(pacc);
pci_scan_bus(pacc);
for (dev = pacc->devices; dev; dev = dev->next)
if (pci_filter_match(&filter, dev))
break;
if (!dev) {
fprintf(stderr, "Device %s not found\n", argv[2]);
exit(1);
}
pci_fill_info(dev, PCI_FILL_BASES | PCI_FILL_SIZES);
if (dev->size[0] != MEM_SIZE || dev->size[1] != IO_SIZE) {
fprintf(stderr, "Unexpected MEM/IO region size, is it"
" VT6307 chip?\n");
exit(1);
}
command = pci_read_word(dev, PCI_COMMAND);
if ((command & PCI_COMMAND_IO) == 0) {
fprintf(stderr, "Device disabled, trying to enable it\n");
pci_write_word(dev, PCI_COMMAND, command | PCI_COMMAND_IO);
}
io_ports = dev->base_addr[1] & PCI_BASE_ADDRESS_IO_MASK;
i2c = (inl(io_ports + 0x20) & 0x80) ? 0 : 1;
fprintf(stderr, "I/O region #1 is at %04X\n", io_ports);
fprintf(stderr, "It seems your VT6307 chip is connected to %s "
"EEPROM\n", i2c ? "I^2C (24c01 or similar)" : "93c46");
if (argc == 3) {
/* enable direct access to pins */
outl_p(inl(io_ports) | 0x80, io_ports);
if (i2c)
write_i2c(0x22, v1_1 ? 8 : 0);
else
write_4w(0x11, v1_1 ? 8 : 0);
/* disable direct access to pins */
outl_p(0x20, io_ports + 0x20);
fprintf(stderr, "Please reboot\n");
} else
display(dev->base_addr[0] & PCI_BASE_ADDRESS_MEM_MASK);
if ((command & PCI_COMMAND_IO) == 0) {
fprintf(stderr, "Disabling device\n");
pci_write_word(dev, PCI_COMMAND, command);
}
exit(0);
}
DLLEXPORT void hal_outl_p(unsigned int val, unsigned long port)
{
outl_p(val, port);
}
