STDCALL void WRAP_EXPORT(WRITE_PORT_USHORT)
(ULONG_PTR port, USHORT value)
{
outw(value, port);
}
static inline void
mikasa_update_irq_hw(int mask)
{
outw(mask, 0x536);
}
static inline void
Write_hfc16(hfc4s8s_hw * a, u_char b, u_short c)
{
SetRegAddr(a, b);
outw(c, a->iobase);
}
static void vx800_writesioword(uint16_t reg, uint16_t val)
{
outw(val, reg);
}
__initfunc(static int seeq8005_probe1(struct device *dev, int ioaddr))
{
static unsigned version_printed = 0;
int i,j;
unsigned char SA_prom[32];
int old_cfg1;
int old_cfg2;
int old_stat;
int old_dmaar;
int old_rear;
if (net_debug>1)
printk("seeq8005: probing at 0x%x\n",ioaddr);
old_stat = inw(SEEQ_STATUS); /* read status register */
if (old_stat == 0xffff)
return ENODEV; /* assume that 0xffff == no device */
if ( (old_stat & 0x1800) != 0x1800 ) { /* assume that unused bits are 1, as my manual says */
if (net_debug>1) {
printk("seeq8005: reserved stat bits != 0x1800\n");
printk(" == 0x%04x\n",old_stat);
}
return ENODEV;
}
old_rear = inw(SEEQ_REA);
if (old_rear == 0xffff) {
outw(0,SEEQ_REA);
if (inw(SEEQ_REA) == 0xffff) { /* assume that 0xffff == no device */
return ENODEV;
}
} else if ((old_rear & 0xff00) != 0xff00) { /* assume that unused bits are 1 */
if (net_debug>1) {
printk("seeq8005: unused rear bits != 0xff00\n");
printk(" == 0x%04x\n",old_rear);
}
return ENODEV;
}
old_cfg2 = inw(SEEQ_CFG2); /* read CFG2 register */
old_cfg1 = inw(SEEQ_CFG1);
old_dmaar = inw(SEEQ_DMAAR);
if (net_debug>4) {
printk("seeq8005: stat = 0x%04x\n",old_stat);
printk("seeq8005: cfg1 = 0x%04x\n",old_cfg1);
printk("seeq8005: cfg2 = 0x%04x\n",old_cfg2);
printk("seeq8005: raer = 0x%04x\n",old_rear);
printk("seeq8005: dmaar= 0x%04x\n",old_dmaar);
}
outw( SEEQCMD_FIFO_WRITE | SEEQCMD_SET_ALL_OFF, SEEQ_CMD); /* setup for reading PROM */
outw( 0, SEEQ_DMAAR); /* set starting PROM address */
outw( SEEQCFG1_BUFFER_PROM, SEEQ_CFG1); /* set buffer to look at PROM */
j=0;
for(i=0; i <32; i++) {
j+= SA_prom[i] = inw(SEEQ_BUFFER) & 0xff;
}
#if 0
/* untested because I only have the one card */
if ( (j&0xff) != 0 ) { /* checksum appears to be 8bit = 0 */
if (net_debug>1) { /* check this before deciding that we have a card */
printk("seeq8005: prom sum error\n");
}
outw( old_stat, SEEQ_STATUS);
outw( old_dmaar, SEEQ_DMAAR);
outw( old_cfg1, SEEQ_CFG1);
return ENODEV;
}
#endif
outw( SEEQCFG2_RESET, SEEQ_CFG2); /* reset the card */
udelay(5);
outw( SEEQCMD_SET_ALL_OFF, SEEQ_CMD);
if (net_debug) {
printk("seeq8005: prom sum = 0x%08x\n",j);
for(j=0; j<32; j+=16) {
printk("seeq8005: prom %02x: ",j);
for(i=0;i<16;i++) {
printk("%02x ",SA_prom[j|i]);
}
printk(" ");
for(i=0;i<16;i++) {
if ((SA_prom[j|i]>31)&&(SA_prom[j|i]<127)) {
printk("%c", SA_prom[j|i]);
} else {
printk(" ");
}
}
printk("\n");
}
}
#if 0
/*
* testing the packet buffer memory doesn't work yet
* but all other buffer accesses do
* - fixing is not a priority
*/
if (net_debug>1) { /* test packet buffer memory */
printk("seeq8005: testing packet buffer ... ");
outw( SEEQCFG1_BUFFER_BUFFER, SEEQ_CFG1);
outw( SEEQCMD_FIFO_WRITE | SEEQCMD_SET_ALL_OFF, SEEQ_CMD);
outw( 0 , SEEQ_DMAAR);
for(i=0;i<32768;i++) {
outw(0x5a5a, SEEQ_BUFFER);
}
j=jiffies+HZ;
while ( ((inw(SEEQ_STATUS) & SEEQSTAT_FIFO_EMPTY) != SEEQSTAT_FIFO_EMPTY) && time_before(jiffies, j) )
mb();
outw( 0 , SEEQ_DMAAR);
while ( ((inw(SEEQ_STATUS) & SEEQSTAT_WINDOW_INT) != SEEQSTAT_WINDOW_INT) && time_before(jiffies, j+HZ))
mb();
if ( (inw(SEEQ_STATUS) & SEEQSTAT_WINDOW_INT) == SEEQSTAT_WINDOW_INT)
outw( SEEQCMD_WINDOW_INT_ACK | (inw(SEEQ_STATUS)& SEEQCMD_INT_MASK), SEEQ_CMD);
outw( SEEQCMD_FIFO_READ | SEEQCMD_SET_ALL_OFF, SEEQ_CMD);
j=0;
for(i=0;i<32768;i++) {
if (inw(SEEQ_BUFFER) != 0x5a5a)
j++;
}
if (j) {
printk("%i\n",j);
} else {
printk("ok.\n");
}
}
#endif
/* Allocate a new 'dev' if needed. */
if (dev == NULL)
dev = init_etherdev(0, sizeof(struct net_local));
if (net_debug && version_printed++ == 0)
printk(version);
printk("%s: %s found at %#3x, ", dev->name, "seeq8005", ioaddr);
/* Fill in the 'dev' fields. */
dev->base_addr = ioaddr;
/* Retrieve and print the ethernet address. */
for (i = 0; i < 6; i++)
printk(" %2.2x", dev->dev_addr[i] = SA_prom[i+6]);
if (dev->irq == 0xff)
; /* Do nothing: a user-level program will set it. */
else if (dev->irq < 2) { /* "Auto-IRQ" */
autoirq_setup(0);
outw( SEEQCMD_RX_INT_EN | SEEQCMD_SET_RX_ON | SEEQCMD_SET_RX_OFF, SEEQ_CMD );
dev->irq = autoirq_report(0);
if (net_debug >= 2)
printk(" autoirq is %d\n", dev->irq);
} else if (dev->irq == 2)
/* Fixup for users that don't know that IRQ 2 is really IRQ 9,
* or don't know which one to set.
*/
dev->irq = 9;
#if 0
{
int irqval = request_irq(dev->irq, &seeq8005_interrupt, 0, "seeq8005", dev);
if (irqval) {
printk ("%s: unable to get IRQ %d (irqval=%d).\n", dev->name,
dev->irq, irqval);
return EAGAIN;
}
}
#endif
/* Grab the region so we can find another board if autoIRQ fails. */
request_region(ioaddr, SEEQ8005_IO_EXTENT,"seeq8005");
/* Initialize the device structure. */
dev->priv = kmalloc(sizeof(struct net_local), GFP_KERNEL);
if (dev->priv == NULL)
return -ENOMEM;
memset(dev->priv, 0, sizeof(struct net_local));
dev->open = seeq8005_open;
dev->stop = seeq8005_close;
dev->hard_start_xmit = seeq8005_send_packet;
dev->get_stats = seeq8005_get_stats;
dev->set_multicast_list = &set_multicast_list;
/* Fill in the fields of the device structure with ethernet values. */
ether_setup(dev);
dev->flags &= ~IFF_MULTICAST;
return 0;
}
static void
eesoxscsi_dma_pseudo(struct Scsi_Host *host, Scsi_Pointer *SCp,
fasdmadir_t dir, int transfer_size)
{
EESOXScsi_Info *info = (EESOXScsi_Info *)host->hostdata;
unsigned int status;
unsigned int length = SCp->this_residual;
union {
unsigned char *c;
unsigned short *s;
unsigned long *l;
} buffer;
buffer.c = SCp->ptr;
status = inb(host->io_port + EESOX_STATUS);
if (dir == DMA_IN) {
while (length > 8) {
if (status & EESOX_STAT_DMA) {
unsigned long l1, l2;
l1 = inw(info->dmaarea);
l1 |= inw(info->dmaarea) << 16;
l2 = inw(info->dmaarea);
l2 |= inw(info->dmaarea) << 16;
*buffer.l++ = l1;
*buffer.l++ = l2;
length -= 8;
} else if (status & EESOX_STAT_INTR)
goto end;
status = inb(host->io_port + EESOX_STATUS);
}
while (length > 1) {
if (status & EESOX_STAT_DMA) {
*buffer.s++ = inw(info->dmaarea);
length -= 2;
} else if (status & EESOX_STAT_INTR)
goto end;
status = inb(host->io_port + EESOX_STATUS);
}
while (length > 0) {
if (status & EESOX_STAT_DMA) {
*buffer.c++ = inw(info->dmaarea);
length -= 1;
} else if (status & EESOX_STAT_INTR)
goto end;
status = inb(host->io_port + EESOX_STATUS);
}
} else {
while (length > 8) {
if (status & EESOX_STAT_DMA) {
unsigned long l1, l2;
l1 = *buffer.l++;
l2 = *buffer.l++;
outw(l1, info->dmaarea);
outw(l1 >> 16, info->dmaarea);
outw(l2, info->dmaarea);
outw(l2 >> 16, info->dmaarea);
length -= 8;
} else if (status & EESOX_STAT_INTR)
goto end;
status = inb(host->io_port + EESOX_STATUS);
}
int
system_call_implementation(void)
{
register int schedule=0;
/*!< System calls may set this variable to 1. The variable is used as
input to the scheduler to indicate if scheduling is necessary. */
switch(SYSCALL_ARGUMENTS.rax)
{
case SYSCALL_PRINTS:
{
kprints((char*) (SYSCALL_ARGUMENTS.rdi));
SYSCALL_ARGUMENTS.rax = ALL_OK;
break;
}
case SYSCALL_PRINTHEX:
{
kprinthex(SYSCALL_ARGUMENTS.rdi);
SYSCALL_ARGUMENTS.rax = ALL_OK;
break;
}
case SYSCALL_DEBUGGER:
{
/* Enable the bochs iodevice and force a return to the debugger. */
outw(0x8a00, 0x8a00);
outw(0x8a00, 0x8ae0);
SYSCALL_ARGUMENTS.rax = ALL_OK;
break;
}
case SYSCALL_VERSION: {
SYSCALL_ARGUMENTS.rax = KERNEL_VERSION;
break;
}
case SYSCALL_CREATEPROCESS: {
int process_number, thread_number;
long int executable_number = SYSCALL_ARGUMENTS.rdi;
struct prepare_process_return_value prepare_process_ret_val;
for (process_number = 0; process_number < MAX_NUMBER_OF_PROCESSES && process_table[process_number].threads > 0; process_number++) {
}
prepare_process_ret_val = prepare_process(
executable_table[executable_number].elf_image,
process_number,
executable_table[executable_number].memory_footprint_size);
if(0 == prepare_process_ret_val.first_instruction_address) {
kprints("Error starting image\n");
}
process_table[process_number].parent = thread_table[cpu_private_data.thread_index].data.owner;
thread_number = allocate_thread();
thread_table[thread_number].data.owner = process_number;
thread_table[thread_number].data.registers.integer_registers.rflags = 0x200;
thread_table[thread_number].data.registers.integer_registers.rip = prepare_process_ret_val.first_instruction_address;
process_table[process_number].threads += 1;
SYSCALL_ARGUMENTS.rax = ALL_OK;
thread_queue_enqueue(&ready_queue,thread_number);
/*cpu_private_data.thread_index = thread_number;*/
break;
}
case SYSCALL_TERMINATE:
{
int i;
int owner_process = thread_table[cpu_private_data.thread_index].data.owner;
int parent_process = process_table[owner_process].parent;
thread_table[cpu_private_data.thread_index].data.owner = -1; /* Terminate Thread */
process_table[owner_process].threads -= 1; /* Decrement Thread count */
if(process_table[owner_process].threads < 1) {
cleanup_process(owner_process);
}
for(i=0; i < MAX_NUMBER_OF_THREADS && thread_table[i].data.owner != parent_process; i++) {
}
/*cpu_private_data.thread_index = i;*/
/*thread_queue_dequeue(&ready_queue);*/
schedule = 1;
break;
}
/* Do not touch any lines above or including this line. */
/* Add the implementation of more system calls here. */
/* Do not touch any lines below or including this line. */
default:
{
/* No system call defined. */
SYSCALL_ARGUMENTS.rax = ERROR_ILLEGAL_SYSCALL;
}
}
return schedule;
}
static int me8100_di_io_irq_start(me_subdevice_t *subdevice,
struct file *filep,
int channel,
int irq_source,
int irq_edge, int irq_arg, int flags)
{
me8100_di_subdevice_t *instance;
int err = ME_ERRNO_SUCCESS;
uint16_t ctrl;
unsigned long cpu_flags;
PDEBUG("executed.\n");
instance = (me8100_di_subdevice_t *) subdevice;
if (irq_source == ME_IRQ_SOURCE_DIO_PATTERN) {
if (flags &
~(ME_IO_IRQ_START_PATTERN_FILTERING |
ME_IO_IRQ_START_DIO_WORD)) {
PERROR("Invalid flag specified.\n");
return ME_ERRNO_INVALID_FLAGS;
}
if (irq_edge != ME_IRQ_EDGE_NOT_USED) {
PERROR("Invalid irq edge specified.\n");
return ME_ERRNO_INVALID_IRQ_EDGE;
}
} else if (irq_source == ME_IRQ_SOURCE_DIO_MASK) {
if (flags &
~(ME_IO_IRQ_START_EXTENDED_STATUS |
ME_IO_IRQ_START_DIO_WORD)) {
PERROR("Invalid flag specified.\n");
return ME_ERRNO_INVALID_FLAGS;
}
if (irq_edge != ME_IRQ_EDGE_ANY) {
PERROR("Invalid irq edge specified.\n");
return ME_ERRNO_INVALID_IRQ_EDGE;
}
if (!(irq_arg & 0xFFFF)) {
PERROR("No mask specified.\n");
return ME_ERRNO_INVALID_IRQ_ARG;
}
} else {
PERROR("Invalid irq source specified.\n");
return ME_ERRNO_INVALID_IRQ_SOURCE;
}
if (channel) {
PERROR("Invalid channel specified.\n");
return ME_ERRNO_INVALID_CHANNEL;
}
ME_SUBDEVICE_ENTER;
spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
if (irq_source == ME_IRQ_SOURCE_DIO_PATTERN) {
outw(irq_arg, instance->pattern_reg);
instance->compare_value = irq_arg;
instance->filtering_flag =
(flags & ME_IO_IRQ_START_PATTERN_FILTERING) ? 1 : 0;
}
if (irq_source == ME_IRQ_SOURCE_DIO_MASK) {
outw(irq_arg, instance->mask_reg);
}
spin_lock(instance->ctrl_reg_lock);
ctrl = inw(instance->ctrl_reg);
ctrl |= ME8100_DIO_CTRL_BIT_INTB_0;
if (irq_source == ME_IRQ_SOURCE_DIO_PATTERN) {
ctrl &= ~ME8100_DIO_CTRL_BIT_INTB_1;
}
if (irq_source == ME_IRQ_SOURCE_DIO_MASK) {
ctrl |= ME8100_DIO_CTRL_BIT_INTB_1;
}
outw(ctrl, instance->ctrl_reg);
PDEBUG_REG("ctrl_reg outw(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
instance->ctrl_reg - instance->reg_base, ctrl);
spin_unlock(instance->ctrl_reg_lock);
instance->rised = 0;
instance->status_value = 0;
instance->status_value_edges = 0;
instance->line_value = inw(instance->port_reg);
instance->status_flag = flags & ME_IO_IRQ_START_EXTENDED_STATUS;
spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
ME_SUBDEVICE_EXIT;
return err;
}
static struct sal_ret_values
sal_emulator (long index, unsigned long in1, unsigned long in2,
unsigned long in3, unsigned long in4, unsigned long in5,
unsigned long in6, unsigned long in7)
{
long r9 = 0;
long r10 = 0;
long r11 = 0;
long status;
/*
* Don't do a "switch" here since that gives us code that
* isn't self-relocatable.
*/
status = 0;
if (index == SAL_FREQ_BASE) {
if (in1 == SAL_FREQ_BASE_PLATFORM)
r9 = 200000000;
else if (in1 == SAL_FREQ_BASE_INTERVAL_TIMER) {
/*
* Is this supposed to be the cr.itc frequency
* or something platform specific? The SAL
* doc ain't exactly clear on this...
*/
r9 = 700000000;
} else if (in1 == SAL_FREQ_BASE_REALTIME_CLOCK)
r9 = 1;
else
status = -1;
} else if (index == SAL_SET_VECTORS) {
;
} else if (index == SAL_GET_STATE_INFO) {
;
} else if (index == SAL_GET_STATE_INFO_SIZE) {
;
} else if (index == SAL_CLEAR_STATE_INFO) {
;
} else if (index == SAL_MC_RENDEZ) {
;
} else if (index == SAL_MC_SET_PARAMS) {
;
} else if (index == SAL_CACHE_FLUSH) {
;
} else if (index == SAL_CACHE_INIT) {
;
#ifdef CONFIG_PCI
} else if (index == SAL_PCI_CONFIG_READ) {
/*
* in1 contains the PCI configuration address and in2
* the size of the read. The value that is read is
* returned via the general register r9.
*/
outl(BUILD_CMD(in1), 0xCF8);
if (in2 == 1) /* Reading byte */
r9 = inb(0xCFC + ((REG_OFFSET(in1) & 3)));
else if (in2 == 2) /* Reading word */
r9 = inw(0xCFC + ((REG_OFFSET(in1) & 2)));
else /* Reading dword */
r9 = inl(0xCFC);
status = PCIBIOS_SUCCESSFUL;
} else if (index == SAL_PCI_CONFIG_WRITE) {
/*
* in1 contains the PCI configuration address, in2 the
* size of the write, and in3 the actual value to be
* written out.
*/
outl(BUILD_CMD(in1), 0xCF8);
if (in2 == 1) /* Writing byte */
outb(in3, 0xCFC + ((REG_OFFSET(in1) & 3)));
else if (in2 == 2) /* Writing word */
outw(in3, 0xCFC + ((REG_OFFSET(in1) & 2)));
else /* Writing dword */
outl(in3, 0xCFC);
status = PCIBIOS_SUCCESSFUL;
#endif /* CONFIG_PCI */
} else if (index == SAL_UPDATE_PAL) {
;
} else {
status = -1;
}
return ((struct sal_ret_values) {status, r9, r10, r11});
/* byte 1 and 2 is the port number to write
* and at byte 3 the value to write starts.
* I assume that there are and- and or- masks
* here when HPEE_PORT_INIT_MASK is set but I have
* not yet encountered this. */
static int configure_port_init(const unsigned char *buf)
{
int len=0;
u_int8_t c;
while (len<HPEE_PORT_INIT_MAX_LEN) {
int s=0;
c = get_8(buf+len);
switch (c & HPEE_PORT_INIT_WIDTH_MASK) {
case HPEE_PORT_INIT_WIDTH_BYTE:
s=1;
if (c & HPEE_PORT_INIT_MASK) {
printk("\n" KERN_WARNING "port_init: unverified mask attribute\n");
outb((inb(get_16(buf+len+1) &
get_8(buf+len+3)) |
get_8(buf+len+4)), get_16(buf+len+1));
} else {
outb(get_8(buf+len+3), get_16(buf+len+1));
}
break;
case HPEE_PORT_INIT_WIDTH_WORD:
s=2;
if (c & HPEE_PORT_INIT_MASK) {
printk(KERN_WARNING "port_init: unverified mask attribute\n");
outw((inw(get_16(buf+len+1)) &
get_16(buf+len+3)) |
get_16(buf+len+5),
get_16(buf+len+1));
} else {
outw(cpu_to_le16(get_16(buf+len+3)), get_16(buf+len+1));
}
break;
case HPEE_PORT_INIT_WIDTH_DWORD:
s=4;
if (c & HPEE_PORT_INIT_MASK) {
printk("\n" KERN_WARNING "port_init: unverified mask attribute\n");
outl((inl(get_16(buf+len+1) &
get_32(buf+len+3)) |
get_32(buf+len+7)), get_16(buf+len+1));
} else {
outl(cpu_to_le32(get_32(buf+len+3)), get_16(buf+len+1));
}
break;
default:
printk("\n" KERN_ERR "Invalid port init word %02x\n", c);
return 0;
}
if (c & HPEE_PORT_INIT_MASK) {
s*=2;
}
len+=s+3;
if (!(c & HPEE_PORT_INIT_MORE)) {
break;
}
}
return len;
}
static void cx700_writesioword(u16 reg, u16 val)
{
outw(val, reg);
}
void oxygen_write16(struct oxygen *chip, unsigned int reg, u16 value)
{
outw(value, chip->addr + reg);
chip->saved_registers._16[reg / 2] = cpu_to_le16(value);
}
void vbgfx_set_res(vga_card* v, int64_t w, int64_t h, uint8_t bpp)
{
if(!v) return;
if(!v->data[0]) return;
if(w * h > 1440000) return;
uint32_t iobase = v->data[0];
outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_ENABLE);
outw(iobase + VBGFX_IO_DATA, 0); //disable VBE extensions
//write resolution
outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_XRES);
outw(iobase + VBGFX_IO_DATA, w);
outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_YRES);
outw(iobase + VBGFX_IO_DATA, h);
//write bpp
outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_BPP);
outw(iobase + VBGFX_IO_DATA, bpp);
//reset video module
vdestroy();
//enable VBE extensions and LFB
outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_ENABLE);
outw(iobase + VBGFX_IO_DATA, 1 | 0x40);
//init video module
int64_t width, height, bppix;
uint32_t lfb_addr = pci_config_read_dword(v->bus, v->slot, 0, 0x10) & ~0xF;
outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_XRES);
width = inw(iobase + VBGFX_IO_DATA);
outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_YRES);
height = inw(iobase + VBGFX_IO_DATA);
outw(iobase + VBGFX_IO_INDEX, VBGFX_INDEX_BPP);
bppix = inl(iobase + VBGFX_IO_DATA);
vinit(width, height, bppix, w * 4, lfb_addr);
}
static void InitBoard(struct net_device *dev)
{
ibmlana_priv *priv = netdev_priv(dev);
int camcnt;
camentry_t cams[16];
u32 cammask;
struct dev_mc_list *mcptr;
u16 rcrval;
/* reset the SONIC */
outw(CMDREG_RST, dev->base_addr + SONIC_CMDREG);
udelay(10);
/* clear all spurious interrupts */
outw(inw(dev->base_addr + SONIC_ISREG), dev->base_addr + SONIC_ISREG);
/* set up the SONIC's bus interface - constant for this adapter -
must be done while the SONIC is in reset */
outw(DCREG_USR1 | DCREG_USR0 | DCREG_WC1 | DCREG_DW32, dev->base_addr + SONIC_DCREG);
outw(0, dev->base_addr + SONIC_DCREG2);
/* remove reset form the SONIC */
outw(0, dev->base_addr + SONIC_CMDREG);
udelay(10);
/* data sheet requires URRA to be programmed before setting up the CAM contents */
outw(0, dev->base_addr + SONIC_URRA);
/* program the CAM entry 0 to the device address */
camcnt = 0;
putcam(cams, &camcnt, dev->dev_addr);
/* start putting the multicast addresses into the CAM list. Stop if
it is full. */
for (mcptr = dev->mc_list; mcptr != NULL; mcptr = mcptr->next) {
putcam(cams, &camcnt, mcptr->dmi_addr);
if (camcnt == 16)
break;
}
/* calculate CAM mask */
cammask = (1 << camcnt) - 1;
/* feed CDA into SONIC, initialize RCR value (always get broadcasts) */
memcpy_toio(priv->base, cams, sizeof(camentry_t) * camcnt);
memcpy_toio(priv->base + (sizeof(camentry_t) * camcnt), &cammask, sizeof(cammask));
#ifdef DEBUG
printk("CAM setup:\n");
dumpmem(dev, 0, sizeof(camentry_t) * camcnt + sizeof(cammask));
#endif
outw(0, dev->base_addr + SONIC_CAMPTR);
outw(camcnt, dev->base_addr + SONIC_CAMCNT);
outw(CMDREG_LCAM, dev->base_addr + SONIC_CMDREG);
if (!wait_timeout(dev, SONIC_CMDREG, CMDREG_LCAM, 0, 2)) {
printk(KERN_ERR "%s:SONIC did not respond on LCAM command - giving up.", dev->name);
return;
} else {
/* clear interrupt condition */
outw(ISREG_LCD, dev->base_addr + SONIC_ISREG);
#ifdef DEBUG
printk("Loading CAM done, address pointers %04x:%04x\n",
inw(dev->base_addr + SONIC_URRA),
inw(dev->base_addr + SONIC_CAMPTR));
{
int z;
printk("\n-->CAM: PTR %04x CNT %04x\n",
inw(dev->base_addr + SONIC_CAMPTR),
inw(dev->base_addr + SONIC_CAMCNT));
outw(CMDREG_RST, dev->base_addr + SONIC_CMDREG);
for (z = 0; z < camcnt; z++) {
outw(z, dev->base_addr + SONIC_CAMEPTR);
printk("Entry %d: %04x %04x %04x\n", z,
inw(dev->base_addr + SONIC_CAMADDR0),
inw(dev->base_addr + SONIC_CAMADDR1),
inw(dev->base_addr + SONIC_CAMADDR2));
}
outw(0, dev->base_addr + SONIC_CMDREG);
}
#endif
}
rcrval = RCREG_BRD | RCREG_LB_NONE;
/* if still multicast addresses left or ALLMULTI is set, set the multicast
enable bit */
if ((dev->flags & IFF_ALLMULTI) || (mcptr != NULL))
rcrval |= RCREG_AMC;
/* promiscous mode ? */
if (dev->flags & IFF_PROMISC)
rcrval |= RCREG_PRO;
/* program receive mode */
outw(rcrval, dev->base_addr + SONIC_RCREG);
#ifdef DEBUG
printk("\nRCRVAL: %04x\n", rcrval);
#endif
/* set up descriptors in shared memory + feed them into SONIC registers */
InitDscrs(dev);
if (!InitSONIC(dev))
return;
/* reset all pending interrupts */
outw(0xffff, dev->base_addr + SONIC_ISREG);
/* enable transmitter + receiver interrupts */
outw(CMDREG_RXEN, dev->base_addr + SONIC_CMDREG);
outw(IMREG_PRXEN | IMREG_RBEEN | IMREG_PTXEN | IMREG_TXEREN, dev->base_addr + SONIC_IMREG);
/* turn on card interrupts */
outb(inb(dev->base_addr + BCMREG) | BCMREG_IEN, dev->base_addr + BCMREG);
#ifdef DEBUG
printk("Register dump after initialization:\n");
dumpregs(dev);
#endif
}
/* Handle the 21143 uniquely: do autoselect with NWay, not the EEPROM list
of available transceivers. */
void t21142_timer(unsigned long data)
{
#if 0
/*RTnet*/struct rtnet_device *rtdev = (/*RTnet*/struct rtnet_device *)data;
struct tulip_private *tp = (struct tulip_private *)rtdev->priv;
long ioaddr = rtdev->base_addr;
int csr12 = inl(ioaddr + CSR12);
int next_tick = 60*HZ;
int new_csr6 = 0;
if (tulip_debug > 2)
/*RTnet*/rtdm_printk(KERN_INFO"%s: 21143 negotiation status %8.8x, %s.\n",
rtdev->name, csr12, medianame[rtdev->if_port]);
if (tulip_media_cap[rtdev->if_port] & MediaIsMII) {
tulip_check_duplex(dev);
next_tick = 60*HZ;
} else if (tp->nwayset) {
/* Don't screw up a negotiated session! */
if (tulip_debug > 1)
/*RTnet*/rtdm_printk(KERN_INFO"%s: Using NWay-set %s media, csr12 %8.8x.\n",
rtdev->name, medianame[rtdev->if_port], csr12);
} else if (tp->medialock) {
;
} else if (rtdev->if_port == 3) {
if (csr12 & 2) { /* No 100mbps link beat, revert to 10mbps. */
if (tulip_debug > 1)
/*RTnet*/rtdm_printk(KERN_INFO"%s: No 21143 100baseTx link beat, %8.8x, "
"trying NWay.\n", rtdev->name, csr12);
t21142_start_nway(dev);
next_tick = 3*HZ;
}
} else if ((csr12 & 0x7000) != 0x5000) {
/* Negotiation failed. Search media types. */
if (tulip_debug > 1)
/*RTnet*/rtdm_printk(KERN_INFO"%s: 21143 negotiation failed, status %8.8x.\n",
rtdev->name, csr12);
if (!(csr12 & 4)) { /* 10mbps link beat good. */
new_csr6 = 0x82420000;
rtdev->if_port = 0;
outl(0, ioaddr + CSR13);
outl(0x0003FFFF, ioaddr + CSR14);
outw(t21142_csr15[rtdev->if_port], ioaddr + CSR15);
outl(t21142_csr13[rtdev->if_port], ioaddr + CSR13);
} else {
/* Select 100mbps port to check for link beat. */
new_csr6 = 0x83860000;
rtdev->if_port = 3;
outl(0, ioaddr + CSR13);
outl(0x0003FF7F, ioaddr + CSR14);
outw(8, ioaddr + CSR15);
outl(1, ioaddr + CSR13);
}
if (tulip_debug > 1)
/*RTnet*/rtdm_printk(KERN_INFO"%s: Testing new 21143 media %s.\n",
rtdev->name, medianame[rtdev->if_port]);
if (new_csr6 != (tp->csr6 & ~0x00D5)) {
tp->csr6 &= 0x00D5;
tp->csr6 |= new_csr6;
outl(0x0301, ioaddr + CSR12);
tulip_restart_rxtx(tp);
}
next_tick = 3*HZ;
}
/* mod_timer synchronizes us with potential add_timer calls
* from interrupts.
*/
/*RTnet*/MUST_REMOVE_mod_timer(&tp->timer, RUN_AT(next_tick));
#endif
}
void led_set_state(unsigned short value)
{
outw(value & 0xFF, LED_BASE);
}
static inline void outw_data(unsigned int val, unsigned int base_addr)
{
outw(val, base_addr + PORT_DATA);
}
static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
{
outw(data, reg);
pr_debug("m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
}
/*----------------------------------------------------------------
* prism2sta_probe_pci
*
* Probe routine called when a PCI device w/ matching ID is found.
* The ISL3874 implementation uses the following map:
* BAR0: Prism2.x registers memory mapped, size=4k
* Here's the sequence:
* - Allocate the PCI resources.
* - Read the PCMCIA attribute memory to make sure we have a WLAN card
* - Reset the MAC
* - Initialize the netdev and wlan data
* - Initialize the MAC
*
* Arguments:
* pdev ptr to pci device structure containing info about
* pci configuration.
* id ptr to the device id entry that matched this device.
*
* Returns:
* zero - success
* negative - failed
*
* Side effects:
*
*
* Call context:
* process thread
*
----------------------------------------------------------------*/
static int __devinit
prism2sta_probe_pci(
struct pci_dev *pdev,
const struct pci_device_id *id)
{
int result;
phys_t phymem = 0;
void *mem = NULL;
wlandevice_t *wlandev = NULL;
hfa384x_t *hw = NULL;
DBFENTER;
/* Enable the pci device */
if (pci_enable_device(pdev)) {
WLAN_LOG_ERROR("%s: pci_enable_device() failed.\n", dev_info);
result = -EIO;
goto fail;
}
/* Figure out our resources */
phymem = pci_resource_start(pdev, 0);
if (!request_mem_region(phymem, pci_resource_len(pdev, 0), "Prism2")) {
printk(KERN_ERR "prism2: Cannot reserve PCI memory region\n");
result = -EIO;
goto fail;
}
mem = ioremap(phymem, PCI_SIZE);
if ( mem == 0 ) {
WLAN_LOG_ERROR("%s: ioremap() failed.\n", dev_info);
result = -EIO;
goto fail;
}
/* Log the device */
WLAN_LOG_INFO("A Prism2.5 PCI device found, "
"phymem:0x%llx, irq:%d, mem:0x%p\n",
(unsigned long long)phymem, pdev->irq, mem);
if ((wlandev = create_wlan()) == NULL) {
WLAN_LOG_ERROR("%s: Memory allocation failure.\n", dev_info);
result = -EIO;
goto fail;
}
hw = wlandev->priv;
if ( wlan_setup(wlandev) != 0 ) {
WLAN_LOG_ERROR("%s: wlan_setup() failed.\n", dev_info);
result = -EIO;
goto fail;
}
/* Setup netdevice's ability to report resources
* Note: the netdevice was allocated by wlan_setup()
*/
wlandev->netdev->irq = pdev->irq;
wlandev->netdev->mem_start = (unsigned long) mem;
wlandev->netdev->mem_end = wlandev->netdev->mem_start +
pci_resource_len(pdev, 0);
/* Register the wlandev, this gets us a name and registers the
* linux netdevice.
*/
SET_MODULE_OWNER(wlandev->netdev);
if ( register_wlandev(wlandev) != 0 ) {
WLAN_LOG_ERROR("%s: register_wlandev() failed.\n", dev_info);
result = -EIO;
goto fail;
}
#if 0
/* TODO: Move this and an irq test into an hfa384x_testif() routine.
*/
outw(PRISM2STA_MAGIC, HFA384x_SWSUPPORT(wlandev->netdev->base_addr));
reg=inw( HFA384x_SWSUPPORT(wlandev->netdev->base_addr));
if ( reg != PRISM2STA_MAGIC ) {
WLAN_LOG_ERROR("MAC register access test failed!\n");
result = -EIO;
goto fail;
}
#endif
/* Initialize the hw data */
hfa384x_create(hw, wlandev->netdev->irq, 0, mem);
hw->wlandev = wlandev;
/* Do a chip-level reset on the MAC */
if (prism2_doreset) {
result = hfa384x_corereset(hw,
prism2_reset_holdtime,
prism2_reset_settletime, 0);
if (result != 0) {
WLAN_LOG_ERROR(
"%s: hfa384x_corereset() failed.\n",
dev_info);
unregister_wlandev(wlandev);
hfa384x_destroy(hw);
result = -EIO;
goto fail;
}
}
pci_set_drvdata(pdev, wlandev);
/* Shouldn't actually hook up the IRQ until we
* _know_ things are alright. A test routine would help.
*/
request_irq(wlandev->netdev->irq, hfa384x_interrupt,
SA_SHIRQ, wlandev->name, wlandev);
wlandev->msdstate = WLAN_MSD_HWPRESENT;
result = 0;
goto done;
fail:
pci_set_drvdata(pdev, NULL);
if (wlandev) kfree(wlandev);
if (hw) kfree(hw);
if (mem) iounmap((void *) mem);
pci_release_regions(pdev);
pci_disable_device(pdev);
done:
DBFEXIT;
return result;
}
static int _pcc_get_status(u_short sock, u_int *value)
{
u_int status;
pr_debug("m32r_cfc: _pcc_get_status:\n");
status = pcc_get(sock, (unsigned int)PLD_CFSTS);
*value = (status) ? SS_DETECT : 0;
pr_debug("m32r_cfc: _pcc_get_status: status=0x%08x\n", status);
#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
if ( status ) {
/* enable CF power */
status = inw((unsigned int)PLD_CPCR);
if (!(status & PLD_CPCR_CF)) {
pr_debug("m32r_cfc: _pcc_get_status: "
"power on (CPCR=0x%08x)\n", status);
status |= PLD_CPCR_CF;
outw(status, (unsigned int)PLD_CPCR);
udelay(100);
}
*value |= SS_POWERON;
pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
udelay(100);
*value |= SS_READY; /* always ready */
*value |= SS_3VCARD;
} else {
/* disable CF power */
status = inw((unsigned int)PLD_CPCR);
status &= ~PLD_CPCR_CF;
outw(status, (unsigned int)PLD_CPCR);
udelay(100);
pr_debug("m32r_cfc: _pcc_get_status: "
"power off (CPCR=0x%08x)\n", status);
}
#elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
if ( status ) {
status = pcc_get(sock, (unsigned int)PLD_CPCR);
if (status == 0) { /* power off */
pcc_set(sock, (unsigned int)PLD_CPCR, 1);
pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
udelay(50);
}
*value |= SS_POWERON;
pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
udelay(50);
pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
udelay(25); /* for IDE reset */
pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
mdelay(2); /* for IDE reset */
*value |= SS_READY;
*value |= SS_3VCARD;
} else {
/* disable CF power */
pcc_set(sock, (unsigned int)PLD_CPCR, 0);
udelay(100);
pr_debug("m32r_cfc: _pcc_get_status: "
"power off (CPCR=0x%08x)\n", status);
}
#else
#error no platform configuration
#endif
pr_debug("m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
sock, *value);
return 0;
} /* _get_status */
/*
* mach8Probe --
* probe and initialize the hardware driver
*/
Bool
mach8Probe()
{
int j, memavail, rounding;
short temp;
DisplayModePtr pMode, pEnd, pmaxX = NULL, pmaxY = NULL;
int maxX, maxY;
OFlagSet validOptions;
int tx, ty;
mach8InfoRec.maxClock = mach8MaxClock;
xf86ClearIOPortList(mach8InfoRec.scrnIndex);
xf86AddIOPorts(mach8InfoRec.scrnIndex, Num_mach8_IOPorts, mach8_IOPorts);
if (mach8InfoRec.chipset) {
if (StrCaseCmp(mach8InfoRec.chipset, "mach8")) {
ErrorF("Chipset specified in XF86Config is not \"mach8\" (%s)!\n",
mach8InfoRec.chipset);
return(FALSE);
}
xf86EnableIOPorts(mach8InfoRec.scrnIndex);
}
else
{
xf86EnableIOPorts(mach8InfoRec.scrnIndex);
/* Reset the 8514/A, and disable all interrupts. */
outw(SUBSYS_CNTL, GPCTRL_RESET | CHPTEST_NORMAL);
outw(SUBSYS_CNTL, GPCTRL_ENAB | CHPTEST_NORMAL);
/* Check to see if an 8514/A is actually installed by writing to
* the ERR_TERM register, and reading back. The 0x5a5a value is
* entirely arbitrary.
*/
outw(ERR_TERM, 0x5a5a);
ProbeWaitIdleEmpty();
if (inw(ERR_TERM) != 0x5a5a) {
ErrorF("%s: No 8514/A registers detected!\n", mach8InfoRec.name);
xf86DisableIOPorts(mach8InfoRec.scrnIndex);
return(FALSE);
}
/* 6 mar 93 TCG : let's make certain */
outw(ERR_TERM, 0x2525);
ProbeWaitIdleEmpty();
if (inw(ERR_TERM) != 0x2525) {
ErrorF("%s: No 8514/A registers detected!\n", mach8InfoRec.name);
xf86DisableIOPorts(mach8InfoRec.scrnIndex);
return(FALSE);
}
temp = inw(ROM_ADDR_1);
outw(ROM_ADDR_1, 0x5555);
ProbeWaitIdleEmpty();
if (inw(ROM_ADDR_1) != 0x5555) {
ErrorF("%s: No ATI accelerator detected\n", mach8InfoRec.name);
xf86DisableIOPorts(mach8InfoRec.scrnIndex);
return(FALSE);
}
outw(ROM_ADDR_1, 0x2a2a);
ProbeWaitIdleEmpty();
if (inw(ROM_ADDR_1) != 0x2a2a) {
ErrorF("%s: No ATI accelerator detected\n", mach8InfoRec.name);
xf86DisableIOPorts(mach8InfoRec.scrnIndex);
return(FALSE);
}
outw(ROM_ADDR_1, temp);
outw(DESTX_DIASTP, 0xaaaa);
ProbeWaitIdleEmpty();
if ((inw(READ_SRC_X) != 0xaaaa) && xf86Verbose) {
outw(DESTX_DIASTP, 0x5555);
ProbeWaitIdleEmpty();
if (inw(READ_SRC_X) == 0x0555) {
ErrorF("%s %s: Mach-32 detected, used as a Mach-8\n",
XCONFIG_PROBED, mach8InfoRec.name);
}
else
ErrorF("%s %s: Mach-8 detected\n", XCONFIG_PROBED,
mach8InfoRec.name);
}
}
OFLG_ZERO(&validOptions);
OFLG_SET(OPTION_CSYNC, &validOptions);
xf86VerifyOptions(&validOptions, &mach8InfoRec);
if (!mach8InfoRec.clocks)
{
outw(DISP_CNTL, DISPEN_DISAB /*| INTERLACE*/ | MEMCFG_4 | ODDBNKENAB);
/* 13-jun-93 TCG : set up dummy video mode */
outw(SHADOW_SET, 1);
outw(SHADOW_CTL, 0);
outw(SHADOW_SET, 2);
outw(SHADOW_CTL, 0);
outw(SHADOW_SET, 0);
outw(ADVFUNC_CNTL, DISABPASSTHRU);
/* vt: 480 488 +31 528 hz: 640 656 +248 920 */
outw(V_TOTAL, 0x420);
outw(V_DISP, 0x3c0);
outw(V_SYNC_STRT, 0x3d0);
outw(V_SYNC_WID, 0x1f);
outw(H_TOTAL, 0x72);
outw(H_DISP, 0x4f);
outw(H_SYNC_STRT, 0x51);
outw(H_SYNC_WID, 0x1f);
outw(DAC_MASK, 0x00);
outw(DISP_CNTL, DISPEN_ENAB | MEMCFG_4 | ODDBNKENAB);
/* 2-oct-93 TCG : detect clocks with dif4 fix */
mach8clkprobedif4fix = TRUE;
xf86GetClocks(16, mach8ClockSelect, (void (*)())NoopDDA,
(SaveScreenProcPtr)NoopDDA, DISP_STAT, 2, 7, 44900,
&mach8InfoRec);
outw(CLOCK_SEL, 0); /* reset pass-through */
mach8clkprobedif4fix = FALSE;
outw(SHADOW_SET, 1);
outw(SHADOW_CTL, 0x3f);
outw(SHADOW_SET, 2);
outw(SHADOW_CTL, 0x3f);
outw(SHADOW_SET, 0);
outw(DAC_MASK, 0xff);
for (j = 0; j < 16; j++)
mach8InfoRec.clock[j + 16] = mach8InfoRec.clock[j] / 2;
mach8InfoRec.clocks = 32;
}
temp = inw(CONFIG_STATUS_1);
if (!mach8InfoRec.videoRam) {
switch((temp & 0x60) >> 5)
{
case 0:
mach8InfoRec.videoRam = 512;
break;
case 1:
mach8InfoRec.videoRam = 1024;
break;
default: /* 2 & 3 reserved in mach-8, used in mach-32 ? */
mach8InfoRec.videoRam = 1024;
break;
}
}
mach8InfoRec.chipset = "mach8";
xf86ProbeFailed = FALSE;
mach8DramUsed = (temp & 0x10) != 0;
if (xf86Verbose)
{
ErrorF("%s %s: (mem: %dk %cRAM numclocks: %d)",
OFLG_ISSET(XCONFIG_VIDEORAM,&mach8InfoRec.xconfigFlag) ?
XCONFIG_GIVEN : XCONFIG_PROBED,
mach8InfoRec.name,
mach8InfoRec.videoRam,
mach8DramUsed ? 'D' : 'V',
mach8InfoRec.clocks);
for (j=0; j < mach8InfoRec.clocks; j++)
{
if ((j % 8) == 0)
ErrorF("\n%s %s: clocks:",
OFLG_ISSET(XCONFIG_CLOCKS,&mach8InfoRec.xconfigFlag) ?
XCONFIG_GIVEN : XCONFIG_PROBED,
mach8InfoRec.name);
ErrorF(" %6.2f", (double)mach8InfoRec.clock[j]/1000.0);
}
ErrorF("\n");
}
memavail = mach8InfoRec.videoRam*1024;
if (mach8InfoRec.virtualX > 0 &&
mach8InfoRec.virtualX * mach8InfoRec.virtualY > memavail)
{
ErrorF("%s: Too little memory for virtual resolution %d %d\n",
mach8InfoRec.name, mach8InfoRec.virtualX,
mach8InfoRec.virtualY);
return(FALSE);
}
maxX = maxY = -1;
pMode = mach8InfoRec.modes;
if (pMode == NULL) {
ErrorF("No modes supplied in XF86Config\n");
return(FALSE);
}
pEnd = NULL;
tx = mach8InfoRec.virtualX;
ty = mach8InfoRec.virtualY;
do {
DisplayModePtr pModeSv;
/*
* xf86LookupMode returns FALSE if it ran into an invalid
* parameter
*/
if(xf86LookupMode(pMode, &mach8InfoRec, LOOKUP_DEFAULT) == FALSE) {
pModeSv=pMode->next;
xf86DeleteMode(&mach8InfoRec, pMode);
pMode = pModeSv;
} else if (pMode->HDisplay > 1024) {
pModeSv=pMode->next;
ErrorF("%s %s: Width to large for mode %s (max 1024)\n",
XCONFIG_PROBED, mach8InfoRec.name, pMode->name);
xf86DeleteMode(&mach8InfoRec, pMode);
pMode = pModeSv;
} else if (pMode->HDisplay * pMode->VDisplay > memavail) {
pModeSv=pMode->next;
ErrorF("%s %s: Too little memory for mode %s\n",
XCONFIG_PROBED, mach8InfoRec.name, pMode->name);
xf86DeleteMode(&mach8InfoRec, pMode);
pMode = pModeSv;
} else if (((tx > 0) && (pMode->HDisplay > tx)) ||
((ty > 0) && (pMode->VDisplay > ty))) {
pModeSv=pMode->next;
ErrorF("%s %s: Resolution %dx%d too large for virtual %dx%d\n",
XCONFIG_PROBED, mach8InfoRec.name,
pMode->HDisplay, pMode->VDisplay, tx, ty);
xf86DeleteMode(&mach8InfoRec, pMode);
pMode = pModeSv;
} else {
/*
* Successfully looked up this mode. If pEnd isn't
* initialized, set it to this mode.
*/
if(pEnd == (DisplayModePtr) NULL)
pEnd = pMode;
if (pMode->HDisplay > maxX)
{
maxX = pMode->HDisplay;
pmaxX = pMode;
}
if (pMode->VDisplay > maxY)
{
maxY = pMode->VDisplay;
pmaxY = pMode;
}
pMode = pMode->next;
}
} while (pMode != pEnd);
mach8InfoRec.virtualX = max(maxX, mach8InfoRec.virtualX);
mach8InfoRec.virtualY = max(maxY, mach8InfoRec.virtualY);
rounding = 8;
if (mach8InfoRec.virtualX % rounding)
{
mach8InfoRec.virtualX -= mach8InfoRec.virtualX % rounding;
ErrorF("%s %s: Virtual width rounded down to a multiple of %d (%d)\n",
XCONFIG_PROBED, mach8InfoRec.name, rounding,
mach8InfoRec.virtualX);
if (mach8InfoRec.virtualX < maxX)
{
ErrorF(
"%s: Rounded down virtual width (%d) is too small for mode %s",
mach8InfoRec.name, mach8InfoRec.virtualX, pmaxX->name);
return(FALSE);
}
ErrorF("%s: Virtual width rounded down to a multiple of %d (%d)\n",
mach8InfoRec.name, rounding, mach8InfoRec.virtualX);
}
if (mach8InfoRec.virtualX > 1024)
{
ErrorF("%s: Virtual width must be no greater than 1024\n",mach8InfoRec.name);
return(FALSE);
}
if ( mach8InfoRec.virtualX * mach8InfoRec.virtualY > memavail)
{
if (mach8InfoRec.virtualX != maxX || mach8InfoRec.virtualY != maxY)
ErrorF(
"%s: Too little memory to accomodate virtual size and mode %s\n",
mach8InfoRec.name,
(mach8InfoRec.virtualX == maxX) ? pmaxX->name : pmaxY->name);
else
ErrorF("%s: Too little memory to accomodate modes %s and %s\n",
mach8InfoRec.name, pmaxX->name, pmaxY->name);
return(FALSE);
}
if (xf86Verbose)
ErrorF("%s %s: Virtual resolution set to %dx%d\n",
OFLG_ISSET(XCONFIG_VIRTUAL,&mach8InfoRec.xconfigFlag) ?
XCONFIG_GIVEN : XCONFIG_PROBED, mach8InfoRec.name,
mach8InfoRec.virtualX, mach8InfoRec.virtualY);
return(TRUE);
}
/**************************************************************************
ETH_POLL - Wait for a frame
***************************************************************************/
int
EtherReceive(char *pkt, int maxlen)
{
/* common variables */
int len;
/* variables for 3C509 */
short status, cst;
register short rx_fifo;
cst = inw(BASE + EP_STATUS);
#ifdef EDEBUG
if (cst & 0x1FFF)
printf("-%x-",cst);
#endif
if ((cst & (S_RX_COMPLETE|S_RX_EARLY)) == 0) {
/* acknowledge everything */
outw(BASE + EP_COMMAND, ACK_INTR| (cst & S_5_INTS));
outw(BASE + EP_COMMAND, C_INTR_LATCH);
return 0;
}
status = inw(BASE + EP_W1_RX_STATUS);
#ifdef EDEBUG
printf("*%x*",status);
#endif
if (status & ERR_RX) {
outw(BASE + EP_COMMAND, RX_DISCARD_TOP_PACK);
return 0;
}
rx_fifo = status & RX_BYTES_MASK;
if (rx_fifo == 0)
return 0;
if (rx_fifo > maxlen)
goto zulang;
/* read packet */
#ifdef EDEBUG
printf("[l=%d",rx_fifo);
#endif
insw(BASE + EP_W1_RX_PIO_RD_1, pkt, rx_fifo / 2);
if (rx_fifo & 1)
pkt[rx_fifo-1] = inb(BASE + EP_W1_RX_PIO_RD_1);
len = rx_fifo;
for (;;) {
status = inw(BASE + EP_W1_RX_STATUS);
#ifdef EDEBUG
printf("*%x*",status);
#endif
rx_fifo = status & RX_BYTES_MASK;
if (rx_fifo > 0) {
if ((len + rx_fifo) > maxlen)
goto zulang;
insw(BASE + EP_W1_RX_PIO_RD_1, pkt + len, rx_fifo / 2);
if (rx_fifo & 1)
pkt[len + rx_fifo-1] = inb(BASE + EP_W1_RX_PIO_RD_1);
len += rx_fifo;
#ifdef EDEBUG
printf("+%d",rx_fifo);
#endif
}
if ((status & RX_INCOMPLETE) == 0) {
#ifdef EDEBUG
printf("=%d",len);
#endif
break;
}
delay(1000);
}
/* acknowledge reception of packet */
outw(BASE + EP_COMMAND, RX_DISCARD_TOP_PACK);
while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
continue;
return len;
zulang:
outw(BASE + EP_COMMAND, RX_DISCARD_TOP_PACK);
while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
continue;
return 0;
}
static void sk_isa_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
{
outw(val, dev->base_addr + reg);
}
/**************************************************************************
ETH_RESET - Reset adapter
***************************************************************************/
void
epreset(void)
{
int i;
/***********************************************************
Reset 3Com 509 card
*************************************************************/
epstop();
/*
* initialize card
*/
while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
continue;
GO_WINDOW(0);
/* Disable the card */
outw(BASE + EP_W0_CONFIG_CTRL, 0);
/* Configure IRQ to none */
outw(BASE + EP_W0_RESOURCE_CFG, SET_IRQ(0));
/* Enable the card */
outw(BASE + EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
GO_WINDOW(2);
/* Reload the ether_addr. */
for (i = 0; i < 6; i++)
outb(BASE + EP_W2_ADDR_0 + i, eth_myaddr[i]);
outw(BASE + EP_COMMAND, RX_RESET);
outw(BASE + EP_COMMAND, TX_RESET);
/* Window 1 is operating window */
GO_WINDOW(1);
for (i = 0; i < 31; i++)
inb(BASE + EP_W1_TX_STATUS);
/* get rid of stray intr's */
outw(BASE + EP_COMMAND, ACK_INTR | 0xff);
outw(BASE + EP_COMMAND, SET_RD_0_MASK | S_5_INTS);
outw(BASE + EP_COMMAND, SET_INTR_MASK);
outw(BASE + EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
FIL_BRDCST);
/* configure BNC */
if (ether_medium == ETHERMEDIUM_BNC) {
outw(BASE + EP_COMMAND, START_TRANSCEIVER);
delay(1000);
}
/* configure UTP */
if (ether_medium == ETHERMEDIUM_UTP) {
GO_WINDOW(4);
outw(BASE + EP_W4_MEDIA_TYPE, ENABLE_UTP);
GO_WINDOW(1);
}
/* start tranciever and receiver */
outw(BASE + EP_COMMAND, RX_ENABLE);
outw(BASE + EP_COMMAND, TX_ENABLE);
/* set early threshold for minimal packet length */
outw(BASE + EP_COMMAND, SET_RX_EARLY_THRESH | 64);
outw(BASE + EP_COMMAND, SET_TX_START_THRESH | 16);
}
/* We have a good packet(s), get it/them out of the buffers. */
static void
seeq8005_rx(struct device *dev)
{
struct net_local *lp = (struct net_local *)dev->priv;
int boguscount = 10;
int pkt_hdr;
int ioaddr = dev->base_addr;
do {
int next_packet;
int pkt_len;
int i;
int status;
status = inw(SEEQ_STATUS);
outw( lp->receive_ptr, SEEQ_DMAAR);
outw(SEEQCMD_FIFO_READ | SEEQCMD_RX_INT_ACK | (status & SEEQCMD_INT_MASK), SEEQ_CMD);
wait_for_buffer(dev);
next_packet = ntohs(inw(SEEQ_BUFFER));
pkt_hdr = inw(SEEQ_BUFFER);
if (net_debug>2) {
printk("%s: 0x%04x recv next=0x%04x, hdr=0x%04x\n",dev->name,lp->receive_ptr,next_packet,pkt_hdr);
}
if ((next_packet == 0) || ((pkt_hdr & SEEQPKTH_CHAIN)==0)) { /* Read all the frames? */
return; /* Done for now */
}
if ((pkt_hdr & SEEQPKTS_DONE)==0)
break;
if (next_packet < lp->receive_ptr) {
pkt_len = (next_packet + 0x10000 - ((DEFAULT_TEA+1)<<8)) - lp->receive_ptr - 4;
} else {
pkt_len = next_packet - lp->receive_ptr - 4;
}
if (next_packet < ((DEFAULT_TEA+1)<<8)) { /* is the next_packet address sane? */
printk("%s: recv packet ring corrupt, resetting board\n",dev->name);
seeq8005_init(dev,1);
return;
}
lp->receive_ptr = next_packet;
if (net_debug>2) {
printk("%s: recv len=0x%04x\n",dev->name,pkt_len);
}
if (pkt_hdr & SEEQPKTS_ANY_ERROR) { /* There was an error. */
lp->stats.rx_errors++;
if (pkt_hdr & SEEQPKTS_SHORT) lp->stats.rx_frame_errors++;
if (pkt_hdr & SEEQPKTS_DRIB) lp->stats.rx_frame_errors++;
if (pkt_hdr & SEEQPKTS_OVERSIZE) lp->stats.rx_over_errors++;
if (pkt_hdr & SEEQPKTS_CRC_ERR) lp->stats.rx_crc_errors++;
/* skip over this packet */
outw( SEEQCMD_FIFO_WRITE | SEEQCMD_DMA_INT_ACK | (status & SEEQCMD_INT_MASK), SEEQ_CMD);
outw( (lp->receive_ptr & 0xff00)>>8, SEEQ_REA);
} else {
/* Malloc up new buffer. */
struct sk_buff *skb;
unsigned char *buf;
skb = dev_alloc_skb(pkt_len);
if (skb == NULL) {
printk("%s: Memory squeeze, dropping packet.\n", dev->name);
lp->stats.rx_dropped++;
break;
}
skb->dev = dev;
skb_reserve(skb, 2); /* align data on 16 byte */
buf = skb_put(skb,pkt_len);
insw(SEEQ_BUFFER, buf, (pkt_len + 1) >> 1);
if (net_debug>2) {
char * p = buf;
printk("%s: recv ",dev->name);
for(i=0;i<14;i++) {
printk("%02x ",*(p++)&0xff);
}
printk("\n");
}
skb->protocol=eth_type_trans(skb,dev);
netif_rx(skb);
lp->stats.rx_packets++;
lp->stats.rx_bytes += pkt_len;
}
} while ((--boguscount) && (pkt_hdr & SEEQPKTH_CHAIN));
static int dhahelper_port(dhahelper_port_t * arg)
{
dhahelper_port_t port;
if (copy_from_user(&port, arg, sizeof(dhahelper_port_t)))
{
if (dhahelper_verbosity > 0)
printk(KERN_ERR "dhahelper: failed copy from userspace\n");
return -EFAULT;
}
switch(port.operation)
{
case PORT_OP_READ:
{
switch(port.size)
{
case 1:
port.value = inb(port.addr);
break;
case 2:
port.value = inw(port.addr);
break;
case 4:
port.value = inl(port.addr);
break;
default:
if (dhahelper_verbosity > 0)
printk(KERN_ERR "dhahelper: invalid port read size (%d)\n",
port.size);
return -EINVAL;
}
break;
}
case PORT_OP_WRITE:
{
switch(port.size)
{
case 1:
outb(port.value, port.addr);
break;
case 2:
outw(port.value, port.addr);
break;
case 4:
outl(port.value, port.addr);
break;
default:
if (dhahelper_verbosity > 0)
printk(KERN_ERR "dhahelper: invalid port write size (%d)\n",
port.size);
return -EINVAL;
}
break;
}
default:
if (dhahelper_verbosity > 0)
printk(KERN_ERR "dhahelper: invalid port operation (%d)\n",
port.operation);
return -EINVAL;
}
/* copy back only if read was performed */
if (port.operation == PORT_OP_READ)
if (copy_to_user(arg, &port, sizeof(dhahelper_port_t)))
{
if (dhahelper_verbosity > 0)
printk(KERN_ERR "dhahelper: failed copy to userspace\n");
return -EFAULT;
}
return 0;
}
extern __inline__ void mvv_write(u8 index, u8 value)
{
outw(index|(value<<8), io_port);
}
static inline u8 gemtek_pci_out( u16 value, u32 port )
{
outw( value, port );
return (u8)value;
}
static void isicom_tx(unsigned long _data)
{
unsigned long flags, base;
unsigned int retries;
short count = (BOARD_COUNT-1), card;
short txcount, wrd, residue, word_count, cnt;
struct isi_port *port;
struct tty_struct *tty;
/* find next active board */
card = (prev_card + 1) & 0x0003;
while (count-- > 0) {
if (isi_card[card].status & BOARD_ACTIVE)
break;
card = (card + 1) & 0x0003;
}
if (!(isi_card[card].status & BOARD_ACTIVE))
goto sched_again;
prev_card = card;
count = isi_card[card].port_count;
port = isi_card[card].ports;
base = isi_card[card].base;
spin_lock_irqsave(&isi_card[card].card_lock, flags);
for (retries = 0; retries < 100; retries++) {
if (inw(base + 0xe) & 0x1)
break;
udelay(2);
}
if (retries >= 100)
goto unlock;
tty = tty_port_tty_get(&port->port);
if (tty == NULL)
goto put_unlock;
for (; count > 0; count--, port++) {
/* port not active or tx disabled to force flow control */
if (!(port->port.flags & ASYNC_INITIALIZED) ||
!(port->status & ISI_TXOK))
continue;
txcount = min_t(short, TX_SIZE, port->xmit_cnt);
if (txcount <= 0 || tty->stopped || tty->hw_stopped)
continue;
if (!(inw(base + 0x02) & (1 << port->channel)))
continue;
pr_debug("txing %d bytes, port%d.\n",
txcount, port->channel + 1);
outw((port->channel << isi_card[card].shift_count) | txcount,
base);
residue = NO;
wrd = 0;
while (1) {
cnt = min_t(int, txcount, (SERIAL_XMIT_SIZE
- port->xmit_tail));
if (residue == YES) {
residue = NO;
if (cnt > 0) {
wrd |= (port->port.xmit_buf[port->xmit_tail]
<< 8);
port->xmit_tail = (port->xmit_tail + 1)
& (SERIAL_XMIT_SIZE - 1);
port->xmit_cnt--;
txcount--;
cnt--;
outw(wrd, base);
} else {
outw(wrd, base);
break;
}
}
if (cnt <= 0)
break;
word_count = cnt >> 1;
outsw(base, port->port.xmit_buf+port->xmit_tail, word_count);
port->xmit_tail = (port->xmit_tail
+ (word_count << 1)) & (SERIAL_XMIT_SIZE - 1);
txcount -= (word_count << 1);
port->xmit_cnt -= (word_count << 1);
if (cnt & 0x0001) {
residue = YES;
wrd = port->port.xmit_buf[port->xmit_tail];
port->xmit_tail = (port->xmit_tail + 1)
& (SERIAL_XMIT_SIZE - 1);
port->xmit_cnt--;
txcount--;
}
}
InterruptTheCard(base);
if (port->xmit_cnt <= 0)
port->status &= ~ISI_TXOK;
if (port->xmit_cnt <= WAKEUP_CHARS)
tty_wakeup(tty);
}
put_unlock:
tty_kref_put(tty);
unlock:
spin_unlock_irqrestore(&isi_card[card].card_lock, flags);
/* schedule another tx for hopefully in about 10ms */
sched_again:
mod_timer(&tx, jiffies + msecs_to_jiffies(10));
}
/* Do the interesting part of the probe at a single address. */
static int __init hpp_probe1(struct net_device *dev, int ioaddr)
{
int i, retval;
unsigned char checksum = 0;
const char name[] = "HP-PC-LAN+";
int mem_start;
static unsigned version_printed;
if (!request_region(ioaddr, HP_IO_EXTENT, DRV_NAME))
return -EBUSY;
/* Check for the HP+ signature, 50 48 0x 53. */
if (inw(ioaddr + HP_ID) != 0x4850
|| (inw(ioaddr + HP_PAGING) & 0xfff0) != 0x5300) {
retval = -ENODEV;
goto out;
}
if (ei_debug && version_printed++ == 0)
printk(version);
printk("%s: %s at %#3x, ", dev->name, name, ioaddr);
/* Retrieve and checksum the station address. */
outw(MAC_Page, ioaddr + HP_PAGING);
for(i = 0; i < ETHER_ADDR_LEN; i++) {
unsigned char inval = inb(ioaddr + 8 + i);
dev->dev_addr[i] = inval;
checksum += inval;
}
checksum += inb(ioaddr + 14);
printk("%pM", dev->dev_addr);
if (checksum != 0xff) {
printk(" bad checksum %2.2x.\n", checksum);
retval = -ENODEV;
goto out;
} else {
/* Point at the Software Configuration Flags. */
outw(ID_Page, ioaddr + HP_PAGING);
printk(" ID %4.4x", inw(ioaddr + 12));
}
/* Read the IRQ line. */
outw(HW_Page, ioaddr + HP_PAGING);
{
int irq = inb(ioaddr + 13) & 0x0f;
int option = inw(ioaddr + HPP_OPTION);
dev->irq = irq;
if (option & MemEnable) {
mem_start = inw(ioaddr + 9) << 8;
printk(", IRQ %d, memory address %#x.\n", irq, mem_start);
} else {
mem_start = 0;
printk(", IRQ %d, programmed-I/O mode.\n", irq);
}
}
/* Set the wrap registers for string I/O reads. */
outw((HP_START_PG + TX_PAGES/2) | ((HP_STOP_PG - 1) << 8), ioaddr + 14);
/* Set the base address to point to the NIC, not the "real" base! */
dev->base_addr = ioaddr + NIC_OFFSET;
dev->netdev_ops = &hpp_netdev_ops;
ei_status.name = name;
ei_status.word16 = 0; /* Agggghhhhh! Debug time: 2 days! */
ei_status.tx_start_page = HP_START_PG;
ei_status.rx_start_page = HP_START_PG + TX_PAGES/2;
ei_status.stop_page = HP_STOP_PG;
ei_status.reset_8390 = &hpp_reset_8390;
ei_status.block_input = &hpp_io_block_input;
ei_status.block_output = &hpp_io_block_output;
ei_status.get_8390_hdr = &hpp_io_get_8390_hdr;
/* Check if the memory_enable flag is set in the option register. */
if (mem_start) {
ei_status.block_input = &hpp_mem_block_input;
ei_status.block_output = &hpp_mem_block_output;
ei_status.get_8390_hdr = &hpp_mem_get_8390_hdr;
dev->mem_start = mem_start;
ei_status.mem = ioremap(mem_start,
(HP_STOP_PG - HP_START_PG)*256);
if (!ei_status.mem) {
retval = -ENOMEM;
goto out;
}
ei_status.rmem_start = dev->mem_start + TX_PAGES/2*256;
dev->mem_end = ei_status.rmem_end
= dev->mem_start + (HP_STOP_PG - HP_START_PG)*256;
}
outw(Perf_Page, ioaddr + HP_PAGING);
NS8390p_init(dev, 0);
/* Leave the 8390 and HP chip reset. */
outw(inw(ioaddr + HPP_OPTION) & ~EnableIRQ, ioaddr + HPP_OPTION);
retval = register_netdev(dev);
if (retval)
goto out1;
return 0;
out1:
iounmap(ei_status.mem);
out:
release_region(ioaddr, HP_IO_EXTENT);
return retval;
}