void process_flash_write(void){
WORD packet_length,i,c;
WORD block_remainder, packet_remainder;
if( !( EP2468STAT & 0x01 )){// EP2 FIFO NOT empty, host sent packet
FIFORESET = 0x80; SYNCDELAY;
packet_length = (EP2BCH << 8) | EP2BCL;
i = 0;
while(i < packet_length){
block_remainder = 256 - flash_addr_l;
packet_remainder = (packet_length > 256) ? 256 : packet_length;
c = min(block_remainder, packet_remainder);
if((flash_addr_m == 0) && (flash_addr_l == 0))
sector_erase(flash_addr_h);
page_write(flash_addr_h, flash_addr_m, flash_addr_l, &EP2FIFOBUF[i], c);
i += c;
// recalculate address
if((c + flash_addr_l) == 256){
flash_addr_l = 0x00;
if(flash_addr_m == 0xFF){
flash_addr_m = 0x00;
flash_addr_h += 1;
}
else
flash_addr_m += 1;
}
else
flash_addr_l += c;
}
FIFORESET = 0x00; SYNCDELAY;
OUTPKTEND = 0x82; // SKIP=1, do NOT pass buffer on to master
}
}
void write_mem(uint8_t* bfr, address_t address, length_t length)
{
uint32_t addrPtr = address;
page_erase(address);
busy_wait();
while(length)
{
uint16_t a = *bfr++;
a |= (*bfr++) << 8;
page_fill(addrPtr,a);
addrPtr += 2;
length -= 2;
}
page_write(address);
busy_wait();
rww_enable();
}
void create_table(void)
{
int field_num = 0;
int i;
int result = -1;
struct table new_table;
struct table *target_table;
char buf[CONFIG_PAGE_SIZE * 40]; // make this dynamic
char *buf_ptr;
int current_page;
int pos_on_current_page;
memset(&new_table, 0, sizeof(struct table));
new_table.isExist = 1;
printf("===== %s =====\n", __func__);
printf("Enter table name (max %d characters) :", CONFIG_MAX_FIELD_SIZE);
// scanf("%s", &(new_table.name));
printf("How many fields do you want (max %d fields) :", CONFIG_MAX_FIELD_SIZE);
// scanf("%d", &field_num);
printf("\ntable_name = %s field_num = %d \n", new_table.name, field_num);
for(i=0; i <= (field_num - 1); i++){
printf("field_num = %d\n", i);
printf("Enter Field #%d size :", i);
// scanf("%d", &(new_table.field_sizes[i]));
printf("Enter Field #%d name :", i);
// scanf("%s", (new_table.field_names[i]));
printf("%d : Field_size = %d field_name = %s\n", i, (new_table.field_sizes[i]), (new_table.field_names[i]));
}
strcpy(&(new_table.name), "adres\n");
strcpy(&(new_table.field_names[0]), "adi\n");
strcpy(&(new_table.field_names[1]), "soyadi\n");
new_table.field_sizes[0] = 12;
new_table.field_sizes[1] = 12;
printf("Done\n");
dump_table_struct(new_table);
result = page_access_init(SYSTEM_CATALOG_FILE);
if (result != ERR_OK)
return;
current_page = 0;
/* buf_ptr = points to somewhere in buf */
/* &buf = byte 0 of page 0 */
buf_ptr = &buf;
printf("buf_ptf = %08x\n", buf_ptr);
printf("*buf_ptf = %08x\n", *buf_ptr);
printf("&buf = %08x\n", &buf);
printf("buf = %08x\n", buf);
/* this is target table, used as pivot when needed */
//target_table = malloc(sizeof(struct table));
target_table = &buf;
printf("0target_table = %08x\n", target_table);
page_read(current_page, &buf);
//hexdump(buf, sizeof(struct table));
do{
if(!target_table->isExist)
{
printf("3target_table = %08x\n", target_table);
memcpy(target_table, &new_table, sizeof(struct table));
//hexdump(&buf, CONFIG_PAGE_SIZE);
// hexdump(&new_table, sizeof(struct table));
// hexdump(target_table, sizeof(struct table));
if ( (page_write(current_page-1, buf) == ERR_OK) &&
(page_write(current_page, buf) == ERR_OK) )
if (page_access_close() == ERR_OK)
result = 0;
break;
}
printf("1target_table = %08x\n", target_table);
*target_table++;
buf_ptr += sizeof(struct table);
printf("2target_table = %08x\n", target_table);
/* buf_ptr = pointer to current struct */
/* current_page = page number on disk starting from zero.
/* if remaining part of pagebuffer is smaller than a struct size it is overlapping */
/* (&buf - bufptr) % CONFIG_PAGE_SIZE > (CONFIG_PAGE_SIZE - sizeof(table)) */
if ( ((buf_ptr - buf) % CONFIG_PAGE_SIZE) > (CONFIG_PAGE_SIZE - sizeof(struct table)) )
{
current_page++;
result = page_read(current_page,
(buf + (current_page * CONFIG_PAGE_SIZE)),
CONFIG_PAGE_SIZE);
}
/* now it is safe to cast struct, we know trailing part of struct residing in &buf */
} while(result != ERR_EOF);
}
/*******************************************************************************
* Pull EP1 data
*******************************************************************************/
void ep1_pool(void){
BYTE i;
WORD adr;
BYTE new_data = 0;
// Test data for internal test
if(FPGA_INT0 && FPGA_DONE && !prev_done && !cmd_cnt){
EP8FIFOCFG = 0x00; SYNCDELAY;
FIFORESET = 0x08; SYNCDELAY;
FIFORESET = 0x00; SYNCDELAY;
EP8FIFOBUF[0] = 0x12;
EP8FIFOBUF[1] = 0x34;
EP8FIFOBUF[2] = 0x56;
EP8FIFOBUF[3] = 0x78;
EP8FIFOBUF[4] = 0x90;
EP8FIFOBUF[5] = 0xAB;
EP8FIFOBUF[6] = 0xCD;
EP8FIFOBUF[7] = 0xEF;
EP8BCH = 0;
EP8BCL = 8;
EP8FIFOCFG = 0x10; SYNCDELAY;
prev_done = 1;
}
if( !( EP1OUTCS & 0x02) ){ // Got something
cmd_cnt++;
for (i = 0; i < 0x40; i++)
EP1INBUF[i] = 0xFF; // fill output buffer
switch(EP1OUTBUF[0]){ // Decode command
//-----------------------------------------------------------------
default:
case CMD_READ_VERSION:
EP1INBUF[0] = fx2_ver_maj_;
EP1INBUF[1] = fx2_ver_min_;
EP1INBUF[2] = fx2_tip_maj_;
EP1INBUF[3] = fx2_tip_min_;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_SET_AUTORESPONSE:
sts_int_auto_configured = 1;
iar_adress = EP1OUTBUF[1];
iar_count = EP1OUTBUF[2];
iar_int_idx = 0;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_GET_AUTORESPONSE:
EP1INBUF[0] = iar_int_idx;
for(i = 0; i < 32; i++)
EP1INBUF[i+1] = auto_response_data[i];
iar_int_idx = 0;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_SWITCH_MODE:
sts_current_mode = 1;
new_data = 1;
EP1INBUF[0] = EP1OUTBUF[1];
break;
//-----------------------------------------------------------------
case CMD_READ_STATUS:
sts_flash_busy = get_flash_busy();
sts_booting = FPGA_DONE;
sts_fpga_prog = 0xaa;
sts_high_speed_mode = (USBCS & bmHSM) ? 1 : 255;
new_data = 1;
EP1INBUF[0] = sts_fifo_error;
EP1INBUF[1] = sts_current_mode;
EP1INBUF[2] = sts_flash_busy;
EP1INBUF[3] = sts_fpga_prog;
EP1INBUF[4] = sts_booting;
EP1INBUF[5] = sts_i2c_new_data;
EP1INBUF[6] = sts_int_auto_configured;
EP1INBUF[7] = sts_high_speed_mode;
sts_i2c_new_data = 0;
break;
//-----------------------------------------------------------------
case CMD_RESET_FIFO_STATUS:
sts_fifo_error = 0;
FIFORESET = 0x80; SYNCDELAY; // NAK all requests from host.
switch(EP1OUTBUF[1]){
case 2:
EP2FIFOCFG = 0x48; SYNCDELAY;
FIFORESET = 0x02; SYNCDELAY;
break;
case 4:
EP4FIFOCFG = 0x48; SYNCDELAY;
FIFORESET = 0x04; SYNCDELAY;
break;
case 6:
EP6FIFOCFG = 0x48; SYNCDELAY;
FIFORESET = 0x06; SYNCDELAY;
break;
default: // 0
EP2FIFOCFG = 0x48; SYNCDELAY;
EP4FIFOCFG = 0x48; SYNCDELAY;
EP6FIFOCFG = 0x48; SYNCDELAY;
EP8FIFOCFG = 0x10; SYNCDELAY;
FIFORESET = 0x02; SYNCDELAY;
FIFORESET = 0x04; SYNCDELAY;
FIFORESET = 0x06; SYNCDELAY;
}
FIFORESET = 0x00; SYNCDELAY; // Resume normal operation.
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_FLASH_WRITE:
if (EP1OUTBUF[4] > 59) EP1OUTBUF[4] = 59;
page_write(EP1OUTBUF[1], EP1OUTBUF[2], EP1OUTBUF[3], &EP1OUTBUF[5], EP1OUTBUF[4]); //highest, high, low adr, read_ptr, size
//-----------------------------------------------------------------
case CMD_FLASH_READ:
if (EP1OUTBUF[4] > 64) EP1OUTBUF[4] = 64;
page_read(EP1OUTBUF[1], EP1OUTBUF[2], EP1OUTBUF[3], &EP1INBUF[0], EP1OUTBUF[4]); //highest, high, low adr, read_ptr, size
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_FLASH_ERASE:
// busy_polling();
// On some modules it cause API error - better to do it from software side
bulk_erase();
new_data = 1;
sts_flash_busy = 1;
break;
//-----------------------------------------------------------------
case CMD_SECTOR_ERASE:
sector_erase(EP1OUTBUF[1]);
new_data = 1;
sts_flash_busy = 1;
break;
//-----------------------------------------------------------------
case CMD_FLASH_WRITE_COMMAND:
EP1INBUF[0] = 0x55;
spi_command(EP1OUTBUF[1], &EP1OUTBUF[3], EP1OUTBUF[2], &EP1INBUF[1]);
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_EEPROM_WRITE:
adr = EP1OUTBUF[1];
adr = (adr << 8) + EP1OUTBUF[2];
if (EP1OUTBUF[3] > 32) EP1OUTBUF[3] = 32;
EEPROMWrite(adr, EP1OUTBUF[3], &EP1OUTBUF[4]); // adress, size, data
//-----------------------------------------------------------------
case CMD_EEPROM_READ:
adr = EP1OUTBUF[1];
adr = (adr << 8) + EP1OUTBUF[2];
EEPROMRead(adr, EP1OUTBUF[3], &EP1INBUF[0]); // adress, size, data
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_GET_FIFO_STATUS:
EP1INBUF[0] = EP2CS;
EP1INBUF[1] = EP4CS;
EP1INBUF[2] = EP6CS;
EP1INBUF[3] = EP8CS;
EP1INBUF[4] = EP2FIFOBCH;
EP1INBUF[5] = EP4FIFOBCH;
EP1INBUF[6] = EP6FIFOBCH;
EP1INBUF[7] = EP8FIFOBCH;
EP1INBUF[8] = EP2FIFOBCL;
EP1INBUF[9] = EP4FIFOBCL;
EP1INBUF[10] = EP6FIFOBCL;
EP1INBUF[11] = EP8FIFOBCL;
EP1INBUF[12] = EP2FIFOFLGS;
EP1INBUF[13] = EP4FIFOFLGS;
EP1INBUF[14] = EP6FIFOFLGS;
EP1INBUF[15] = EP8FIFOFLGS;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_I2C_WRITE:
I2CWrite(EP1OUTBUF[1], EP1OUTBUF[2], &EP1OUTBUF[3]); // adress, size, data
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_I2C_READ:
I2CRead(EP1OUTBUF[1], EP1OUTBUF[2], &EP1INBUF[0]); // adress, size, data
new_data = 1;
break;
//-----------------------------------------------------------------
/*
case CMD_I2C_WRITE_READ:
i = EP1OUTBUF[1];
I2CWrite(i, EP1OUTBUF[2], &EP1OUTBUF[4]); // adress, size, data
delaycnt = 0;
while (INT0_PIN == 0){
EZUSB_Delay1ms();
delaycnt++;
if (delaycnt > 800)
break;
continue;
}
I2CRead(i, EP1OUTBUF[3], &EP1INBUF[0]); // adress, size, data
new_data = 1;
break;
*/
//-----------------------------------------------------------------
case CMD_FPGA_POWER:
if (EP1OUTBUF[1] == 0){
FPGA_POWER = 0;
sts_int_auto_configured = 0;
}
else{
IOD = 0x03; // Enable Power and disable Reset
OED = 0x03; // PROG_B and POWER
FPGA_POWER = 1;
}
EP1INBUF[0] = (FPGA_POWER) ? 1 : 0;
EP1INBUF[1] = 0xAA;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_FPGA_RESET:
FPGA_INT1 = (EP1OUTBUF[1]) ? 1 : 0;
EP1INBUF[0] = FPGA_INT1;
EP1INBUF[1] = 0xAA;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_DEV_LOCK:
if(EP1OUTBUF[1] == 0x01){ // Driver trying to lock device
if(lock == 0){ // Device is free
EP1INBUF[0] = 0x22; // Sucessfull lock
lock = 1;
}
else // Device is locked
EP1INBUF[0] = 0x00; // Already locked
}
else{ // Driver trying to unlock device
if(lock == 1){ // Device is locked
EP1INBUF[0] = 0x33; // Sucessfull unlock
lock = 0;
}
else // Device is unlocked
EP1INBUF[0] = 0x00; // Got problem
}
new_data = 1;
break;
//-----------------------------------------------------------------
}
EP1OUTBC = EP1DATA_COUNT; // Free input buffer
}
if(new_data){ // Have something to send
if ( !(EP1INCS & 0x02)){ // Can send ?
EP1INBC = EP1DATA_COUNT; // Send
new_data = 0;
}
}
}
