int gd405ex_get_fpga_done(unsigned fpga) { int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; if (legacy) return in_le16((void *)LATCH3_BASE) & CONFIG_SYS_FPGA_DONE(fpga); else return pca9698_get_value(0x22, fpga ? 9 : 8); }
int checkboard(void) { char *s = env_get("serial#"); bool hw_type_cat = pca9698_get_value(0x20, 20); puts("Board: "); printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber"); if (s) { puts(", serial# "); puts(s); } puts("\n"); return 0; }
int checkboard(void) { char *s = getenv("serial#"); bool hw_type_cat = pca9698_get_value(0x20, 18); puts("Board: "); printf("Strider %s", hw_type_cat ? "CAT" : "Fiber"); if (s != NULL) { puts(", serial# "); puts(s); } puts("\n"); return 0; }
static void print_fpga_info(unsigned int fpga, bool rgmii2_present) { u16 versions; u16 fpga_version; u16 fpga_features; unsigned unit_type; unsigned hardware_version; unsigned feature_compression; unsigned feature_osd; unsigned feature_audio; unsigned feature_sysclock; unsigned feature_ramconfig; unsigned feature_carrier_speed; unsigned feature_carriers; unsigned feature_video_channels; int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; FPGA_GET_REG(0, versions, &versions); FPGA_GET_REG(0, fpga_version, &fpga_version); FPGA_GET_REG(0, fpga_features, &fpga_features); unit_type = (versions & 0xf000) >> 12; feature_compression = (fpga_features & 0xe000) >> 13; feature_osd = fpga_features & (1<<11); feature_audio = (fpga_features & 0x0600) >> 9; feature_sysclock = (fpga_features & 0x0180) >> 7; feature_ramconfig = (fpga_features & 0x0060) >> 5; feature_carrier_speed = fpga_features & (1<<4); feature_carriers = (fpga_features & 0x000c) >> 2; feature_video_channels = fpga_features & 0x0003; if (legacy) printf("legacy "); switch (unit_type) { case UNITTYPE_MAIN_USER: printf("Mainchannel"); break; case UNITTYPE_VIDEO_USER: printf("Videochannel"); break; default: printf("UnitType %d(not supported)", unit_type); break; } if (unit_type == UNITTYPE_MAIN_USER) { if (legacy) hardware_version = (in_le16((void *)LATCH2_BASE)>>8) & 0x0f; else hardware_version = (!!pca9698_get_value(0x20, 24) << 0) | (!!pca9698_get_value(0x20, 25) << 1) | (!!pca9698_get_value(0x20, 26) << 2) | (!!pca9698_get_value(0x20, 27) << 3); switch (hardware_version) { case HWVER_100: printf(" HW-Ver 1.00,"); break; case HWVER_104: printf(" HW-Ver 1.04,"); break; case HWVER_110: printf(" HW-Ver 1.10,"); break; case HWVER_120: printf(" HW-Ver 1.20-1.21,"); break; case HWVER_200: printf(" HW-Ver 2.00,"); break; case HWVER_210: printf(" HW-Ver 2.10,"); break; case HWVER_220: printf(" HW-Ver 2.20,"); break; case HWVER_230: printf(" HW-Ver 2.30,"); break; default: printf(" HW-Ver %d(not supported),", hardware_version); break; } if (rgmii2_present) printf(" RGMII2,"); }
int mpc8308_get_fpga_done(uint fpga) { return pca9698_get_value(0x20, 19); }
int last_stage_init(void) { int slaves; uint k; uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; u16 fpga_features; bool hw_type_cat = pca9698_get_value(0x20, 20); bool ch0_rgmii2_present; FPGA_GET_REG(0, fpga_features, &fpga_features); /* Turn on Parade DP501 */ pca9698_direction_output(0x20, 10, 1); pca9698_direction_output(0x20, 11, 1); ch0_rgmii2_present = !pca9698_get_value(0x20, 30); /* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { uint ctr = 0; if (i2c_probe(mclink_controllers[k])) continue; while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { mdelay(100); if (ctr++ > 5) { printf("no done for mclink_controller %u\n", k); break; } } pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); udelay(10); pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, MCFPGA_RESET_N); } if (hw_type_cat) { uint mux_ch; int retval; struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); mdiodev->read = bb_miiphy_read; mdiodev->write = bb_miiphy_write; retval = mdio_register(mdiodev); if (retval < 0) return retval; for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { if ((mux_ch == 1) && !ch0_rgmii2_present) continue; setup_88e1514(bb_miiphy_buses[0].name, mux_ch); } } /* give slave-PLLs and Parade DP501 some time to be up and running */ mdelay(500); mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); mclink_fpgacount = 0; ioep_fpga_print_info(0); osd_probe(0); #ifdef CONFIG_SYS_OSD_DH osd_probe(4); #endif if (slaves <= 0) return 0; mclink_fpgacount = slaves; for (k = 1; k <= slaves; ++k) { FPGA_GET_REG(k, fpga_features, &fpga_features); ioep_fpga_print_info(k); osd_probe(k); #ifdef CONFIG_SYS_OSD_DH osd_probe(k + 4); #endif if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[k].name, MDIO_NAME_LEN); mdiodev->read = bb_miiphy_read; mdiodev->write = bb_miiphy_write; retval = mdio_register(mdiodev); if (retval < 0) return retval; setup_88e1514(bb_miiphy_buses[k].name, 0); } } for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) { i2c_set_bus_num(hrcon_fans[k].bus); init_fan_controller(hrcon_fans[k].addr); } return 0; }
int mpc8308_get_fpga_done(unsigned fpga) { return pca9698_get_value(0x20, 20); }
int last_stage_init(void) { int slaves; unsigned int k; unsigned int mux_ch; unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; bool hw_type_cat = pca9698_get_value(0x20, 18); bool ch0_sgmii2_present = false; /* Turn on Analog Devices ADV7611 */ pca9698_direction_output(0x20, 8, 0); /* Turn on Parade DP501 */ pca9698_direction_output(0x20, 9, 1); ch0_sgmii2_present = !pca9698_get_value(0x20, 37); /* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { unsigned int ctr = 0; if (i2c_probe(mclink_controllers[k])) continue; while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { udelay(100000); if (ctr++ > 5) { printf("no done for mclink_controller %d\n", k); break; } } pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); udelay(10); pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, MCFPGA_RESET_N); } if (hw_type_cat) { miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, bb_miiphy_write); for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { if ((mux_ch == 1) && !ch0_sgmii2_present) continue; setup_88e1514(bb_miiphy_buses[0].name, mux_ch); } } /* give slave-PLLs and Parade DP501 some time to be up and running */ udelay(500000); mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); mclink_fpgacount = 0; ioep_fpga_print_info(0); if (!adv7611_probe(0)) printf(" Advantiv ADV7611 HDMI Receiver\n"); #ifdef CONFIG_STRIDER_CON if (ioep_fpga_has_osd(0)) osd_probe(0); #endif #ifdef CONFIG_STRIDER_CPU ch7301_probe(0, false); #endif if (slaves <= 0) return 0; mclink_fpgacount = slaves; for (k = 1; k <= slaves; ++k) { ioep_fpga_print_info(k); #ifdef CONFIG_STRIDER_CON if (ioep_fpga_has_osd(k)) osd_probe(k); #endif #ifdef CONFIG_STRIDER_CPU FPGA_SET_REG(k, extended_control, 0); /* enable video in*/ if (!adv7611_probe(k)) printf(" Advantiv ADV7611 HDMI Receiver\n"); ch7301_probe(k, false); #endif if (hw_type_cat) { miiphy_register(bb_miiphy_buses[k].name, bb_miiphy_read, bb_miiphy_write); setup_88e1514(bb_miiphy_buses[k].name, 0); } } for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) { i2c_set_bus_num(strider_fans[k].bus); init_fan_controller(strider_fans[k].addr); } return 0; }
int last_stage_init(void) { int slaves; unsigned int k; unsigned int mux_ch; unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; #ifdef CONFIG_STRIDER_CPU unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; #endif bool hw_type_cat = pca9698_get_value(0x20, 18); #ifdef CONFIG_STRIDER_CON_DP bool is_dh = pca9698_get_value(0x20, 25); #endif bool ch0_sgmii2_present = false; /* Turn on Analog Devices ADV7611 */ pca9698_direction_output(0x20, 8, 0); /* Turn on Parade DP501 */ pca9698_direction_output(0x20, 10, 1); pca9698_direction_output(0x20, 11, 1); ch0_sgmii2_present = !pca9698_get_value(0x20, 37); /* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) { unsigned int ctr = 0; unsigned char *mclink_controllers = mclink_controllers_dvi; #ifdef CONFIG_STRIDER_CPU if (i2c_probe(mclink_controllers[k])) { mclink_controllers = mclink_controllers_dp; if (i2c_probe(mclink_controllers[k])) continue; } #else if (i2c_probe(mclink_controllers[k])) continue; #endif while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { udelay(100000); if (ctr++ > 5) { printf("no done for mclink_controller %d\n", k); break; } } pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); udelay(10); pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, MCFPGA_RESET_N); } if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); mdiodev->read = bb_miiphy_read; mdiodev->write = bb_miiphy_write; retval = mdio_register(mdiodev); if (retval < 0) return retval; for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { if ((mux_ch == 1) && !ch0_sgmii2_present) continue; setup_88e1514(bb_miiphy_buses[0].name, mux_ch); } } /* give slave-PLLs and Parade DP501 some time to be up and running */ udelay(500000); mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); mclink_fpgacount = 0; ioep_fpga_print_info(0); if (!adv7611_probe(0)) printf(" Advantiv ADV7611 HDMI Receiver\n"); #ifdef CONFIG_STRIDER_CON if (ioep_fpga_has_osd(0)) osd_probe(0); #endif #ifdef CONFIG_STRIDER_CON_DP if (ioep_fpga_has_osd(0)) { osd_probe(0); if (is_dh) osd_probe(4); } #endif #ifdef CONFIG_STRIDER_CPU ch7301_probe(0, false); dp501_probe(0, false); #endif if (slaves <= 0) return 0; mclink_fpgacount = slaves; #ifdef CONFIG_STRIDER_CPU /* get ADV7611 out of reset, power up DP501, give some time to wakeup */ for (k = 1; k <= slaves; ++k) FPGA_SET_REG(k, extended_control, 0x10); /* enable video */ udelay(500000); #endif for (k = 1; k <= slaves; ++k) { ioep_fpga_print_info(k); #ifdef CONFIG_STRIDER_CON if (ioep_fpga_has_osd(k)) osd_probe(k); #endif #ifdef CONFIG_STRIDER_CON_DP if (ioep_fpga_has_osd(k)) { osd_probe(k); if (is_dh) osd_probe(k + 4); } #endif #ifdef CONFIG_STRIDER_CPU if (!adv7611_probe(k)) printf(" Advantiv ADV7611 HDMI Receiver\n"); ch7301_probe(k, false); dp501_probe(k, false); #endif if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[k].name, MDIO_NAME_LEN); mdiodev->read = bb_miiphy_read; mdiodev->write = bb_miiphy_write; retval = mdio_register(mdiodev); if (retval < 0) return retval; setup_88e1514(bb_miiphy_buses[k].name, 0); } } for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) { i2c_set_bus_num(strider_fans[k].bus); init_fan_controller(strider_fans[k].addr); } return 0; }