static void pch_lpc_add_io_resources(struct device *dev) { /* Add the default claimed legacy IO range for the LPC device. */ pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED); /* SoC IO resource overrides */ pch_lpc_soc_fill_io_resources(dev); }
/* Fill up LPC IO resource structure inside SoC directory */ void pch_lpc_soc_fill_io_resources(struct device *dev) { /* * PMC pci device gets hidden from PCI bus due to Silicon * policy hence bind ACPI BASE aka ABASE (offset 0x20) with * LPC IO resources to ensure that ABASE falls under PCI reserved * IO memory range. * * Note: Don't add any more resource with same offset 0x20 * under this device space. */ pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED); }