int __pci_pre_init(struct pci_controller *hose) { /* * This board is always configured as the host & requires the * PCI arbiter to be enabled. */ if (!pci_arbiter_enabled()) { printf("PCI: PCI Arbiter disabled!\n"); return 0; } return 1; }
int checkcpu (void) { #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */ uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; #if !defined(CONFIG_IOP480) char addstr[64] = ""; sys_info_t sys_info; puts ("CPU: "); get_sys_info(&sys_info); puts("AMCC PowerPC 4"); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) puts("05"); #endif #if defined(CONFIG_440) puts("40"); #endif switch (pvr) { case PVR_405GP_RB: puts("GP Rev. B"); break; case PVR_405GP_RC: puts("GP Rev. C"); break; case PVR_405GP_RD: puts("GP Rev. D"); break; #ifdef CONFIG_405GP case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ puts("GP Rev. E"); break; #endif case PVR_405CR_RA: puts("CR Rev. A"); break; case PVR_405CR_RB: puts("CR Rev. B"); break; #ifdef CONFIG_405CR case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ puts("CR Rev. C"); break; #endif case PVR_405GPR_RB: puts("GPr Rev. B"); break; case PVR_405EP_RB: puts("EP Rev. B"); break; case PVR_405EZ_RA: puts("EZ Rev. A"); break; case PVR_405EX1_RA: puts("EX Rev. A"); strcpy(addstr, "Security support"); break; case PVR_405EX2_RA: puts("EX Rev. A"); strcpy(addstr, "No Security support"); break; case PVR_405EXR1_RA: puts("EXr Rev. A"); strcpy(addstr, "Security support"); break; case PVR_405EXR2_RA: puts("EXr Rev. A"); strcpy(addstr, "No Security support"); break; #if defined(CONFIG_440) case PVR_440GP_RB: puts("GP Rev. B"); /* See errata 1.12: CHIP_4 */ if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) || (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){ puts ( "\n\t CPC0_SYSx DCRs corrupted. " "Resetting chip ...\n"); udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ do_chip_reset ( mfdcr(cpc0_strp0), mfdcr(cpc0_strp1) ); } break; case PVR_440GP_RC: puts("GP Rev. C"); break; case PVR_440GX_RA: puts("GX Rev. A"); break; case PVR_440GX_RB: puts("GX Rev. B"); break; case PVR_440GX_RC: puts("GX Rev. C"); break; case PVR_440GX_RF: puts("GX Rev. F"); break; case PVR_440EP_RA: puts("EP Rev. A"); break; #ifdef CONFIG_440EP case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */ puts("EP Rev. B"); break; case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */ puts("EP Rev. C"); break; #endif /* CONFIG_440EP */ #ifdef CONFIG_440GR case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */ puts("GR Rev. A"); break; case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */ puts("GR Rev. B"); break; #endif /* CONFIG_440GR */ #endif /* CONFIG_440 */ #ifdef CONFIG_440EPX case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("EPx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("EPx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; #endif /* CONFIG_440EPX */ #ifdef CONFIG_440GRX case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("GRx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("GRx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; #endif /* CONFIG_440GRX */ case PVR_440SP_6_RAB: puts("SP Rev. A/B"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SP_RAB: puts("SP Rev. A/B"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SP_6_RC: puts("SP Rev. C"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SP_RC: puts("SP Rev. C"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SPe_6_RA: puts("SPe Rev. A"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RA: puts("SPe Rev. A"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SPe_6_RB: puts("SPe Rev. B"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RB: puts("SPe Rev. B"); strcpy(addstr, "No RAID 6 support"); break; default: printf (" UNKNOWN (PVR=%08x)", pvr); break; } printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), sys_info.freqPLB / 1000000, get_OPB_freq() / 1000000, sys_info.freqEBC / 1000000); if (addstr[0] != 0) printf(" %s\n", addstr); #if defined(I2C_BOOTROM) printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); #endif /* I2C_BOOTROM */ #if defined(SDR0_PINSTP_SHIFT) printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]); printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); #endif /* SDR0_PINSTP_SHIFT */ #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); #endif #if defined(PCI_ASYNC) if (pci_async_enabled()) { printf (", PCI async ext clock used"); } else { printf (", PCI sync clock at %lu MHz", sys_info.freqPLB / sys_info.pllPciDiv / 1000000); } #endif #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) putc('\n'); #endif #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) printf (" 16 kB I-Cache 16 kB D-Cache"); #elif defined(CONFIG_440) printf (" 32 kB I-Cache 32 kB D-Cache"); #else printf (" 16 kB I-Cache %d kB D-Cache", ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); #endif #endif /* !defined(CONFIG_IOP480) */ #if defined(CONFIG_IOP480) printf ("PLX IOP480 (PVR=%08x)", pvr); printf (" at %s MHz:", strmhz(buf, clock)); printf (" %u kB I-Cache", 4); printf (" %u kB D-Cache", 2); #endif #endif /* !defined(CONFIG_405) */ putc ('\n'); return 0; }