ACPI_STATUS
acpi_os_write_pci_configuration (
acpi_pci_id *pci_id,
u32 reg,
NATIVE_UINT value,
u32 width)
{
int result = 0;
switch (width)
{
case 8:
result = pci_config_write(pci_id->segment, pci_id->bus,
pci_id->device, pci_id->function, reg, 1, value);
break;
case 16:
result = pci_config_write(pci_id->segment, pci_id->bus,
pci_id->device, pci_id->function, reg, 2, value);
break;
case 32:
result = pci_config_write(pci_id->segment, pci_id->bus,
pci_id->device, pci_id->function, reg, 4, value);
break;
default:
BUG();
}
return (result ? AE_ERROR : AE_OK);
}
acpi_status
acpi_os_write_pci_configuration (
struct acpi_pci_id *pci_id,
u32 reg,
acpi_integer value,
u32 width)
{
int result = 0;
switch (width)
{
case 8:
result = pci_config_write(pci_id->segment, pci_id->bus,
pci_id->device, pci_id->function, reg, 1, value);
break;
case 16:
result = pci_config_write(pci_id->segment, pci_id->bus,
pci_id->device, pci_id->function, reg, 2, value);
break;
case 32:
result = pci_config_write(pci_id->segment, pci_id->bus,
pci_id->device, pci_id->function, reg, 4, value);
break;
default:
BUG();
}
return (result ? AE_ERROR : AE_OK);
}
void pci_config_write_partial(uint8_t bus, uint8_t device, uint8_t function, uint8_t offset, uint32_t value, int size) {
int remainder = offset & 3;
offset &= (~(uint8_t)3);
uint32_t current = pci_config_read(bus, device, function, offset);
value <<= remainder;
current |= value;
pci_config_write(bus, device, function, offset, value);
}
/**
* \brief Enable PCI command bits of the specified PCI configuration
* register.
* \param addr Address of PCI configuration register.
* \param flags Flags used to enable PCI command bits.
*/
void
pci_command_enable(pci_config_addr_t addr, uint32_t flags)
{
uint32_t data;
addr.reg_off = 0x04; /* PCI COMMAND_REGISTER */
data = pci_config_read(addr);
pci_config_write(addr, data | flags);
}
