static void mch_domain_read_resources(device_t dev)
{
u64 tom, touud;
u32 tomk, tsegk, tolud, usable_tomk;
u32 pcie_config_base, pcie_config_size;
u32 uma_sizek = 0;
/* 1024KiB TSEG */
tsegk = 1 << 10;
pci_domain_read_resources(dev);
/* Top of Upper Usable DRAM, including remap */
touud = pci_read_config16(dev, D0F0_TOUUD);
touud <<= 20;
/* Top of Lower Usable DRAM */
tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0;
tolud <<= 16;
/* Top of Memory - does not account for any UMA */
tom = pci_read_config16(dev, D0F0_TOM) & 0x01ff;
tom <<= 26;
printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
touud, tolud, tom);
tomk = tolud >> 10;
/* Graphics memory comes next */
const u16 ggc = pci_read_config16(dev, D0F0_GGC);
printk(BIOS_DEBUG, "IGD decoded, subtracting ");
/* Graphics memory */
const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);
/* GTT Graphics Stolen Memory Size (GGMS) */
const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
uma_sizek = gms_sizek + gsm_sizek + tsegk;
usable_tomk = tomk - uma_sizek;
printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10);
/* Report the memory regions */
ram_resource(dev, 3, 0, legacy_hole_base_k);
ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
(usable_tomk - (legacy_hole_base_k + legacy_hole_size_k)));
/*
* If >= 4GB installed then memory from TOLUD to 4GB
* is remapped above TOM, TOUUD will account for both
*/
touud >>= 10; /* Convert to KB */
if (touud > 4096 * 1024) {
ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024));
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
(touud >> 10) - 4096);
}
static void cpu_pci_domain_read_resources(struct device *dev)
{
pci_domain_read_resources(dev);
}
static void cpu_pci_domain_read_resources(struct device *dev)
{
u16 nbid = pci_read_config16(dev_find_slot(0, 0), PCI_DEVICE_ID);
int i440fx = (nbid == 0x1237);
int q35 = (nbid == 0x29c0);
struct resource *res;
unsigned long tomk = 0, high;
int idx = 10;
int size;
pci_domain_read_resources(dev);
size = fw_cfg_check_file("etc/e820");
if (size > 0) {
/* supported by qemu 1.7+ */
FwCfgE820Entry *list = malloc(size);
int i;
fw_cfg_load_file("etc/e820", list);
for (i = 0; i < size/sizeof(*list); i++) {
switch (list[i].type) {
case 1: /* ram */
printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n",
list[i].address, list[i].length);
if (list[i].address == 0) {
tomk = list[i].length / 1024;
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768);
} else {
ram_resource(dev, idx++,
list[i].address / 1024,
list[i].length / 1024);
}
break;
case 2: /* reserved */
printk(BIOS_DEBUG, "QEMU: e820/res: 0x%08llx +0x%08llx\n",
list[i].address, list[i].length);
res = new_resource(dev, idx++);
res->base = list[i].address;
res->size = list[i].length;
res->limit = 0xffffffff;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
break;
default:
/* skip unknown */
break;
}
}
free(list);
}
if (!tomk) {
/* qemu older than 1.7, or reading etc/e820 failed. Fallback to cmos. */
tomk = qemu_get_memory_size();
high = qemu_get_high_memory_size();
printk(BIOS_DEBUG, "QEMU: cmos: %lu MiB RAM below 4G.\n", tomk / 1024);
printk(BIOS_DEBUG, "QEMU: cmos: %lu MiB RAM above 4G.\n", high / 1024);
/* Report the memory regions. */
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768);
if (high)
ram_resource(dev, idx++, 4 * 1024 * 1024, high);
}
/* Reserve I/O ports used by QEMU */
qemu_reserve_ports(dev, idx++, 0x0510, 0x02, "firmware-config");
qemu_reserve_ports(dev, idx++, 0x5658, 0x01, "vmware-port");
if (i440fx) {
qemu_reserve_ports(dev, idx++, 0xae00, 0x10, "pci-hotplug");
qemu_reserve_ports(dev, idx++, 0xaf00, 0x20, "cpu-hotplug");
qemu_reserve_ports(dev, idx++, 0xafe0, 0x04, "piix4-gpe0");
}
if (inb(CONFIG_CONSOLE_QEMU_DEBUGCON_PORT) == 0xe9) {
qemu_reserve_ports(dev, idx++, CONFIG_CONSOLE_QEMU_DEBUGCON_PORT, 1,
"debugcon");
}
if (q35 && ((tomk * 1024) < 0xb0000000)) {
/*
* Reserve the region between top-of-ram and the
* mmconf xbar (ar 0xb0000000), so coreboot doesn't
* place pci bars there. The region isn't declared as
* pci io window in the acpi tables (\_SB.PCI0._CRS).
*/
res = new_resource(dev, idx++);
res->base = tomk * 1024;
res->size = 0xb0000000 - tomk * 1024;
res->limit = 0xffffffff;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
if (i440fx) {
/* Reserve space for the IOAPIC. This should be in
* the southbridge, but I couldn't tell which device
* to put it in. */
res = new_resource(dev, 2);
res->base = IO_APIC_ADDR;
res->size = 0x100000UL;
res->limit = 0xffffffffUL;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
/* Reserve space for the LAPIC. There's one in every processor, but
* the space only needs to be reserved once, so we do it here. */
res = new_resource(dev, 3);
res->base = LOCAL_APIC_ADDR;
res->size = 0x10000UL;
res->limit = 0xffffffffUL;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
}
static void mch_domain_read_resources(struct device *dev)
{
u64 tom, touud;
u32 tomk, tolud, uma_sizek = 0, delta_cbmem;
u32 pcie_config_base, pcie_config_size;
/* Total Memory 2GB example:
*
* 00000000 0000MB-2014MB 2014MB RAM (writeback)
* 7de00000 2014MB-2016MB 2MB GFX GTT (uncached)
* 7e000000 2016MB-2048MB 32MB GFX UMA (uncached)
* 80000000 2048MB TOLUD
* 80000000 2048MB TOM
*
* Total Memory 4GB example:
*
* 00000000 0000MB-3038MB 3038MB RAM (writeback)
* bde00000 3038MB-3040MB 2MB GFX GTT (uncached)
* be000000 3040MB-3072MB 32MB GFX UMA (uncached)
* be000000 3072MB TOLUD
* 100000000 4096MB TOM
* 100000000 4096MB-5120MB 1024MB RAM (writeback)
* 140000000 5120MB TOUUD
*/
pci_domain_read_resources(dev);
struct device *mch = pcidev_on_root(0, 0);
/* Top of Upper Usable DRAM, including remap */
touud = pci_read_config16(mch, D0F0_TOUUD);
touud <<= 20;
/* Top of Lower Usable DRAM */
tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0;
tolud <<= 16;
/* Top of Memory - does not account for any UMA */
tom = pci_read_config16(mch, D0F0_TOM) & 0x1ff;
tom <<= 27;
printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
touud, tolud, tom);
tomk = tolud >> 10;
/* Graphics memory comes next */
const u16 ggc = pci_read_config16(mch, D0F0_GGC);
if (!(ggc & 2)) {
printk(BIOS_DEBUG, "IGD decoded, subtracting ");
/* Graphics memory */
const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
printk(BIOS_DEBUG, "%uM UMA, ", gms_sizek >> 10);
tomk -= gms_sizek;
/* GTT Graphics Stolen Memory Size (GGMS) */
const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
printk(BIOS_DEBUG, "%uM GTT", gsm_sizek >> 10);
tomk -= gsm_sizek;
uma_sizek = gms_sizek + gsm_sizek;
}
