void
iq80321_pci_init2(pci_chipset_tag_t pc, void *cookie)
{
pcitag_t tag;
int i, j;
struct board_id *sys;
u_int32_t reg;
for (i = 0; systems[i] != NULL; i++) {
sys = systems[i];
for (j = 0; sys->list[j].vend != 0; j++) {
tag = pci_make_tag(pc, sys->list[j].bus,
sys->list[j].dev, 0);
reg = pci_conf_read(pc, tag, 0 /* ID */);
#ifdef PROBE_NEW_BOARD
printf("read %x expected %x\n", reg,
(sys->list[j].vend | sys->list[j].prod << 16));
#endif
if ((sys->list[j].vend | sys->list[j].prod << 16) !=
reg){
sys = NULL;
break;
}
}
if (sys != NULL)
break;
}
if (sys == NULL) {
printf("board id failed\n");
#ifdef PROBE_NEW_BOARD
for (i = 0; i < 16; i++) {
tag = pci_make_tag(pc, 0, i, 0);
printf("bus 0, dev %d: %x\n", i,
pci_conf_read(pc, tag, 0 /* ID */));
}
#endif
} else
printf(": %s", sys->name);
iq80321_irq_map = sys->irq_map;
/* XXX */
if (sys == &thecus) {
/*
* thecus com irq appears to not be attached, override
* it's irq here, it is tied to the tick timer, irq9
* - yes this is a hack.
*/
extern int com_irq_override;
com_irq_override = 28;
}
}
void
pci_device_foreach(struct shpcic_softc *sc, pci_chipset_tag_t pc, int maxbus,
void (*func)(struct shpcic_softc *, pci_chipset_tag_t, pcitag_t))
{
const struct pci_quirkdata *qd;
int bus, device, function, maxdevs, nfuncs;
pcireg_t id, bhlcr;
pcitag_t tag;
for (bus = 0; bus <= maxbus; bus++) {
maxdevs = pci_bus_maxdevs(pc, bus);
for (device = 0; device < maxdevs; device++) {
tag = pci_make_tag(pc, bus, device, 0);
id = pci_conf_read(pc, tag, PCI_ID_REG);
/* Invalid vendor ID value? */
if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
continue;
/* XXX Not invalid, but we've done this ~forever. */
if (PCI_VENDOR(id) == 0)
continue;
qd = pci_lookup_quirkdata(PCI_VENDOR(id),
PCI_PRODUCT(id));
bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
if (PCI_HDRTYPE_MULTIFN(bhlcr) ||
(qd != NULL &&
(qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0))
nfuncs = 8;
else
nfuncs = 1;
for (function = 0; function < nfuncs; function++) {
tag = pci_make_tag(pc, bus, device, function);
id = pci_conf_read(pc, tag, PCI_ID_REG);
/* Invalid vendor ID value? */
if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
continue;
/*
* XXX Not invalid, but we've done this
* ~forever.
*/
if (PCI_VENDOR(id) == 0)
continue;
(*func)(sc, pc, tag);
}
}
}
}
void
mpbios_intr_fixup(void)
{
const struct mpbios_icu_table *mpit = NULL;
pci_chipset_tag_t pc = NULL;
pcitag_t icutag;
int device, maxdevs = pci_bus_maxdevs(pc, 0);
/* Search configuration space for a known interrupt router. */
for (device = 0; device < maxdevs; device++) {
const struct pci_quirkdata *qd;
int function, nfuncs;
pcireg_t icuid;
pcireg_t bhlcr;
icutag = pci_make_tag(pc, 0, device, 0);
icuid = pci_conf_read(pc, icutag, PCI_ID_REG);
/* Invalid vendor ID value? */
if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID)
continue;
qd = pci_lookup_quirkdata(PCI_VENDOR(icuid),
PCI_PRODUCT(icuid));
bhlcr = pci_conf_read(pc, icutag, PCI_BHLC_REG);
if (PCI_HDRTYPE_MULTIFN(bhlcr) || (qd != NULL &&
(qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0))
nfuncs = 8;
else
nfuncs = 1;
for (function = 0; function < nfuncs; function++) {
icutag = pci_make_tag(pc, 0, device, function);
icuid = pci_conf_read(pc, icutag, PCI_ID_REG);
/* Invalid vendor ID value? */
if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID)
continue;
if ((mpit = mpbios_icu_lookup(icuid)))
break;
}
if (mpit != NULL)
break;
}
if (mpit)
mpit->mpit_mpbios_fixup(pc, icutag);
}
/*
* Setup proper Local<->PCI mapping
* PCI memory window: 256M @ PCI0MEMBASE with direct memory translation
*/
void
ibm4xx_setup_pci(void)
{
pci_chipset_tag_t pc = &genppc_ibm4xx_chipset;
pcitag_t tag;
setup_pcicfg_window();
/* Disable all three memory mappers */
bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA, 0x00000000); /* disabled */
bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1MA, 0x00000000); /* disabled */
bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2MA, 0x00000000); /* disabled */
bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS, 0x00000000); /* Can't really disable PTM1. */
bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2MS, 0x00000000); /* disabled */
/* Setup memory map #0 */
bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA, 0xF0000001); /* 256M non-prefetchable, enabled */
bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0LA, PCI0_MEM_BASE);
bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCILA, PCI0_MEM_BASE);
bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCIHA, 0);
/* Configure PCI bridge */
tag = pci_make_tag(pc, 0, 0, 0);
// x = pci_conf_read(pc, tag, PCI0_CMD); /* Read PCI command register */
// pci_conf_write(pc, tag, PCI0_CMD, x | MA | ME); /* enable bus mastering and memory space */
bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS, 0xF0000001); /* Enable PTM1 */
bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1LA, 0);
pci_conf_write(pc, tag, PCIC_PTM1BAR, 0); /* Set up proper PCI->Local address base. Always enabled */
pci_conf_write(pc, tag, PCIC_PTM2BAR, 0);
}
void
pci_alphabook1_pickintr(struct lca_config *lcp)
{
bus_space_tag_t iot = &lcp->lc_iot;
pci_chipset_tag_t pc = &lcp->lc_pc;
pcireg_t sioclass;
int sioII;
/* XXX MAGIC NUMBER */
sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, LCA_SIO_DEVICE, 0),
PCI_CLASS_REG);
sioII = (sioclass & 0xff) >= 3;
if (!sioII)
printf("WARNING: SIO NOT SIO II... NO BETS...\n");
pc->pc_intr_v = lcp;
pc->pc_intr_map = dec_alphabook1_intr_map;
pc->pc_intr_string = dec_alphabook1_intr_string;
pc->pc_intr_line = dec_alphabook1_intr_line;
pc->pc_intr_establish = dec_alphabook1_intr_establish;
pc->pc_intr_disestablish = dec_alphabook1_intr_disestablish;
/* Not supported on AlphaBook. */
pc->pc_pciide_compat_intr_establish = NULL;
#if NSIO
sio_intr_setup(pc, iot);
#else
panic("pci_alphabook1_pickintr: no I/O interrupt handler (no sio)");
#endif
}
/*
* AcpiOsReadPciConfiguration:
*
* Read a value from a PCI configuration register.
*/
ACPI_STATUS
AcpiOsReadPciConfiguration(ACPI_PCI_ID *PciId, UINT32 Register, UINT64 *Value,
UINT32 Width)
{
pcitag_t tag;
pcireg_t tmp;
/* XXX Need to deal with "segment" ("hose" in Alpha terminology). */
if (PciId->Bus >= 256 || PciId->Device >= 32 || PciId->Function >= 8)
return AE_BAD_PARAMETER;
tag = pci_make_tag(acpi_softc->sc_pc, PciId->Bus, PciId->Device,
PciId->Function);
tmp = pci_conf_read(acpi_softc->sc_pc, tag, Register & ~3);
switch (Width) {
case 8:
*(uint8_t *) Value = (tmp >> ((Register & 3) * 8)) & 0xff;
break;
case 16:
*(uint16_t *) Value = (tmp >> ((Register & 3) * 8)) & 0xffff;
break;
case 32:
*(uint32_t *) Value = tmp;
break;
default:
return AE_BAD_PARAMETER;
}
return AE_OK;
}
int
igsfb_pci_cnattach(bus_space_tag_t iot, bus_space_tag_t memt,
pci_chipset_tag_t pc,
int bus, int device, int function)
{
struct igsfb_devconfig *dc;
pcitag_t tag;
pcireg_t id;
int ret;
tag = pci_make_tag(pc, bus, device, function);
id = pci_conf_read(pc, tag, PCI_ID_REG);
if (igsfb_pci_match_by_id(id) == 0)
return 1;
dc = &igsfb_console_dc;
if (igsfb_pci_map_regs(dc, iot, memt, pc, tag, PCI_PRODUCT(id)) != 0)
return 1;
ret = igsfb_enable(dc->dc_iot, dc->dc_iobase, dc->dc_ioflags);
if (ret)
return ret;
ret = igsfb_cnattach_subr(dc);
if (ret)
return ret;
igsfb_pci_console = 1;
igsfb_pci_constag = tag;
return 0;
}
void
ibmnws_pci_indirect_attach_hook(struct device *parent, struct device *self,
struct pcibus_attach_args *pba)
{
if (pba->pba_bus != 0)
return;
printf(": indirect configuration space access");
#if defined(OPENPIC)
if (openpic_base) {
pci_chipset_tag_t pc;
pcitag_t tag;
pcireg_t id, address;
pc = pba->pba_pc;
tag = pci_make_tag(pc, 0, 13, 0);
id = pci_conf_read(pc, tag, PCI_ID_REG);
if (PCI_VENDOR(id) == PCI_VENDOR_IBM
&& PCI_PRODUCT(id) == PCI_PRODUCT_IBM_MPIC) {
address = pci_conf_read(pc, tag, PCI_CBIO);
if ((address & PCI_MAPREG_TYPE_MASK) == PCI_MAPREG_TYPE_MEM) {
address &= PCI_MAPREG_MEM_ADDR_MASK;
openpic_base = (unsigned char *)(PREP_BUS_SPACE_MEM | address);
}
}
}
#endif /* OPENPIC */
}
static int
pchbmatch(device_t parent, cfdata_t cf, void *aux)
{
struct plb_attach_args *paa = aux;
/* XXX chipset tag unused by walnut, so just pass 0 */
pci_chipset_tag_t pc = 0;
pcitag_t tag;
int class, id;
/* match only pchb devices */
if (strcmp(paa->plb_name, cf->cf_name) != 0)
return 0;
pci_machdep_init();
tag = pci_make_tag(pc, 0, 0, 0);
class = pci_conf_read(pc, tag, PCI_CLASS_REG);
id = pci_conf_read(pc, tag, PCI_ID_REG);
/*
* Match all known PCI host chipsets.
*/
if (PCI_CLASS(class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_HOST) {
switch (PCI_VENDOR(id)) {
case PCI_VENDOR_IBM:
switch (PCI_PRODUCT(id)) {
case PCI_PRODUCT_IBM_405GP:
return (!pcifound);
}
break;
}
}
return (0);
}
void
aapic_attach(struct device *parent, struct device *self, void *aux)
{
struct pci_attach_args *pa = aux;
int bus, dev, func;
pcitag_t tag;
pcireg_t reg;
printf("\n");
#if NIOAPIC > 0
if (nioapics == 0)
return;
#else
return;
#endif
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AMD8131_IOAPIC_CTL);
reg |= AMD8131_IOAEN;
pci_conf_write(pa->pa_pc, pa->pa_tag, AMD8131_IOAPIC_CTL, reg);
pci_decompose_tag(pa->pa_pc, pa->pa_tag, &bus, &dev, &func);
func = 0;
tag = pci_make_tag(pa->pa_pc, bus, dev, func);
reg = pci_conf_read(pa->pa_pc, tag, AMD8131_PCIX_MISC);
reg &= ~AMD8131_NIOAMODE;
pci_conf_write(pa->pa_pc, tag, AMD8131_PCIX_MISC, reg);
}
static void
sdhc_pci_quirk_ti_hack(struct pci_attach_args *pa)
{
pci_chipset_tag_t pc = pa->pa_pc;
pcitag_t tag;
pcireg_t id, reg;
/* Look at func - 1 for the flash device */
tag = pci_make_tag(pc, pa->pa_bus, pa->pa_device, pa->pa_function - 1);
id = pci_conf_read(pc, tag, PCI_ID_REG);
if (PCI_VENDOR(id) != PCI_VENDOR_TI) {
return;
}
switch (PCI_PRODUCT(id)) {
case PCI_PRODUCT_TI_PCI72111FM:
case PCI_PRODUCT_TI_PCIXX12FM:
break;
default:
return;
}
/*
* Disable MMC/SD on the flash media controller so the
* SD host takes over.
*/
reg = pci_conf_read(pc, tag, SDHC_PCI_GENERAL_CTL);
reg |= MMC_SD_DIS;
pci_conf_write(pc, tag, SDHC_PCI_GENERAL_CTL, reg);
}
/*
* Initialize the PCI-bus. The Atari-BIOS does not do this, so....
* We only disable all devices here. Memory and I/O enabling is done
* later at pcibusattach.
*/
void
init_pci_bus(void)
{
pci_chipset_tag_t pc = NULL; /* XXX */
pcitag_t tag;
pcireg_t csr;
int device, id, maxndevs;
tag = 0;
id = 0;
maxndevs = pci_bus_maxdevs(pc, 0);
for (device = 0; device < maxndevs; device++) {
tag = pci_make_tag(pc, 0, device, 0);
id = pci_conf_read(pc, tag, PCI_ID_REG);
if (id == 0 || id == 0xffffffff)
continue;
csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
csr &= ~PCI_COMMAND_MASTER_ENABLE;
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
}
}
void
pciaddr_remap(pci_chipset_tag_t pc)
{
pcitag_t devtag;
int device;
/* Must fix up all PCI devices, ahc_pci expects proper i/o mapping */
for (device = 1; device < 4; device++) {
const struct pci_quirkdata *qd;
int function, nfuncs;
pcireg_t bhlcr, id;
devtag = pci_make_tag(pc, 0, device, 0);
id = pci_conf_read(pc, devtag, PCI_ID_REG);
/* Invalid vendor ID value? */
if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
continue;
/* XXX Not invalid, but we've done this ~forever. */
if (PCI_VENDOR(id) == 0)
continue;
qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id));
bhlcr = pci_conf_read(pc, devtag, PCI_BHLC_REG);
if (PCI_HDRTYPE_MULTIFN(bhlcr) ||
(qd != NULL &&
(qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0))
nfuncs = 8;
else
nfuncs = 1;
for (function = 0; function < nfuncs; function++) {
devtag = pci_make_tag(pc, 0, device, function);
id = pci_conf_read(pc, devtag, PCI_ID_REG);
/* Invalid vendor ID value? */
if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
continue;
/* Not invalid, but we've done this ~forever */
if (PCI_VENDOR(id) == 0)
continue;
pciaddr_resource_manage(pc, devtag, NULL);
}
}
}
int
cy82c693_setup_elcr(void)
{
int device, maxndevs;
pcitag_t tag;
pcireg_t id;
/*
* Search PCI configuration space for a Cypress CY82C693.
*
* Note we can make some assumptions about our bus number
* here, because:
*
* (1) there can be at most one ISA/EISA bridge per PCI bus, and
*
* (2) any ISA/EISA bridges must be attached to primary PCI
* busses (i.e. bus zero).
*/
maxndevs = pci_bus_maxdevs(sio_pc, 0);
for (device = 0; device < maxndevs; device++) {
tag = pci_make_tag(sio_pc, 0, device, 0);
id = pci_conf_read(sio_pc, tag, PCI_ID_REG);
/* Invalid vendor ID value? */
if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
continue;
/* XXX Not invalid, but we've done this ~forever. */
if (PCI_VENDOR(id) == 0)
continue;
if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ ||
PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693)
continue;
/*
* Found one!
*/
#if 0
printf("cy82c693_setup_elcr: found 82C693 at device %d\n",
device);
#endif
sio_cy82c693_handle = cy82c693_init(sio_iot);
sio_read_elcr = cy82c693_read_elcr;
sio_write_elcr = cy82c693_write_elcr;
return (0);
}
/*
* Didn't find a CY82C693.
*/
return (ENODEV);
}
/*
* Machine independent support for PCI serial console support.
*
* Scan the PCI bus for something which resembles a 16550
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: puccn.c,v 1.9 2007/01/13 18:59:31 cube Exp $");
#include "opt_kgdb.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcidevs.h>
#include <sys/termios.h>
#include <dev/ic/comreg.h>
#include <dev/ic/comvar.h>
#include <dev/cons.h>
#include <dev/pci/pucvar.h>
#include <dev/pci/puccn.h>
#ifndef CONSPEED
#define CONSPEED TTYDEF_SPEED
#endif
#ifndef CONMODE
#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE|CSTOPB|PARENB))|CS8) /* 8N1 */
#endif
#ifdef i386 /* Handle i386 directly */
int
cpu_comcnprobe(struct consdev *cn, struct pci_attach_args *pa)
{
pci_mode_detect();
pa->pa_iot = X86_BUS_SPACE_IO;
pa->pa_pc = 0;
pa->pa_tag = pci_make_tag(0, 0, 31, 0);
return 0;
}
static void
mainbus_attach(device_t parent, device_t self, void *aux)
{
struct mainbus_attach_args ma;
const struct mainbusdev *md;
#if defined(PCI_NETBSD_ENABLE_IDE) || defined(PCI_NETBSD_CONFIGURE)
struct malta_config *mcp = &malta_configuration;
pci_chipset_tag_t pc = &mcp->mc_pc;
#endif
#if defined(PCI_NETBSD_ENABLE_IDE)
pcitag_t idetag;
pcireg_t idetim;
#endif
mainbus_found = true;
printf("\n");
#if defined(PCI_NETBSD_CONFIGURE)
struct mips_cache_info * const mci = &mips_cache_info;
struct extent *ioext = extent_create("pciio", 0x00001000, 0x0000efff,
NULL, 0, EX_NOWAIT);
struct extent *memext = extent_create("pcimem", MALTA_PCIMEM1_BASE,
MALTA_PCIMEM1_BASE + MALTA_PCIMEM1_SIZE,
NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, ioext, memext, NULL, 0, mci->mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
#if defined(PCI_NETBSD_ENABLE_IDE)
/*
* Perhaps PMON has not enabled the IDE controller. Easy to
* fix -- just set the ENABLE bits for each channel in the
* IDETIM register. Just clear all the bits for the channel
* except for the ENABLE bits -- the `pciide' driver will
* properly configure it later.
*/
idetim = 0;
if (PCI_NETBSD_ENABLE_IDE & 0x01)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 0);
if (PCI_NETBSD_ENABLE_IDE & 0x02)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1);
/* pciide0 is pci device 10, function 1 */
idetag = pci_make_tag(pc, 0, 10, 1);
pci_conf_write(pc, idetag, PIIX_IDETIM, idetim);
#endif
for (md = mainbusdevs; md->md_name != NULL; md++) {
ma.ma_name = md->md_name;
ma.ma_addr = md->md_addr;
ma.ma_intr = md->md_intr;
(void) config_found_sm_loc(self, "mainbus", NULL, &ma,
mainbus_print, mainbus_submatch);
}
}
void
fix_node_irq(int node, struct pcibus_attach_args *pba)
{
struct {
u_int32_t phys_hi, phys_mid, phys_lo;
u_int32_t size_hi, size_lo;
} addr [8];
u_int32_t map[144];
int len;
pcitag_t tag;
u_int32_t irq;
u_int32_t intr;
int parent;
pci_chipset_tag_t pc = pba->pba_pc;
len = OF_getprop(node, "assigned-addresses", addr, sizeof(addr));
if (len == -1 || len < sizeof(addr[0]))
return;
/* if this node has a AAPL,interrupts property, firmware
* has initialized the register correctly.
*/
len = OF_getprop(node, "AAPL,interrupts", &intr, 4);
if (len != 4) {
parent = OF_parent(node);
irq = -1;
/* we want the first interrupt, set size_hi to 1 */
addr[0].size_hi = 1;
if (find_node_intr(parent, &addr[0].phys_hi, &irq) == -1) {
len = OF_getprop(node, "interrupts", map,
sizeof(map));
if (len != -1 && len != 4) {
irq = map[0];
} else
return;
}
} else
irq = intr;
/* program the interrupt line register with the value
* found in openfirmware
*/
tag = pci_make_tag(pc, pcibus(addr[0].phys_hi),
pcidev(addr[0].phys_hi), pcifunc(addr[0].phys_hi));
intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
intr &= ~PCI_INTERRUPT_LINE_MASK;
intr |= irq & PCI_INTERRUPT_LINE_MASK;
pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
}
int
ne_pci_ipkdb_attach(struct ipkdb_if *kip, bus_space_tag_t iot,
pci_chipset_tag_t pc, int bus, int dev)
{
struct pci_attach_args pa;
bus_space_tag_t nict, asict;
bus_space_handle_t nich, asich;
u_int32_t csr;
pa.pa_iot = iot;
pa.pa_pc = pc;
pa.pa_device = dev;
pa.pa_function = 0;
pa.pa_flags = PCI_FLAGS_IO_OKAY;
pa.pa_tag = pci_make_tag(pc, bus, dev, /*func*/0);
pa.pa_id = pci_conf_read(pc, pa.pa_tag, PCI_ID_REG);
pa.pa_class = pci_conf_read(pc, pa.pa_tag, PCI_CLASS_REG);
if (ne_pci_lookup(&pa) == NULL)
return -1;
if (pci_mapreg_map(&pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
&nict, &nich, NULL, NULL))
return -1;
asict = nict;
if (bus_space_subregion(nict, nich, NE2000_ASIC_OFFSET,
NE2000_ASIC_NPORTS, &asich)) {
bus_space_unmap(nict, nich, NE2000_NPORTS);
return -1;
}
/* Enable card */
csr = pci_conf_read(pc, pa.pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, pa.pa_tag, PCI_COMMAND_STATUS_REG,
csr | PCI_COMMAND_MASTER_ENABLE);
ipkdb_softc.sc_ne2000.sc_dp8390.sc_regt = nict;
ipkdb_softc.sc_ne2000.sc_dp8390.sc_regh = nich;
ipkdb_softc.sc_ne2000.sc_asict = asict;
ipkdb_softc.sc_ne2000.sc_asich = asich;
kip->port = &ipkdb_softc;
ipkdb_pc = pc;
ipkdb_tag = pa.pa_tag;
ne_kip = kip;
if (ne2000_ipkdb_attach(kip) < 0) {
bus_space_unmap(nict, nich, NE2000_NPORTS);
return -1;
}
return 0;
}
/*
* Big ugly hack to enable bridge/fix interrupts
*/
void
macppc_cardbus_init(pci_chipset_tag_t pc, pcitag_t tag)
{
u_int x;
static int initted = 0;
if (initted)
return;
initted = 1;
/* XXX What about other bridges? */
x = pci_conf_read(pc, tag, PCI_ID_REG);
if (PCI_VENDOR(x) == PCI_VENDOR_TI &&
PCI_PRODUCT(x) == PCI_PRODUCT_TI_PCI1211) {
/* For CardBus card. */
pci_conf_write(pc, tag, 0x18, 0x10010100);
/* Route INTA to MFUNC0 */
x = pci_conf_read(pc, tag, 0x8c);
x |= 0x02;
pci_conf_write(pc, tag, 0x8c, x);
tag = pci_make_tag(pc, 0, 0, 0);
x = pci_conf_read(pc, tag, PCI_ID_REG);
if (PCI_VENDOR(x) == PCI_VENDOR_MOT &&
PCI_PRODUCT(x) == PCI_PRODUCT_MOT_MPC106) {
/* Set subordinate bus number to 1. */
x = pci_conf_read(pc, tag, 0x40);
x |= 1 << 8;
pci_conf_write(pc, tag, 0x40, x);
}
}
if (PCI_VENDOR(x) == PCI_VENDOR_TI &&
(PCI_PRODUCT(x) == PCI_PRODUCT_TI_PCI1410 ||
PCI_PRODUCT(x) == PCI_PRODUCT_TI_PCI1510)) {
/* dont mess with the bus numbers or latency timer */
/* Route INTA to MFUNC0 */
x = pci_conf_read(pc, tag, 0x8c);
x |= 0x02;
pci_conf_write(pc, tag, 0x8c, x);
}
}
void
ibm4xx_show_pci_map(void)
{
pci_chipset_tag_t pc = &genppc_ibm4xx_chipset;
paddr_t la, lm, pl, ph;
pcitag_t tag;
setup_pcicfg_window();
printf("Local -> PCI map\n");
la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0LA);
lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA);
pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCILA);
ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCIHA);
printf("0: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
(lm & 2) ? "":"not ",
(lm & 1) ? "enabled":"disabled");
la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1LA);
lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1MA);
pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1PCILA);
ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1PCIHA);
printf("1: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
(lm & 2) ? "":"not ",
(lm & 1) ? "enabled":"disabled");
la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2LA);
lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2MA);
pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2PCILA);
ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2PCIHA);
printf("2: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
(lm & 2) ? "":"not ",
(lm & 1) ? "enabled":"disabled");
printf("PCI -> Local map\n");
tag = pci_make_tag(pc, 0, 0, 0);
pl = pci_conf_read(pc, tag, PCIC_PTM1BAR);
la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1LA);
lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS);
printf("1: %08lx -> %08lx,%08lx %s\n", pl, la, lm,
(lm & 1)?"enabled":"disabled");
pl = pci_conf_read(pc, tag, PCIC_PTM2BAR);
la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2LA);
lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2MS);
printf("2: %08lx -> %08lx,%08lx %s\n", pl, la, lm,
(lm & 1)?"enabled":"disabled");
}
void
sdhc_takecontroller(struct pci_attach_args *pa)
{
pcitag_t tag;
pcireg_t id, reg;
/* Look at func 3 for the flash device */
tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 3);
id = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
if (PCI_PRODUCT(id) != PCI_PRODUCT_TI_PCI7XX1_FLASH)
return;
/*
* Disable MMC/SD on the flash media controller so the
* SD host takes over.
*/
reg = pci_conf_read(pa->pa_pc, tag, SDHC_PCI_GENERAL_CTL);
reg |= MMC_SD_DIS;
pci_conf_write(pa->pa_pc, tag, SDHC_PCI_GENERAL_CTL, reg);
}
/*
* Determine which flags should be passed to the primary PCI bus's
* autoconfiguration node. We use this to detect broken chipsets
* which cannot safely use memory-mapped device access.
*/
int
pci_bus_flags()
{
int rval = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
int device, maxndevs;
pcitag_t tag;
pcireg_t id;
maxndevs = pci_bus_maxdevs(NULL, 0);
for (device = 0; device < maxndevs; device++) {
tag = pci_make_tag(NULL, 0, device, 0);
id = pci_conf_read(NULL, tag, PCI_ID_REG);
/* Invalid vendor ID value? */
if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
continue;
/* XXX Not invalid, but we've done this ~forever. */
if (PCI_VENDOR(id) == 0)
continue;
switch (PCI_VENDOR(id)) {
case PCI_VENDOR_SIS:
switch (PCI_PRODUCT(id)) {
case PCI_PRODUCT_SIS_85C496:
goto disable_mem;
}
break;
}
}
return (rval);
disable_mem:
printf("Warning: broken PCI-Host bridge detected; "
"disabling memory-mapped access\n");
rval &= ~(PCI_FLAGS_MEM_ENABLED|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY|
PCI_FLAGS_MWI_OKAY);
return (rval);
}
void
pcidevdetached(device_t self, device_t child)
{
struct pci_softc *sc = device_private(self);
int d, f;
pcitag_t tag;
struct pci_child *c;
d = device_locator(child, PCICF_DEV);
f = device_locator(child, PCICF_FUNCTION);
c = &sc->PCI_SC_DEVICESC(d, f);
KASSERT(c->c_dev == child);
tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f);
if (c->c_psok)
pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate);
pci_conf_restore(sc->sc_pc, tag, &c->c_conf);
c->c_dev = NULL;
}
int
pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id)
{
/* ignore bogus IDs */
if (PCI_VENDOR(id) == 0)
return 0;
/* 2700 hardware wedges on accesses to device 6. */
if (bus == 0 && dev == 6)
return 0;
/* 2800 hardware wedges on accesses to device 31. */
if (bus == 0 && dev == 31)
return 0;
/* Don't configure the bridge and PCI probe. */
if (PCI_VENDOR(id) == PCI_VENDOR_MARVELL &&
PCI_PRODUCT(id) == PCI_PRODUCT_MARVELL_GT64011)
return 0;
/* Don't configure on-board VIA VT82C586 (pcib, uhci) */
if (bus == 0 && dev == 9 && (func == 0 || func == 2))
return 0;
/* Enable viaide secondary port. Some firmware doesn't enable it. */
if (bus == 0 && dev == 9 && func == 1) {
pcitag_t tag;
pcireg_t csr;
#define APO_VIAIDECONF (APO_VIA_REGBASE + 0x00)
tag = pci_make_tag(pc, bus, dev, func);
csr = pci_conf_read(pc, tag, APO_VIAIDECONF);
pci_conf_write(pc, tag, APO_VIAIDECONF,
csr | APO_IDECONF_EN(1));
}
return PCI_CONF_DEFAULT & ~(PCI_COMMAND_SERR_ENABLE |
PCI_COMMAND_PARITY_ENABLE);
}
static int
pciioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
{
struct pci_softc *sc = device_lookup_private(&pci_cd, minor(dev));
struct pciio_bdf_cfgreg *bdfr;
struct pciio_businfo *binfo;
pcitag_t tag;
switch (cmd) {
case PCI_IOC_BDF_CFGREAD:
case PCI_IOC_BDF_CFGWRITE:
bdfr = data;
if (bdfr->bus > 255 || bdfr->device >= sc->sc_maxndevs ||
bdfr->function > 7)
return EINVAL;
tag = pci_make_tag(sc->sc_pc, bdfr->bus, bdfr->device,
bdfr->function);
if (cmd == PCI_IOC_BDF_CFGREAD) {
bdfr->cfgreg.val = pci_conf_read(sc->sc_pc, tag,
bdfr->cfgreg.reg);
} else {
if ((flag & FWRITE) == 0)
return EBADF;
pci_conf_write(sc->sc_pc, tag, bdfr->cfgreg.reg,
bdfr->cfgreg.val);
}
return 0;
case PCI_IOC_BUSINFO:
binfo = data;
binfo->busno = sc->sc_bus;
binfo->maxdevs = sc->sc_maxndevs;
return 0;
default:
return ENOTTY;
}
}
/*
* Set up the chipset's function pointers.
*/
void
irongate_init(struct irongate_config *icp, int mallocsafe)
{
pcitag_t tag;
pcireg_t reg;
icp->ic_mallocsafe = mallocsafe;
/*
* Set up PCI configuration space; we can only read the
* revision info through configuration space.
*/
irongate_pci_init(&icp->ic_pc, icp);
#if 0
alpha_pci_chipset = &icp->ic_pc;
#endif
tag = pci_make_tag(&icp->ic_pc, 0, IRONGATE_PCIHOST_DEV, 0);
/* Read the revision. */
reg = irongate_conf_read0(icp, tag, PCI_CLASS_REG);
icp->ic_rev = PCI_REVISION(reg);
if (icp->ic_initted == 0) {
/* Don't do these twice, since they set up extents. */
icp->ic_iot = irongate_bus_io_init(icp);
icp->ic_memt = irongate_bus_mem_init(icp);
#if 0
/* Only one each PCI I/O and MEM window. */
alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1;
alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1;
alpha_bus_get_window = irongate_bus_get_window;
#endif
}
icp->ic_initted = 1;
}
void
lemote_pci_attach_hook(pci_chipset_tag_t pc)
{
pcireg_t id;
pcitag_t tag;
int dev;
/*
* Check for an AMD CS5536 chip; if one is found, register
* the proper PCI configuration space hooks.
*/
for (dev = pci_bus_maxdevs(pc, 0); dev >= 0; dev--) {
tag = pci_make_tag(pc, 0, dev, 0);
id = pci_conf_read(pc, tag, PCI_ID_REG);
if (id == PCI_ID_CODE(PCI_VENDOR_AMD,
PCI_PRODUCT_AMD_CS5536_PCISB)) {
glx_init(pc, tag, dev);
break;
}
}
}
static void
scan_pci_bus(void)
{
pcitag_t tag;
int i, x;
for (i=0;i<32;i++){
tag = pci_make_tag(0, 0, i, 0);
x = pci_conf_read(0, tag, 0);
printf("%d tag=%08x : %08x\n", i, tag, x);
#if 0
if (PCI_VENDOR(x) == PCI_VENDOR_INTEL
&& PCI_PRODUCT(x) == PCI_PRODUCT_INTEL_80960_RP) {
/* Do not configure PCI bus analyzer */
continue;
}
x = pci_conf_read(0, tag, PCI_COMMAND_STATUS_REG);
x |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
pci_conf_write(0, tag, PCI_COMMAND_STATUS_REG, x);
#endif
}
}
/*
* AcpiOsWritePciConfiguration:
*
* Write a value to a PCI configuration register.
*/
ACPI_STATUS
AcpiOsWritePciConfiguration(ACPI_PCI_ID *PciId, UINT32 Register,
ACPI_INTEGER Value, UINT32 Width)
{
pcitag_t tag;
pcireg_t tmp;
/* XXX Need to deal with "segment" ("hose" in Alpha terminology). */
tag = pci_make_tag(acpi_softc->sc_pc, PciId->Bus, PciId->Device,
PciId->Function);
switch (Width) {
case 8:
tmp = pci_conf_read(acpi_softc->sc_pc, tag, Register & ~3);
tmp &= ~(0xff << ((Register & 3) * 8));
tmp |= (Value << ((Register & 3) * 8));
break;
case 16:
tmp = pci_conf_read(acpi_softc->sc_pc, tag, Register & ~3);
tmp &= ~(0xffff << ((Register & 3) * 8));
tmp |= (Value << ((Register & 3) * 8));
break;
case 32:
tmp = Value;
break;
default:
return AE_BAD_PARAMETER;
}
pci_conf_write(acpi_softc->sc_pc, tag, Register & ~3, tmp);
return AE_OK;
}
int
pci_conf_hook(void *v, int bus, int dev, int func, pcireg_t id)
{
/*
* We need to disable devices in the Southbridge, and as
* we have all the tags we need at this point, this is
* where we do it.
*/
if (PCI_VENDOR(id) == PCI_VENDOR_ALI &&
PCI_PRODUCT(id) == PCI_PRODUCT_ALI_M1543)
{
pcitag_t tag;
int status;
pci_chipset_tag_t pc = (pci_chipset_tag_t) v;
tag = pci_make_tag(pc, bus, dev, func);
/* Undocumented magic */
/* Disable USB */
pci_conf_write_byte(pc, tag, 0x53, 0x40);
pci_conf_write_byte(pc, tag, 0x52, 0x00);
status = pci_conf_read_byte(pc, tag, 0x7e);
pci_conf_write_byte(pc, tag, 0x7e, status & ~0x80);
/* Disable modem */
pci_conf_write_byte(pc, tag, 0x77, 1 << 6);
/* Disable SCI */
pci_conf_write_byte(pc, tag, 0x78, 1 << 7);
}
return (PCI_CONF_DEFAULT);
}
