static void gma_func0_init(struct device *dev)
{
u32 reg32;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* configure GMBUSFREQ */
pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc);
int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1;
if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
if (vga_disable) {
printk(BIOS_INFO,
"IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
} else {
int lightup_ok;
gma_gfxinit(&lightup_ok);
}
} else {
pci_dev_init(dev);
}
intel_gma_restore_opregion();
}
static void pch_pcie_init(struct device *dev)
{
u16 reg16;
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
/* Enable SERR */
pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
/* Enable Bus Master */
pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Set Cache Line Size to 0x10 */
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
/* disable parity error response, enable ISA */
pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2);
if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) {
printk(BIOS_SPEW, " MBL = 0x%08x\n",
pci_read_config32(dev, PCI_MEMORY_BASE));
printk(BIOS_SPEW, " PMBL = 0x%08x\n",
pci_read_config32(dev, PCI_PREF_MEMORY_BASE));
printk(BIOS_SPEW, " PMBU32 = 0x%08x\n",
pci_read_config32(dev, PCI_PREF_BASE_UPPER32));
printk(BIOS_SPEW, " PMLU32 = 0x%08x\n",
pci_read_config32(dev, PCI_PREF_LIMIT_UPPER32));
}
/* Clear errors in status registers */
reg16 = pci_read_config16(dev, PCI_STATUS);
pci_write_config16(dev, PCI_STATUS, reg16);
reg16 = pci_read_config16(dev, PCI_SEC_STATUS);
pci_write_config16(dev, PCI_SEC_STATUS, reg16);
}
