void smbus_enable(void) { /* iobase addr */ pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* smbus enable */ pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN); /* iospace enable */ pcibios_write_config_word(PM_BUS, PM_DEVFN, PCI_COMMAND, PCI_COMMAND_IO); /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); }
void smbus_enable(void) { unsigned char byte; /* iobase addr */ pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x20, SMBUS_IO_BASE | 1); /* smbus enable */ pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1); /* iospace enable */ pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1); /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); }
asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn, unsigned long off, unsigned long len, unsigned char *buf) { unsigned char ubyte; unsigned short ushort; unsigned int uint; long err = 0; if (!capable(CAP_SYS_ADMIN)) return -EPERM; if (!pcibios_present()) return -ENOSYS; switch (len) { case 1: err = get_user(ubyte, buf); if (err) break; err = pcibios_write_config_byte(bus, dfn, off, ubyte); if (err != PCIBIOS_SUCCESSFUL) { err = -EFAULT; } break; case 2: err = get_user(ushort, (unsigned short *)buf); if (err) break; err = pcibios_write_config_word(bus, dfn, off, ushort); if (err != PCIBIOS_SUCCESSFUL) { err = -EFAULT; } break; case 4: err = get_user(uint, (unsigned int *)buf); if (err) break; err = pcibios_write_config_dword(bus, dfn, off, uint); if (err != PCIBIOS_SUCCESSFUL) { err = -EFAULT; } break; default: err = -EINVAL; break; } return err; }
void UxPciConfigWrite(ux_diva_card_t *card, int size, int offset, void *value) { switch (size) { case sizeof(byte): pcibios_write_config_byte(card->bus_num, card->func_num, offset, * (byte *) value); break; case sizeof(word): pcibios_write_config_word(card->bus_num, card->func_num, offset, * (word *) value); break; case sizeof(dword): pcibios_write_config_dword(card->bus_num, card->func_num, offset, * (dword *) value); break; default: printk(KERN_WARNING "Divas: Invalid size in UxPciConfigWrite\n"); } }
__initfunc(int w83c553f_init(void)) { u_char bus, dev; #if 0 unsigned char t8; unsigned short t16; #endif unsigned int t32; struct pci_dev *pdev; if ((pdev = pci_find_device(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, NULL))) { bus = pdev->bus->number; dev = pdev->devfn + 1; pcibios_read_config_dword(bus, dev, PCI_VENDOR_ID, &t32); if (t32 == (PCI_DEVICE_ID_WINBOND_82C105<<16) + PCI_VENDOR_ID_WINBOND) { #if 0 printk("Enabling SL82C105 IDE on W83C553F\n"); /* * FIXME: this doesn't help :-( */ /* I/O mapping */ pcibios_read_config_word(bus, dev, PCI_COMMAND, &t16); t16 |= PCI_COMMAND_IO; pcibios_write_config_word(bus, dev, PCI_COMMAND, t16); /* Standard IDE registers */ pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_0, 0xffffffff); pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_0, &t32); pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_0, 0x000001f0 | 1); pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_1, 0xffffffff); pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_1, &t32); pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_1, 0x000003f4 | 1); pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_2, 0xffffffff); pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_2, &t32); pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_2, 0x00000170 | 1); pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_3, 0xffffffff); pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_3, &t32); pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_3, 0x00000374 | 1); /* IDE Bus Master Control */ pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_4, 0xffffffff); pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_4, &t32); pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_4, 0x1000 | 1); pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_5, 0xffffffff); pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_5, &t32); pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_5, 0x1010 | 1); /* IDE Interrupt */ pcibios_read_config_byte(bus, dev, PCI_INTERRUPT_LINE, &t8); chrp_ide_irq = t8; #endif return 1; } } return 0; }
static int RCscan(void) { int cards_found = 0; struct device *dev = 0; if (pcibios_present()) { static int pci_index = 0; unsigned char pci_bus, pci_device_fn; int scan_status; int board_index = 0; for (; pci_index < 0xff; pci_index++) { unsigned char pci_irq_line; unsigned short pci_command, vendor, device, class; unsigned int pci_ioaddr; scan_status = (pcibios_find_device (RC_PCI45_VENDOR_ID, RC_PCI45_DEVICE_ID, pci_index, &pci_bus, &pci_device_fn)); #ifdef RCDEBUG printk("rc scan_status = 0x%X\n", scan_status); #endif if (scan_status != PCIBIOS_SUCCESSFUL) break; pcibios_read_config_word(pci_bus, pci_device_fn, PCI_VENDOR_ID, &vendor); pcibios_read_config_word(pci_bus, pci_device_fn, PCI_DEVICE_ID, &device); pcibios_read_config_byte(pci_bus, pci_device_fn, PCI_INTERRUPT_LINE, &pci_irq_line); pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_0, &pci_ioaddr); pcibios_read_config_word(pci_bus, pci_device_fn, PCI_CLASS_DEVICE, &class); pci_ioaddr &= ~0xf; #ifdef RCDEBUG printk("rc: Found RedCreek PCI adapter\n"); printk("rc: pci class = 0x%x 0x%x \n", class, class>>8); printk("rc: pci_bus = %d, pci_device_fn = %d\n", pci_bus, pci_device_fn); printk("rc: pci_irq_line = 0x%x \n", pci_irq_line); printk("rc: pci_ioaddr = 0x%x\n", pci_ioaddr); #endif #if 0 if (check_region(pci_ioaddr, 32768)) { printk("rc: check_region failed\n"); continue; } else { printk("rc: check_region passed\n"); } #endif /* * Get and check the bus-master and latency values. * Some PCI BIOSes fail to set the master-enable bit. */ pcibios_read_config_word(pci_bus, pci_device_fn, PCI_COMMAND, &pci_command); if ( ! (pci_command & PCI_COMMAND_MASTER)) { printk("rc: PCI Master Bit has not been set!\n"); pci_command |= PCI_COMMAND_MASTER; pcibios_write_config_word(pci_bus, pci_device_fn, PCI_COMMAND, pci_command); } if ( ! (pci_command & PCI_COMMAND_MEMORY)) { /* * If the BIOS did not set the memory enable bit, what else * did it not initialize? Skip this adapter. */ printk("rc: Adapter %d, PCI Memory Bit has not been set!\n", cards_found); printk("rc: Bios problem? \n"); continue; } dev = RCfound_device(dev, pci_ioaddr, pci_irq_line, pci_bus, pci_device_fn, board_index++, cards_found); if (dev) { dev = 0; cards_found++; } } } printk("rc: found %d cards \n", cards_found); return cards_found; }
/***************************************************************************** Function name : orc_ReturnNumberOfAdapters Description : This function will scan PCI bus to get all Orchid card Input : None. Output : None. Return : SUCCESSFUL - Successful scan ohterwise - No drives founded *****************************************************************************/ int orc_ReturnNumberOfAdapters(void) { unsigned int i, iAdapters; iAdapters = 0; /* * PCI-bus probe. */ if (pcibios_present()) { struct { unsigned short vendor_id; unsigned short device_id; } const inia100_pci_devices[] = { {ORC_VENDOR_ID, I920_DEVICE_ID}, {ORC_VENDOR_ID, ORC_DEVICE_ID} }; unsigned int dRegValue; unsigned short command; WORD wBIOS, wBASE; BYTE bPCIBusNum, bInterrupt, bPCIDeviceNum; #ifdef MMAPIO unsigned long page_offset, base; #endif #if LINUX_VERSION_CODE > CVT_LINUX_VERSION(2,1,92) struct pci_dev *pdev = NULL; #else int index; unsigned char pci_bus, pci_devfn; #endif bPCIBusNum = 0; bPCIDeviceNum = 0; init_inia100Adapter_table(); for (i = 0; i < NUMBER(inia100_pci_devices); i++) { #if LINUX_VERSION_CODE > CVT_LINUX_VERSION(2,1,92) pdev = NULL; while ((pdev = pci_find_device(inia100_pci_devices[i].vendor_id, inia100_pci_devices[i].device_id, pdev))) #else index = 0; while (!(pcibios_find_device(inia100_pci_devices[i].vendor_id, inia100_pci_devices[i].device_id, index++, &pci_bus, &pci_devfn))) #endif { if (iAdapters >= MAX_SUPPORTED_ADAPTERS) break; /* Never greater than maximum */ if (i == 0) { /* printk("inia100: The RAID controller is not supported by\n"); printk("inia100: this driver, we are ignoring it.\n"); */ } else { /* * Read sundry information from PCI BIOS. */ #if LINUX_VERSION_CODE > CVT_LINUX_VERSION(2,1,92) bPCIBusNum = pdev->bus->number; bPCIDeviceNum = pdev->devfn; dRegValue = pdev->base_address[0]; if (dRegValue == -1) { /* Check return code */ printk("\n\rinia100: orchid read configuration error.\n"); return (0); /* Read configuration space error */ } /* <02> read from base address + 0x50 offset to get the wBIOS balue. */ wBASE = (WORD) dRegValue; /* Now read the interrupt line */ dRegValue = pdev->irq; bInterrupt = dRegValue & 0xFF; /* Assign interrupt line */ pci_read_config_word(pdev, PCI_COMMAND, &command); pci_write_config_word(pdev, PCI_COMMAND, command | PCI_COMMAND_MASTER | PCI_COMMAND_IO); #else bPCIBusNum = pci_bus; bPCIDeviceNum = pci_devfn; pcibios_read_config_dword(pci_bus, pci_devfn, PCI_BASE_ADDRESS_0, &dRegValue); if (dRegValue == -1) { /* Check return code */ printk("\n\rinia100: Orchid read configuration error.\n"); return (0); /* Read configuration space error */ } /* <02> read from base address + 0x50 offset to get the wBIOS balue. */ wBASE = (WORD) dRegValue; /* Now read the interrupt line */ pcibios_read_config_dword(pci_bus, pci_devfn, PCI_INTERRUPT_LINE, &dRegValue); bInterrupt = dRegValue & 0xFF; /* Assign interrupt line */ pcibios_read_config_word(pci_bus, pci_devfn, PCI_COMMAND, &command); pcibios_write_config_word(pci_bus, pci_devfn, PCI_COMMAND, command | PCI_COMMAND_MASTER | PCI_COMMAND_IO); #endif wBASE &= PCI_BASE_ADDRESS_IO_MASK; wBIOS = ORC_RDWORD(wBASE, 0x50); #ifdef MMAPIO base = wBASE & PAGE_MASK; page_offset = wBASE - base; /* * replace the next line with this one if you are using 2.1.x: * temp_p->maddr = ioremap(base, page_offset + 256); */ #if LINUX_VERSION_CODE >= CVT_LINUX_VERSION(2,1,0) wBASE = ioremap(base, page_offset + 256); #else wBASE = (WORD) vremap(base, page_offset + 256); #endif if (wBASE) { wBASE += page_offset; } #endif if (Addinia100_into_Adapter_table(wBIOS, wBASE, bInterrupt, bPCIBusNum, bPCIDeviceNum) == SUCCESSFUL) iAdapters++; } } /* while(pdev=....) */ } /* for PCI_DEVICES */ } /* PCI BIOS present */ return (iAdapters); }
/* scan the pci bus look for vendor/device Id == Siemens PITA if found look for subvendor id if found write to pita register 1c in the first address range the value 0x04000000 */ int pcimod_scan(void) { int i, pos = 0; int bus, fun; unsigned char headertype = 0; u32 id; u32 vdid; /* vendor/device id */ int candev = 0; /* number of found devices */ if (!pcibios_present()) { printk("CAN: No PCI bios present\n"); return ENODEV; } /* printk("CAN: PCI bios present!\n"); */ /* * This code is derived from "drivers/pci/pci.c". This means that * the GPL applies to this source file and credit is due to the * original authors (Drew Eckhardt, Frederic Potter, David * Mosberger-Tang) */ for (bus = 0; !bus; bus++) { /* only bus 0 :-) */ for (fun=0; fun < 0x100 && pos < PAGE_SIZE; fun++) { if (!PCI_FUNC(fun)) /* first function */ pcibios_read_config_byte(bus,fun,PCI_HEADER_TYPE, &headertype); else if (!(headertype & 0x80)) continue; /* the following call gets vendor AND device ID */ pcibios_read_config_dword(bus, fun, PCI_VENDOR_ID, &id); if (!id || id == ~0) { headertype = 0; continue; } /* v-endor and d-evice id */ vdid = id; #if 0 printk(" -- found pci device, vendor id = %u/0x%x , device 0x%x\n", (id & 0xffff), (id & 0xffff), (id >> 16)); #endif pcibios_read_config_dword(bus, fun, PCI_CLASS_REVISION, &id); #if 0 printk(" class 0x%x, Revision %d\n", (id >> 8), (id & 0x0ff)); #endif if(vdid == (PCI_VENDOR + (PCI_DEVICE << 16))) { unsigned char irq; u16 cmd; u32 svdid; /* subsystem vendor/device id */ /* found EMS CAN CPC-PCI */ vdid = 0; /* reset it */ printk(" found Siemens PITA PCI-Chip\n"); pcibios_read_config_byte(bus, fun, PCI_INTERRUPT_LINE, &irq); printk(" using IRQ %d\n", irq); pcibios_read_config_word(bus, fun, PCI_COMMAND, &cmd); /* printk(" cmd: 0x%x\n", cmd); */ /* PCI_COMMAND should be at least PCI_COMMAND_MEMORY */ pcibios_write_config_word(bus, fun, /* PCI_COMMAND, PCI_COMMAND_MEMORY); */ PCI_COMMAND, PCI_COMMAND_MEMORY + PCI_COMMAND_MASTER ); pcibios_read_config_word(bus, fun, PCI_COMMAND, &cmd); /* printk(" cmd: 0x%x\n", cmd); */ pcibios_read_config_dword(bus, fun, PCI_SUBSYSTEM_VENDOR_ID, &svdid); /* printk(" s_vendor 0x%x, s_device 0x%x\n", */ /* (svdid & 0xffff), (svdid >> 16)); */ /* How can we be sure that that is an EMS CAN card ?? */ for (i = 0; addresses[i]; i++) { u32 curr, mask; char *type; pcibios_read_config_dword(bus, fun, addresses[i], &curr); cli(); pcibios_write_config_dword(bus, fun, addresses[i], ~0); pcibios_read_config_dword(bus, fun, addresses[i], &mask); pcibios_write_config_dword(bus, fun, addresses[i], curr); sti(); /* printk(" region %i: mask 0x%08lx, now at 0x%08lx\n", i, */ /* (unsigned long)mask, */ /* (unsigned long)curr); */ #if 0 /* we don't need this message, so we don't need this code */ if (!mask) { printk(" region %i not existent\n", i); break; } #endif /* extract the type, and the programmable bits */ if (mask & PCI_BASE_ADDRESS_SPACE) { type = "I/O"; mask &= PCI_BASE_ADDRESS_IO_MASK; } else { type = "mem"; mask &= PCI_BASE_ADDRESS_MEM_MASK; } /* printk(" region %i: type %s, size %i\n", i, */ /* type, ~mask+1); */ if(i == 0) { /* BAR0 internal PITA registers */ unsigned long ptr = (unsigned long)ioremap(curr, 256); /* enable memory access */ /* printk("write to pita\n"); */ writel(0x04000000, ptr + 0x1c); Can_pitapci_control[candev] = ptr; } if(i == 1) { /* BAR1 parallel I/O * at address 0 are some EMS control registers * at address 0x400 the first controller area * at address 0x600 the second controller area * registers are read as 32bit * * at adress 0 we can verify the card * 0x55 0xaa 0x01 0xcb */ /* dump_CAN(curr, 4); */ reset_CPC_PCI(curr); /* enable interrupts Int_0 */ /* write to PITAs ICR register */ writel(0x00020000, Can_pitapci_control[candev] + 0x0); /* dump_CAN(curr + 0x400, 4); */ if(controller_available(curr + 0x400, 4)) { printk("CAN: at pos 1\n"); if(candev > 4) { printk("CAN: only 4 devices supported\n"); break; /* the devices scan loop */ } Base[candev] = (unsigned long)ioremap(curr + 0x400, 32*4); IOModel[candev] = 'm'; IRQ[candev] = irq; candev++; } else { printk("CAN: NO at pos 1\n"); } /* dump_CAN(curr + 0x600, 4); */ if(controller_available(curr + 0x600, 4)) { printk("CAN: at pos 2\n"); if(candev > 4) { printk("CAN: only 4 devices supported\n"); break; /* the devices scan loop */ } /* share the board control register with prev ch */ Can_pitapci_control[candev] = Can_pitapci_control[candev - 1]; Base[candev] = (unsigned long)ioremap(curr + 0x600, 32*4); IOModel[candev] = 'm'; IRQ[candev] = irq; candev++; } else { printk("CAN: NO at pos 2\n"); } } } } /* EMS CPC-PCI */ } /* for all devices */ } /* for all busses */ return 0; }
void pcicfg_write_word(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U16 v) { pcibios_write_config_word(bus, (dev<<3)|func, reg, v); }
int DivasCardsDiscover(void) { word wNumCards = 0, wDeviceIndex = 0; byte byBus, byFunc; word wPCIConsultation, PCItmp; dword j, i; unsigned int PCIserial; dia_card_t Card; byte *b; while (wDeviceIndex < 10) { wPCIConsultation = pcibios_find_device(PCI_VENDOR_ID_EICON, PCI_DEVICE_ID_EICON_MAESTRAQ, wDeviceIndex, &byBus, &byFunc); if (wPCIConsultation == PCIBIOS_SUCCESSFUL) { dword dwRAM, dwDivasIOBase, dwCFG, dwCTL; byte byIRQ; printk(KERN_DEBUG "Divas: DIVA Server 4BRI Found\n"); pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_2,(unsigned int *) &dwRAM); dwRAM &= 0xFFC00000; pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_1,(unsigned int *) &dwDivasIOBase); dwDivasIOBase &= 0xFFFFFF00; pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_0,(unsigned int *) &dwCFG); dwCFG &= 0xFFFFFF00; pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_3,(unsigned int *) &dwCTL); dwCTL &= 0xFFFFE000; pcibios_read_config_byte(byBus, byFunc, PCI_INTERRUPT_LINE, &byIRQ); /* Retrieve the serial number */ pcibios_write_config_word(byBus,byFunc,0x4E,0x00FC); for (j=0, PCItmp=0; j<10000 && !PCItmp; j++) { pcibios_read_config_word(byBus,byFunc,0x4E, &PCItmp); PCItmp &= 0x8000; // extract done flag } pcibios_read_config_dword(byBus,byFunc,0x50, &PCIserial); Card.memory[DIVAS_RAM_MEMORY] = ioremap(dwRAM, 0x400000); Card.memory[DIVAS_CTL_MEMORY] = ioremap(dwCTL, 0x2000); Card.memory[DIVAS_CFG_MEMORY] = ioremap(dwCFG, 0x100); Card.io_base=dwDivasIOBase; Card.irq = byIRQ; Card.card_type = DIA_CARD_TYPE_DIVA_SERVER_Q; Card.bus_type = DIA_BUS_TYPE_PCI; FPGA_Done = 0; /* Create four virtual card structures as we want to treat the 4Bri card as 4 Bri cards*/ for(i=0;i<4;i++) { b=Card.memory[DIVAS_RAM_MEMORY]; b+=(MQ_PROTCODE_OFFSET) * (i==0?0:1); DPRINTF(("divas: offset = 0x%x", i* MQ_PROTCODE_OFFSET)); Card.memory[DIVAS_RAM_MEMORY]=b; b = Card.memory[DIVAS_RAM_MEMORY]; b += MQ_SM_OFFSET; Card.memory[DIVAS_SHARED_MEMORY] = b; Card.bus_num = byBus; Card.func_num = byFunc; Card.slot = -1; /* Fill in Name */ Card.name[0] = 'D'; Card.name[1] = 'I'; Card.name[2] = 'V'; Card.name[3] = 'A'; Card.name[4] = 'S'; Card.name[5] = 'Q'; Card.name[6] = '0' + i; Card.name[7] = '\0'; Card.serial = PCIserial; Card.card_id = wNumCards; if (DivasCardNew(&Card) != 0) { // Force for loop to terminate i = 4; continue; } wNumCards++; }//for } wDeviceIndex++; } wDeviceIndex = 0; while (wDeviceIndex < 10) { wPCIConsultation = pcibios_find_device(PCI_VENDOR_ID_EICON, PCI_DEVICE_ID_EICON_MAESTRA, wDeviceIndex, &byBus, &byFunc); if (wPCIConsultation == PCIBIOS_SUCCESSFUL) { dword dwPLXIOBase, dwDivasIOBase; byte byIRQ; printk(KERN_DEBUG "Divas: DIVA Server BRI (S/T) Found\n"); pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_1, (unsigned int *) &dwPLXIOBase); dwPLXIOBase &= 0xFFFFFF80; pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_2, (unsigned int *) &dwDivasIOBase); dwDivasIOBase &= 0xFFFFFFFC; pcibios_read_config_byte(byBus, byFunc, PCI_INTERRUPT_LINE, &byIRQ); Card.card_id = wNumCards; Card.card_type = DIA_CARD_TYPE_DIVA_SERVER_B; Card.bus_type = DIA_BUS_TYPE_PCI; Card.irq = byIRQ; Card.reset_base = dwPLXIOBase; Card.io_base = dwDivasIOBase; Card.bus_num = byBus; Card.func_num = byFunc; Card.slot = -1; Card.name[0] = 'D'; Card.name[1] = 'I'; Card.name[2] = 'V'; Card.name[3] = 'A'; Card.name[4] = 'S'; Card.name[5] = 'B'; Card.name[6] = '\0'; if (check_region(Card.io_base, 0x20)) { printk(KERN_WARNING "Divas: DIVA I/O Base already in use 0x%x-0x%x\n", Card.io_base, Card.io_base + 0x1F); wDeviceIndex++; continue; } if (check_region(Card.reset_base, 0x80)) { printk(KERN_WARNING "Divas: PLX I/O Base already in use 0x%x-0x%x\n", Card.reset_base, Card.reset_base + 0x7F); wDeviceIndex++; continue; } if (DivasCardNew(&Card) != 0) { wDeviceIndex++; continue; } wNumCards++; } wPCIConsultation = pcibios_find_device(PCI_VENDOR_ID_EICON, PCI_DEVICE_ID_EICON_MAESTRAQ_U, wDeviceIndex, &byBus, &byFunc); if (wPCIConsultation == PCIBIOS_SUCCESSFUL) { dword dwPLXIOBase, dwDivasIOBase; byte byIRQ; printk(KERN_DEBUG "Divas: DIVA Server BRI (U) Found\n"); pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_1, (unsigned int *) &dwPLXIOBase); dwPLXIOBase &= 0xFFFFFF80; pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_2, (unsigned int *) &dwDivasIOBase); dwDivasIOBase &= 0xFFFFFFFC; pcibios_read_config_byte(byBus, byFunc, PCI_INTERRUPT_LINE, &byIRQ); Card.card_id = wNumCards; Card.card_type = DIA_CARD_TYPE_DIVA_SERVER_B; Card.bus_type = DIA_BUS_TYPE_PCI; Card.irq = byIRQ; Card.reset_base = dwPLXIOBase; Card.io_base = dwDivasIOBase; Card.bus_num = byBus; Card.func_num = byFunc; Card.slot = -1; Card.name[0] = 'D'; Card.name[1] = 'I'; Card.name[2] = 'V'; Card.name[3] = 'A'; Card.name[4] = 'S'; Card.name[5] = 'B'; Card.name[6] = '\0'; if (check_region(Card.io_base, 0x20)) { printk(KERN_WARNING "Divas: DIVA I/O Base already in use 0x%x-0x%x\n", Card.io_base, Card.io_base + 0x1F); wDeviceIndex++; continue; } if (check_region(Card.reset_base, 0x80)) { printk(KERN_WARNING "Divas: PLX I/O Base already in use 0x%x-0x%x\n", Card.reset_base, Card.reset_base + 0x7F); wDeviceIndex++; continue; } if (DivasCardNew(&Card) != 0) { wDeviceIndex++; continue; } wNumCards++; } wDeviceIndex++; } wDeviceIndex = 0; while (wDeviceIndex < 10) { wPCIConsultation = pcibios_find_device(PCI_VENDOR_ID_EICON, PCI_DEVICE_ID_EICON_MAESTRAP, wDeviceIndex, &byBus, &byFunc); if (wPCIConsultation == PCIBIOS_SUCCESSFUL) { dword dwRAM, dwREG, dwCFG; byte byIRQ; printk(KERN_DEBUG "Divas: DIVA Server PRI Found\n"); pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_0, (unsigned int *) &dwRAM); dwRAM &= 0xFFFFF000; pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_2, (unsigned int *) &dwREG); dwREG &= 0xFFFFF000; pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_4, (unsigned int *) &dwCFG); dwCFG &= 0xFFFFF000; pcibios_read_config_byte(byBus, byFunc, PCI_INTERRUPT_LINE, &byIRQ); Card.memory[DIVAS_RAM_MEMORY] = ioremap(dwRAM, 0x10000); Card.memory[DIVAS_REG_MEMORY] = ioremap(dwREG, 0x4000); Card.memory[DIVAS_CFG_MEMORY] = ioremap(dwCFG, 0x1000); Card.memory[DIVAS_SHARED_MEMORY] = Card.memory[DIVAS_RAM_MEMORY] + DIVAS_SHARED_OFFSET; /* pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_1, (unsigned int *) &dwPLXIOBase); dwPLXIOBase &= 0xFFFFFFFc; pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_2, (unsigned int *) &dwDivasIOBase); dwDivasIOBase &= 0xFFFFFF80; pcibios_read_config_byte(byBus, byFunc, PCI_INTERRUPT_LINE, &byIRQ); */ Card.card_id = wNumCards; Card.card_type = DIA_CARD_TYPE_DIVA_SERVER; Card.bus_type = DIA_BUS_TYPE_PCI; Card.irq = byIRQ; /* Card.reset_base = dwPLXIOBase; Card.io_base = dwDivasIOBase;*/ Card.bus_num = byBus; Card.func_num = byFunc; Card.slot = -1; Card.name[0] = 'D'; Card.name[1] = 'I'; Card.name[2] = 'V'; Card.name[3] = 'A'; Card.name[4] = 'S'; Card.name[5] = 'P'; Card.name[6] = '\0'; if (DivasCardNew(&Card) != 0) { wDeviceIndex++; continue; } wNumCards++; } wDeviceIndex++; } printk(KERN_INFO "Divas: %d cards detected\n", wNumCards); if(wNumCards == 0) { return -1; } Divas_fops.ioctl = do_ioctl; Divas_fops.poll = do_poll; Divas_fops.read = do_read; Divas_fops.open = do_open; Divas_fops.release = do_release; Divas_major = register_chrdev(0, "Divas", &Divas_fops); if (Divas_major < 0) { printk(KERN_WARNING "Divas: Unable to register character driver\n"); return -1; } return 0; }
static int pci_etherdev_probe(struct device *dev, struct pci_id_info pci_tbl[]) { int cards_found = 0; int pci_index = 0; unsigned char pci_bus, pci_device_fn; if ( ! pcibios_present()) return -ENODEV; for (;pci_index < 0xff; pci_index++) { u16 vendor, device, pci_command, new_command; int chip_idx, irq; long pciaddr; long ioaddr; if (pcibios_find_class (PCI_CLASS_NETWORK_ETHERNET << 8, pci_index, &pci_bus, &pci_device_fn) != PCIBIOS_SUCCESSFUL) break; pcibios_read_config_word(pci_bus, pci_device_fn, PCI_VENDOR_ID, &vendor); pcibios_read_config_word(pci_bus, pci_device_fn, PCI_DEVICE_ID, &device); for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++) if (vendor == pci_tbl[chip_idx].vendor_id && (device & pci_tbl[chip_idx].device_id_mask) == pci_tbl[chip_idx].device_id) break; if (pci_tbl[chip_idx].vendor_id == 0) /* Compiled out! */ continue; { #if defined(PCI_SUPPORT_VER2) struct pci_dev *pdev = pci_find_slot(pci_bus, pci_device_fn); #ifdef VIA_USE_IO pciaddr = pdev->base_address[0]; #else pciaddr = pdev->base_address[1]; #endif irq = pdev->irq; #else u32 pci_memaddr; u8 pci_irq_line; pcibios_read_config_byte(pci_bus, pci_device_fn, PCI_INTERRUPT_LINE, &pci_irq_line); #ifdef VIA_USE_IO pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_0, &pci_memaddr); pciaddr = pci_memaddr; #else pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_1, &pci_memaddr); pciaddr = pci_memaddr; #endif irq = pci_irq_line; #endif } if (debug > 2) printk(KERN_INFO "Found %s at PCI address %#lx, IRQ %d.\n", pci_tbl[chip_idx].name, pciaddr, irq); if (pci_tbl[chip_idx].flags & PCI_USES_IO) { ioaddr = pciaddr & ~3; if (check_region(ioaddr, pci_tbl[chip_idx].io_size)) continue; } else if ((ioaddr = (long)ioremap(pciaddr & ~0xf, pci_tbl[chip_idx].io_size)) == 0) { printk(KERN_INFO "Failed to map PCI address %#lx.\n", pciaddr); continue; } pcibios_read_config_word(pci_bus, pci_device_fn, PCI_COMMAND, &pci_command); new_command = pci_command | (pci_tbl[chip_idx].flags & 7); if (pci_command != new_command) { printk(KERN_INFO " The PCI BIOS has not enabled the" " device at %d/%d! Updating PCI command %4.4x->%4.4x.\n", pci_bus, pci_device_fn, pci_command, new_command); pcibios_write_config_word(pci_bus, pci_device_fn, PCI_COMMAND, new_command); } dev = pci_tbl[chip_idx].probe1(pci_bus, pci_device_fn, dev, ioaddr, irq, chip_idx, cards_found); if (dev && (pci_tbl[chip_idx].flags & PCI_COMMAND_MASTER)) { u8 pci_latency; pcibios_read_config_byte(pci_bus, pci_device_fn, PCI_LATENCY_TIMER, &pci_latency); if (pci_latency < min_pci_latency) { printk(KERN_INFO " PCI latency timer (CFLT) is " "unreasonably low at %d. Setting to %d clocks.\n", pci_latency, min_pci_latency); pcibios_write_config_byte(pci_bus, pci_device_fn, PCI_LATENCY_TIMER, min_pci_latency); } } dev = 0; cards_found++; } return cards_found ? 0 : -ENODEV; }
int rtl8139_probe(struct device *dev) { int cards_found = 0; int pci_index = 0; unsigned char pci_bus, pci_device_fn; if ( ! pcibios_present()) return -ENODEV; for (; pci_index < 0xff; pci_index++) { u16 vendor, device, pci_command, new_command; int chip_idx, irq; long ioaddr; if (pcibios_find_class (PCI_CLASS_NETWORK_ETHERNET << 8, pci_index, &pci_bus, &pci_device_fn) != PCIBIOS_SUCCESSFUL) break; pcibios_read_config_word(pci_bus, pci_device_fn, PCI_VENDOR_ID, &vendor); pcibios_read_config_word(pci_bus, pci_device_fn, PCI_DEVICE_ID, &device); for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++) if (vendor == pci_tbl[chip_idx].vendor_id && (device & pci_tbl[chip_idx].device_id_mask) == pci_tbl[chip_idx].device_id) break; if (pci_tbl[chip_idx].vendor_id == 0) /* Compiled out! */ continue; { #if defined(PCI_SUPPORT_VER2) struct pci_dev *pdev = pci_find_slot(pci_bus, pci_device_fn); ioaddr = pdev->base_address[0] & ~3; irq = pdev->irq; #else u32 pci_ioaddr; u8 pci_irq_line; pcibios_read_config_byte(pci_bus, pci_device_fn, PCI_INTERRUPT_LINE, &pci_irq_line); pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_0, &pci_ioaddr); ioaddr = pci_ioaddr & ~3; irq = pci_irq_line; #endif } if ((pci_tbl[chip_idx].flags & PCI_USES_IO) && check_region(ioaddr, pci_tbl[chip_idx].io_size)) continue; /* Activate the card: fix for brain-damaged Win98 BIOSes. */ pcibios_read_config_word(pci_bus, pci_device_fn, PCI_COMMAND, &pci_command); new_command = pci_command | (pci_tbl[chip_idx].flags & 7); if (pci_command != new_command) { printk(KERN_INFO " The PCI BIOS has not enabled the" " device at %d/%d! Updating PCI command %4.4x->%4.4x.\n", pci_bus, pci_device_fn, pci_command, new_command); pcibios_write_config_word(pci_bus, pci_device_fn, PCI_COMMAND, new_command); } dev = pci_tbl[chip_idx].probe1(pci_bus, pci_device_fn, dev, ioaddr, irq, chip_idx, cards_found); if (dev && (pci_tbl[chip_idx].flags & PCI_COMMAND_MASTER)) { u8 pci_latency; pcibios_read_config_byte(pci_bus, pci_device_fn, PCI_LATENCY_TIMER, &pci_latency); if (pci_latency < 32) { printk(KERN_NOTICE " PCI latency timer (CFLT) is " "unreasonably low at %d. Setting to 64 clocks.\n", pci_latency); pcibios_write_config_byte(pci_bus, pci_device_fn, PCI_LATENCY_TIMER, 64); } } dev = 0; cards_found++; } return cards_found ? 0 : -ENODEV; }