static void dm_rx_hw_antena_div_init(struct odm_dm_struct *dm_odm)
{
struct adapter *adapter = dm_odm->Adapter;
u32 value32;
if (*(dm_odm->mp_mode) == 1) {
dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);
return;
}
/* MAC Setting */
value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
value32|(BIT23|BIT25));
/* Pin Settings */
phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);
/* OFDM Settings */
phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
0x000000a0);
/* CCK Settings */
phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1);
phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1);
rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);
}
static bool rf6052_conf_para(struct adapter *adapt)
{
struct hal_data_8188e *hal_data = adapt->HalData;
u32 u4val = 0;
bool rtstatus = true;
struct bb_reg_def *pphyreg;
pphyreg = &hal_data->PHYRegDef[RF90_PATH_A];
u4val = phy_query_bb_reg(adapt, pphyreg->rfintfs, BRFSI_RFENV);
phy_set_bb_reg(adapt, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
udelay(1);
phy_set_bb_reg(adapt, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
udelay(1);
phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREADDREAALENGTH, 0x0);
udelay(1);
phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREDATALENGTH, 0x0);
udelay(1);
rtstatus = rtl88e_phy_config_rf_with_headerfile(adapt);
phy_set_bb_reg(adapt, pphyreg->rfintfs, BRFSI_RFENV, u4val);
return rtstatus;
}
static void dm_trx_hw_antenna_div_init(struct odm_dm_struct *dm_odm)
{
struct adapter *adapter = dm_odm->Adapter;
u32 value32;
if (*(dm_odm->mp_mode) == 1) {
dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT5|BIT4|BIT3, 0);
return;
}
/* MAC Setting */
value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
value32|(BIT23|BIT25));
/* Pin Settings */
phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);
/* OFDM Settings */
phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
0x000000a0);
/* CCK Settings */
phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1);
phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1);
/* Tx Settings */
phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0);
rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
/* antenna mapping table */
if (!dm_odm->bIsMPChip) { /* testchip */
phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N,
BIT10|BIT9|BIT8, 1);
phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N,
BIT13|BIT12|BIT11, 2);
} else { /* MPchip */
phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord,
0x0201);
}
}
static void dm_fast_training_init(struct odm_dm_struct *dm_odm)
{
struct adapter *adapter = dm_odm->Adapter;
u32 value32, i;
struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
u32 AntCombination = 2;
if (*(dm_odm->mp_mode) == 1) {
return;
}
for (i = 0; i < 6; i++) {
dm_fat_tbl->Bssid[i] = 0;
dm_fat_tbl->antSumRSSI[i] = 0;
dm_fat_tbl->antRSSIcnt[i] = 0;
dm_fat_tbl->antAveRSSI[i] = 0;
}
dm_fat_tbl->TrainIdx = 0;
dm_fat_tbl->FAT_State = FAT_NORMAL_STATE;
/* MAC Setting */
value32 = phy_query_bb_reg(adapter, 0x4c, bMaskDWord);
phy_set_bb_reg(adapter, 0x4c, bMaskDWord, value32|(BIT23|BIT25));
value32 = phy_query_bb_reg(adapter, 0x7B4, bMaskDWord);
phy_set_bb_reg(adapter, 0x7b4, bMaskDWord, value32|(BIT16|BIT17));
/* Match MAC ADDR */
phy_set_bb_reg(adapter, 0x7b4, 0xFFFF, 0);
phy_set_bb_reg(adapter, 0x7b0, bMaskDWord, 0);
phy_set_bb_reg(adapter, 0x870, BIT9|BIT8, 0);
phy_set_bb_reg(adapter, 0x864, BIT10, 0);
phy_set_bb_reg(adapter, 0xb2c, BIT22, 0);
phy_set_bb_reg(adapter, 0xb2c, BIT31, 1);
phy_set_bb_reg(adapter, 0xca4, bMaskDWord, 0x000000a0);
/* antenna mapping table */
if (AntCombination == 2) {
if (!dm_odm->bIsMPChip) { /* testchip */
phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 1);
phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 2);
} else { /* MPchip */
phy_set_bb_reg(adapter, 0x914, bMaskByte0, 1);
phy_set_bb_reg(adapter, 0x914, bMaskByte1, 2);
}
} else if (AntCombination == 7) {
if (!dm_odm->bIsMPChip) { /* testchip */
phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 0);
phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 1);
phy_set_bb_reg(adapter, 0x878, BIT16, 0);
phy_set_bb_reg(adapter, 0x858, BIT15|BIT14, 2);
phy_set_bb_reg(adapter, 0x878, BIT19|BIT18|BIT17, 3);
phy_set_bb_reg(adapter, 0x878, BIT22|BIT21|BIT20, 4);
phy_set_bb_reg(adapter, 0x878, BIT25|BIT24|BIT23, 5);
phy_set_bb_reg(adapter, 0x878, BIT28|BIT27|BIT26, 6);
phy_set_bb_reg(adapter, 0x878, BIT31|BIT30|BIT29, 7);
} else { /* MPchip */
phy_set_bb_reg(adapter, 0x914, bMaskByte0, 0);
phy_set_bb_reg(adapter, 0x914, bMaskByte1, 1);
phy_set_bb_reg(adapter, 0x914, bMaskByte2, 2);
phy_set_bb_reg(adapter, 0x914, bMaskByte3, 3);
phy_set_bb_reg(adapter, 0x918, bMaskByte0, 4);
phy_set_bb_reg(adapter, 0x918, bMaskByte1, 5);
phy_set_bb_reg(adapter, 0x918, bMaskByte2, 6);
phy_set_bb_reg(adapter, 0x918, bMaskByte3, 7);
}
}
/* Default Ant Setting when no fast training */
phy_set_bb_reg(adapter, 0x80c, BIT21, 1);
phy_set_bb_reg(adapter, 0x864, BIT5|BIT4|BIT3, 0);
phy_set_bb_reg(adapter, 0x864, BIT8|BIT7|BIT6, 1);
/* Enter Traing state */
phy_set_bb_reg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1));
phy_set_bb_reg(adapter, 0xc50, BIT7, 1);
}
