static void pic32_eth_stop(struct udevice *dev)
{
struct pic32eth_dev *priv = dev_get_priv(dev);
struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
struct pic32_emac_regs *emac_p = priv->emac_regs;
/* Reset the phy if the controller is enabled */
if (readl(&ectl_p->con1.raw) & ETHCON_ON)
phy_reset(priv->phydev);
/* Shut down the PHY */
phy_shutdown(priv->phydev);
/* Stop rx/tx */
writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
mdelay(10);
/* reset MAC */
writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
/* clear reset */
writel(0, &emac_p->cfg1.raw);
mdelay(10);
/* disable controller */
writel(ETHCON_ON, &ectl_p->con1.clr);
mdelay(10);
/* wait until everything is down */
wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
2 * CONFIG_SYS_HZ, false);
/* clear any existing interrupt event */
writel(0xffffffff, &ectl_p->irq.clr);
}
static void ethoc_stop_common(struct ethoc *priv)
{
ethoc_disable_rx_and_tx(priv);
#ifdef CONFIG_PHYLIB
phy_shutdown(priv->phydev);
#endif
}
static void ldpaa_eth_stop(struct eth_device *net_dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
int err = 0;
if ((net_dev->state == ETH_STATE_PASSIVE) ||
(net_dev->state == ETH_STATE_INIT))
return;
#ifdef DEBUG
ldpaa_eth_get_dpni_counter();
#endif
err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dprc_handle, &dpmac_endpoint);
if (err < 0)
printf("dprc_disconnect() failed dpmac_endpoint\n");
err = dpmac_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle);
if (err < 0)
printf("dpmac_destroy() failed\n");
/* Stop Tx and Rx traffic */
err = dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
if (err < 0)
printf("dpni_disable() failed\n");
#ifdef CONFIG_PHYLIB
phy_shutdown(priv->phydev);
#endif
ldpaa_dpbp_free();
dpni_reset(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
}
static void pch_gbe_stop(struct udevice *dev)
{
struct pch_gbe_priv *priv = dev_get_priv(dev);
pch_gbe_reset(dev);
phy_shutdown(priv->phydev);
}
static void pch_gbe_halt(struct eth_device *dev)
{
struct pch_gbe_priv *priv = dev->priv;
pch_gbe_reset(dev);
phy_shutdown(priv->phydev);
}
static void _dw_eth_halt(struct dw_eth_dev *priv)
{
struct eth_mac_regs *mac_p = priv->mac_regs_p;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
phy_shutdown(priv->phydev);
}
/*
* disable transmitter, receiver
*/
static void ftgmac100_stop(struct udevice *dev)
{
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
debug("%s()\n", __func__);
writel(0, &ftgmac100->maccr);
phy_shutdown(priv->phydev);
}
static void ks2_eth_stop(struct udevice *dev)
{
struct ks2_eth_priv *priv = dev_get_priv(dev);
if (!priv->emac_open)
return;
ethss_stop();
ksnav_close(priv->netcp_pktdma);
qm_close();
phy_shutdown(priv->phydev);
priv->emac_open = false;
}
static int pic32_eth_remove(struct udevice *dev)
{
struct pic32eth_dev *priv = dev_get_priv(dev);
struct mii_dev *bus;
dm_gpio_free(dev, &priv->rst_gpio);
phy_shutdown(priv->phydev);
free(priv->phydev);
bus = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
mdio_unregister(bus);
mdio_free(bus);
iounmap(priv->ectl_regs);
return 0;
}
/* halt device */
static void ll_temac_halt(struct eth_device *dev)
{
struct ll_temac *ll_temac = dev->priv;
struct temac_reg *regs = (struct temac_reg *)dev->iobase;
/* Disable Receiver */
ll_temac_indirect_set(regs, TEMAC_RCW0, 0);
/* Disable Transmitter */
ll_temac_indirect_set(regs, TEMAC_TC, 0);
if (ll_temac->ctrlhalt)
ll_temac->ctrlhalt(dev);
/* Shut down the PHY, as needed */
phy_shutdown(ll_temac->phydev);
}
/* Stop the interface */
static void tsec_halt(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
tsec_t *regs = priv->regs;
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
!= (IEVENT_GRSC | IEVENT_GTSC))
;
clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
/* Shut down the PHY, as needed */
phy_shutdown(priv->phydev);
}
static void fm_eth_halt(struct eth_device *dev)
{
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
fm_eth = (struct fm_eth *)dev->priv;
mac = fm_eth->mac;
/* graceful stop the transmission of frames */
fmc_tx_port_graceful_stop_enable(fm_eth);
/* disable bmi Tx port */
bmi_tx_port_disable(fm_eth->tx_port);
/* disable MAC rx/tx port */
mac->disable_mac(mac);
/* disable bmi Rx port */
bmi_rx_port_disable(fm_eth->rx_port);
phy_shutdown(fm_eth->phydev);
}
/* Eth device close */
void keystone2_eth_close(struct eth_device *dev)
{
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
struct phy_device *phy_dev = eth_priv->phy_dev;
debug("+ emac_close\n");
if (!emac_open)
return;
ethss_stop();
ksnav_close(&netcp_pktdma);
qm_close();
phy_shutdown(phy_dev);
emac_open = 0;
debug("- emac_close\n");
}
static void ldpaa_eth_stop(struct eth_device *net_dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
int err = 0;
if ((net_dev->state == ETH_STATE_PASSIVE) ||
(net_dev->state == ETH_STATE_INIT))
return;
/* Stop Tx and Rx traffic */
err = dpni_disable(dflt_mc_io, priv->dpni_handle);
if (err < 0)
printf("dpni_disable() failed\n");
#ifdef CONFIG_PHYLIB
phy_shutdown(priv->phydev);
#endif
ldpaa_dpbp_free();
dpni_reset(dflt_mc_io, priv->dpni_handle);
dpni_close(dflt_mc_io, priv->dpni_handle);
}
/* blocking notifier support */
void cpcap_musb_notifier_call(unsigned long event)
{
struct musb *musb = g_musb;
struct device *dev = musb->controller;
struct musb_hdrc_platform_data *pdata = dev->platform_data;
struct omap_musb_board_data *data = pdata->board_data;
static int hostmode;
u32 val;
u8 power;
switch (event) {
case USB_EVENT_ID:
DBG(1, "ID GND\n");
/* configure musb into smartidle with wakeup enabled
* smart standby mode.
*/
omap_pm_set_max_mpu_wakeup_lat(&pdata->musb_qos_request, 4000);
musb_writel(musb->mregs, OTG_FORCESTDBY, 0);
val = musb_readl(musb->mregs, OTG_SYSCONFIG);
if (cpu_is_omap44xx())
val |= SMARTIDLEWKUP | SMARTSTDBY | ENABLEWAKEUP;
else
val |= SMARTIDLE | SMARTSTDBY | ENABLEWAKEUP;
musb_writel(musb->mregs, OTG_SYSCONFIG, val);
if (data->interface_type == MUSB_INTERFACE_UTMI) {
phy_init();
otg_init(musb->xceiv);
/* enable VBUS valid, id groung*/
__raw_writel(AVALID | VBUSVALID, ctrl_base +
USBOTGHS_CONTROL);
val = __raw_readl(phymux_base +
USBA0_OTG_CE_PAD1_USBA0_OTG_DP);
val |= DP_WAKEUPENABLE;
__raw_writel(val, phymux_base +
USBA0_OTG_CE_PAD1_USBA0_OTG_DP);
}
hostmode = 1;
musb_start(musb);
musb_set_vbus(musb, 1);
break;
case USB_EVENT_VBUS:
DBG(1, "VBUS Connect\n");
/* configure musb into smartidle with wakeup enabled
* smart standby mode.
*/
musb_writel(musb->mregs, OTG_FORCESTDBY, 0);
val = musb_readl(musb->mregs, OTG_SYSCONFIG);
if (cpu_is_omap44xx())
val |= SMARTIDLEWKUP | SMARTSTDBY | ENABLEWAKEUP;
else
val |= SMARTIDLE | SMARTSTDBY | ENABLEWAKEUP;
musb_writel(musb->mregs, OTG_SYSCONFIG, val);
power = musb_readb(musb->mregs, MUSB_POWER);
power &= ~MUSB_POWER_SOFTCONN;
musb_writeb(musb->mregs, MUSB_POWER, power);
if (data->interface_type == MUSB_INTERFACE_UTMI) {
phy_init();
otg_init(musb->xceiv);
if (!hostmode) {
/* Enable VBUS Valid, AValid. Clear SESSEND.*/
__raw_writel(IDDIG | AVALID | VBUSVALID,
ctrl_base + USBOTGHS_CONTROL);
}
}
break;
case USB_EVENT_NONE:
DBG(1, "VBUS Disconnect\n");
if (data->interface_type == MUSB_INTERFACE_UTMI) {
/* enable this clock because in suspend interrupt
* handler phy clocks are disabled. If phy clocks are
* not enabled then DISCONNECT interrupt will not be
* reached to mentor
*/
otg_set_clk(musb->xceiv, 1);
__raw_writel(SESSEND | IDDIG, ctrl_base +
USBOTGHS_CONTROL);
if (musb->xceiv->set_vbus)
otg_set_vbus(musb->xceiv, 0);
otg_shutdown(musb->xceiv);
phy_shutdown();
}
/* configure in force idle/ standby */
musb_writel(musb->mregs, OTG_FORCESTDBY, 1);
val = musb_readl(musb->mregs, OTG_SYSCONFIG);
val &= ~(SMARTIDLEWKUP | SMARTSTDBY | ENABLEWAKEUP);
val |= FORCEIDLE | FORCESTDBY;
musb_writel(musb->mregs, OTG_SYSCONFIG, val);
omap_pm_set_max_mpu_wakeup_lat(&pdata->musb_qos_request, -1);
if (data->interface_type == MUSB_INTERFACE_UTMI) {
val = __raw_readl(phymux_base +
USBA0_OTG_CE_PAD1_USBA0_OTG_DP);
val &= ~DP_WAKEUPENABLE;
__raw_writel(val, phymux_base +
USBA0_OTG_CE_PAD1_USBA0_OTG_DP);
}
if (hostmode) {
musb_stop(musb);
musb_set_vbus(musb, 0);
}
hostmode = 0;
break;
default:
DBG(1, "ID float\n");
}
}
