static void apollo_pic_set_irq_line(device_t *device, int irq, int state) {
// don't log PTM interrupts
if (irq != APOLLO_IRQ_PTM) {
DLOG1(("apollo_pic_set_irq_line: irq=%d state=%d", irq, state));
}
switch (irq) {
case 0: pic8259_ir0_w(get_pic8259_master(device), state); break;
case 1: pic8259_ir1_w(get_pic8259_master(device), state); break;
case 2: pic8259_ir2_w(get_pic8259_master(device), state); break;
case 3: pic8259_ir3_w(get_pic8259_master(device), state); break;
case 4: pic8259_ir4_w(get_pic8259_master(device), state); break;
case 5: pic8259_ir5_w(get_pic8259_master(device), state); break;
case 6: pic8259_ir6_w(get_pic8259_master(device), state); break;
case 7: pic8259_ir7_w(get_pic8259_master(device), state); break;
case 8: pic8259_ir0_w(get_pic8259_slave(device), state); break;
case 9: pic8259_ir1_w(get_pic8259_slave(device), state); break;
case 10: pic8259_ir2_w(get_pic8259_slave(device), state); break;
case 11: pic8259_ir3_w(get_pic8259_slave(device), state); break;
case 12: pic8259_ir4_w(get_pic8259_slave(device), state); break;
case 13: pic8259_ir5_w(get_pic8259_slave(device), state); break;
case 14: pic8259_ir6_w(get_pic8259_slave(device), state); break;
case 15: pic8259_ir7_w(get_pic8259_slave(device), state); break;
}
}
void pc1512_state::update_ack()
{
if (m_ack_int_enable)
pic8259_ir7_w(m_pic, m_ack);
else
pic8259_ir7_w(m_pic, CLEAR_LINE);
}
UINT8 s100_wunderbus_device::s100_sinp_r(offs_t offset)
{
UINT8 address = (input_port_read(this, "7C") & 0x3e) << 2;
if ((offset & 0xf8) != address) return 0;
UINT8 data = 0;
if ((offset & 0x07) < 7)
{
switch (m_group)
{
case 0:
switch (offset & 0x07)
{
case 0: // DAISY 0 IN (STATUS)
/*
bit description
0 End of Ribbon
1 Paper Out
2 Cover Open
3 Paper Feed Ready
4 Carriage Ready
5 Print Wheel Ready
6 Check
7 Printer Ready
*/
break;
case 1: // Switch/Parallel port flags
/*
bit description
0 FLAG1
1 FLAG2
2 10A S6
3 10A S5
4 10A S4
5 10A S3
6 10A S2
7 10A S1
*/
data = BITSWAP8(input_port_read(this, "10A"),0,1,2,3,4,5,6,7) & 0xfc;
break;
case 2: // R.T. Clock IN/RESET CLK. Int.
/*
bit description
0 1990 Data Out
1 1990 TP
2
3
4
5
6
7
*/
data |= m_rtc->data_out_r();
data |= m_rtc->tp_r() << 1;
// reset clock interrupt
m_rtc_tp = 0;
pic8259_ir7_w(m_pic, m_rtc_tp);
break;
case 3: // Parallel data IN
break;
case 4: // 8259 0 register
case 5: // 8259 1 register
data = pic8259_r(m_pic, offset & 0x01);
break;
case 6: // not used
break;
}
break;
case 1:
data = ins8250_r(m_ace1, offset & 0x07);
break;
case 2:
data = ins8250_r(m_ace2, offset & 0x07);
break;
case 3:
data = ins8250_r(m_ace3, offset & 0x07);
break;
}
}
return data;
}
