void port_in(bit16u port, bit8u *data)
{
switch (port)
{
case 0x000: dma_read_offset(0, data); break;
case 0x001: dma_read_wordcount(0, data); break;
case 0x002: dma_read_offset(1, data); break;
case 0x003: dma_read_wordcount(1, data); break;
case 0x004: dma_read_offset(2, data); break;
case 0x005: dma_read_wordcount(2, data); break;
case 0x006: dma_read_offset(3, data); break;
case 0x007: dma_read_wordcount(3, data); break;
case 0x008: dma_read_status_reg(data); break;
case 0x040: pit_read_latch(0, data); break;
case 0x041: pit_read_latch(1, data); break;
case 0x042: pit_read_latch(2, data); break;
case 0x020: pic_read(port, data); break;
case 0x021: pic_read(port, data); break;
case 0x060: ppi_read_port_a(data); break;
case 0x062: ppi_read_port_c(data); break;
case 0x3BA: mda_read_status(data); break;
default:
EMU_DEBUG("tried to read from unmapped port %03x", port);
*data = 0;
break;
}
}
void
pic_load(pic_state *pic, struct pic_port *port)
{
pic_value form;
size_t ai = pic_gc_arena_preserve(pic);
while (! pic_eof_p(form = pic_read(pic, port))) {
pic_eval(pic, form, pic->lib->env);
pic_gc_arena_restore(pic, ai);
}
}
int sysmon_init_f (void)
{
sysmon_t ** l;
ulong reg;
/* Power on CCFL, PCMCIA */
reg = pic_read (0x60);
reg |= 0x09;
pic_write (0x60, reg);
for (l = sysmon_list; *l; l++) {
(*l)->init(*l);
}
return 0;
}
static int scc_init (void)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
volatile cpm8xx_t *cp = &(im->im_cpm);
uint dpaddr;
#if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
#endif
/* initialize pointers to SCC */
sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
#if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
{ /* Disable Ethernet, enable Serial */
uchar c;
c = pic_read (0x61);
c &= ~0x40; /* enable COM3 */
c |= 0x80; /* disable Ethernet */
pic_write (0x61, c);
/* enable RTS2 */
cp->cp_pbpar |= 0x2000;
cp->cp_pbdat |= 0x2000;
cp->cp_pbdir |= 0x2000;
}
#endif /* CONFIG_LWMON */
/* Disable transmitter/receiver.
*/
sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
#if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
/*
* The MPC850 has SCC3 on Port B
*/
cp->cp_pbpar |= 0x06;
cp->cp_pbdir &= ~0x06;
cp->cp_pbodr &= ~0x06;
#elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
/*
* Standard configuration for SCC's is on Part A
*/
ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
#else
/*
* The IP860 has SCC3 and SCC4 on Port D
*/
ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
#endif
/* Allocate space for two buffer descriptors in the DP ram.
*/
#ifdef CFG_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
#else
dpaddr = CPM_SERIAL2_BASE ;
#endif
/* Enable SDMA.
*/
im->im_siu_conf.sc_sdcr = 0x0001;
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
rbdf->cbd_bufaddr = (uint) (rbdf+2);
rbdf->cbd_sc = 0;
tbdf = rbdf + 1;
tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
tbdf->cbd_sc = 0;
/* Set up the baud rate generator.
*/
scc_setbrg ();
/* Set up the uart parameters in the parameter ram.
*/
up->scc_genscc.scc_rbase = dpaddr;
up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
/* Initialize Tx/Rx parameters.
*/
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
up->scc_genscc.scc_mrblr = 1; /* Single character receive */
up->scc_maxidl = 0; /* disable max idle */
up->scc_brkcr = 1; /* send one break character on stop TX */
up->scc_parec = 0;
up->scc_frmec = 0;
up->scc_nosec = 0;
up->scc_brkec = 0;
up->scc_uaddr1 = 0;
up->scc_uaddr2 = 0;
up->scc_toseq = 0;
up->scc_char1 = 0x8000;
up->scc_char2 = 0x8000;
up->scc_char3 = 0x8000;
up->scc_char4 = 0x8000;
up->scc_char5 = 0x8000;
up->scc_char6 = 0x8000;
up->scc_char7 = 0x8000;
up->scc_char8 = 0x8000;
up->scc_rccm = 0xc0ff;
/* Set low latency / small fifo.
*/
sp->scc_gsmrh = SCC_GSMRH_RFW;
/* Set SCC(x) clock mode to 16x
* See 8xx_io/commproc.c for details.
*
* Wire BRG1 to SCCn
*/
/* Set UART mode, clock divider 16 on Tx and Rx
*/
sp->scc_gsmrl &= ~0xF;
sp->scc_gsmrl |=
(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
sp->scc_psmr = 0;
sp->scc_psmr |= SCU_PSMR_CL;
/* Mask all interrupts and remove anything pending.
*/
sp->scc_sccm = 0;
sp->scc_scce = 0xffff;
sp->scc_dsr = 0x7e7e;
sp->scc_psmr = 0x3000;
/* Make the first buffer the only buffer.
*/
tbdf->cbd_sc |= BD_SC_WRAP;
rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
/* Enable transmitter/receiver.
*/
sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
return (0);
}
