static int
mtk_pic_attach(device_t dev)
{
struct mtk_pic_softc *sc;
intptr_t xref = pic_xref(dev);
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, mtk_pic_spec, sc->pic_res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->pic_dev = dev;
/* Initialize mutex */
mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
/* Set the number of interrupts */
sc->nirqs = nitems(sc->pic_irqs);
/* Mask all interrupts */
WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF);
/* But enable interrupt generation/masking */
WRITE4(sc, MTK_INTENA, 0x00000000);
/* Set all interrupts to type 0 */
WRITE4(sc, MTK_INTTYPE, 0xFFFFFFFF);
/* Register the interrupts */
if (mtk_pic_register_isrcs(sc) != 0) {
device_printf(dev, "could not register PIC ISRCs\n");
goto cleanup;
}
/*
* Now, when everything is initialized, it's right time to
* register interrupt controller to interrupt framefork.
*/
if (intr_pic_register(dev, xref) == NULL) {
device_printf(dev, "could not register PIC\n");
goto cleanup;
}
if (bus_setup_intr(dev, sc->pic_res[1], INTR_TYPE_CLK,
mtk_pic_intr, NULL, sc, &sc->pic_intrhand)) {
device_printf(dev, "could not setup irq handler\n");
intr_pic_deregister(dev, xref);
goto cleanup;
}
return (0);
cleanup:
bus_release_resources(dev, mtk_pic_spec, sc->pic_res);
return(ENXIO);
}
static int
mips_pic_attach(device_t dev)
{
struct mips_pic_softc *sc;
intptr_t xref = pic_xref(dev);
if (pic_sc)
return (ENXIO);
sc = device_get_softc(dev);
sc->pic_dev = dev;
pic_sc = sc;
/* Initialize mutex */
mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
/* Set the number of interrupts */
sc->nirqs = nitems(sc->pic_irqs);
/*
* Now, when everything is initialized, it's right time to
* register interrupt controller to interrupt framefork.
*/
if (intr_pic_register(dev, xref) != 0) {
device_printf(dev, "could not register PIC\n");
goto cleanup;
}
/* Claim our root controller role */
if (intr_pic_claim_root(dev, xref, mips_pic_intr, sc, 0) != 0) {
device_printf(dev, "could not set PIC as a root\n");
intr_pic_unregister(dev, xref);
goto cleanup;
}
return (0);
cleanup:
return(ENXIO);
}
static int
apb_attach(device_t dev)
{
struct apb_softc *sc = device_get_softc(dev);
#ifdef INTRNG
intptr_t xref = pic_xref(dev);
int miscirq;
#else
int rid = 0;
#endif
sc->apb_dev = dev;
sc->apb_mem_rman.rm_type = RMAN_ARRAY;
sc->apb_mem_rman.rm_descr = "APB memory window";
if(ar531x_soc >= AR531X_SOC_AR5315) {
if (rman_init(&sc->apb_mem_rman) != 0 ||
rman_manage_region(&sc->apb_mem_rman,
AR5315_APB_BASE,
AR5315_APB_BASE + AR5315_APB_SIZE - 1) != 0)
panic("apb_attach: failed to set up memory rman");
} else {
if (rman_init(&sc->apb_mem_rman) != 0 ||
rman_manage_region(&sc->apb_mem_rman,
AR5312_APB_BASE,
AR5312_APB_BASE + AR5312_APB_SIZE - 1) != 0)
panic("apb_attach: failed to set up memory rman");
}
sc->apb_irq_rman.rm_type = RMAN_ARRAY;
sc->apb_irq_rman.rm_descr = "APB IRQ";
if (rman_init(&sc->apb_irq_rman) != 0 ||
rman_manage_region(&sc->apb_irq_rman,
APB_IRQ_BASE, APB_IRQ_END) != 0)
panic("apb_attach: failed to set up IRQ rman");
#ifndef INTRNG
if ((sc->sc_misc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE)) == NULL) {
device_printf(dev, "unable to allocate IRQ resource\n");
return (ENXIO);
}
if ((bus_setup_intr(dev, sc->sc_misc_irq, INTR_TYPE_MISC,
apb_filter, NULL, sc, &sc->sc_misc_ih))) {
device_printf(dev,
"WARNING: unable to register interrupt handler\n");
return (ENXIO);
}
#else
/* Register the interrupts */
if (apb_pic_register_isrcs(sc) != 0) {
device_printf(dev, "could not register PIC ISRCs\n");
return (ENXIO);
}
/*
* Now, when everything is initialized, it's right time to
* register interrupt controller to interrupt framefork.
*/
if (intr_pic_register(dev, xref) == NULL) {
device_printf(dev, "could not register PIC\n");
return (ENXIO);
}
if(ar531x_soc >= AR531X_SOC_AR5315) {
miscirq = AR5315_CPU_IRQ_MISC;
} else {
miscirq = AR5312_IRQ_MISC;
}
cpu_establish_hardintr("aric", apb_filter, NULL, sc, miscirq,
INTR_TYPE_MISC, NULL);
#endif
/* mask all misc interrupt */
if(ar531x_soc >= AR531X_SOC_AR5315) {
ATH_WRITE_REG(AR5315_SYSREG_BASE
+ AR5315_SYSREG_MISC_INTMASK, 0);
} else {
ATH_WRITE_REG(AR5312_SYSREG_BASE
+ AR5312_SYSREG_MISC_INTMASK, 0);
}
bus_generic_probe(dev);
bus_enumerate_hinted_children(dev);
bus_generic_attach(dev);
return (0);
}
