static int axp_pmx_get_function_groups(struct pinctrl_dev *pctldev, unsigned function, const char * const **groups, unsigned * const num_groups) { struct axp_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); *groups = pctl->functions[function].groups; *num_groups = pctl->functions[function].ngroups; return 0; }
static int axp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *num_pins) { struct axp_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); *pins = (unsigned *)&pctl->groups[selector].pin; *num_pins = 1; return 0; }
static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev, unsigned int func, const char * const **groups, unsigned int * const num_groups) { struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); *groups = pctl->functions[func].groups; *num_groups = pctl->functions[func].ngroups; return 0; }
static int cygnus_get_function_groups(struct pinctrl_dev *pctrl_dev, unsigned selector, const char * const **groups, unsigned * const num_groups) { struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); *groups = pinctrl->functions[selector].groups; *num_groups = pinctrl->functions[selector].num_groups; return 0; }
static int ns_pinctrl_get_group_pins(struct pinctrl_dev *pctrl_dev, unsigned int selector, const unsigned int **pins, unsigned int *num_pins) { struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); *pins = ns_pinctrl->groups[selector].pins; *num_pins = ns_pinctrl->groups[selector].num_pins; return 0; }
static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned selector, const char * const **groups, unsigned * const num_groups) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); *groups = pmx->pfc->info->functions[selector].groups; *num_groups = pmx->pfc->info->functions[selector].nr_groups; return 0; }
static int lpc18xx_pmx_get_func_groups(struct pinctrl_dev *pctldev, unsigned function, const char *const **groups, unsigned *const num_groups) { struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev); *groups = scu->func[function].groups; *num_groups = scu->func[function].ngroups; return 0; }
static int wmt_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *num_pins) { struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); *pins = &data->pins[selector].number; *num_pins = 1; return 0; }
static int oxnas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, const unsigned int **pins, unsigned int *num_pins) { struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); *pins = &pctl->groups[group].pin; *num_pins = 1; return 0; }
static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *num_pins) { struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); *pins = pctrl->groups[selector].pins; *num_pins = pctrl->groups[selector].npins; return 0; }
static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, const unsigned **pins, unsigned *num_pins) { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); *pins = pmx->soc->groups[group].pins; *num_pins = pmx->soc->groups[group].npins; return 0; }
static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, const char * const **groups, unsigned * const num_groups) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; *groups = info->functions[selector].groups; *num_groups = info->functions[selector].num_groups; return 0; }
static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, unsigned group, const char * const **groups, unsigned * const num_groups) { struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); *groups = d->soc->functions[group].groups; *num_groups = d->soc->functions[group].ngroups; return 0; }
static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, unsigned function, const char * const **groups, unsigned * const num_groups) { struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); *groups = npct->soc->functions[function].groups; *num_groups = npct->soc->functions[function].ngroups; return 0; }
static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev, unsigned selector, const unsigned **pins, unsigned *num_pins) { struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); if (selector >= info->num_grps) return -EINVAL; *pins = info->grps[selector].pins; *num_pins = info->grps[selector].npins; return 0; }
static int wmt_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, bool input) { struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); wmt_set_pinmux(data, (input ? WMT_FSEL_GPIO_IN : WMT_FSEL_GPIO_OUT), offset); return 0; }
static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx1_pinctrl_soc_info *info = ipctl->info; const struct imx1_pin *pins; unsigned int npins; int i; /* * Configure the mux mode for each pin in the group for a specific * function. */ pins = info->groups[group].pins; npins = info->groups[group].npins; WARN_ON(!pins || !npins); dev_dbg(ipctl->dev, "enable function %s group %s\n", info->functions[selector].name, info->groups[group].name); for (i = 0; i < npins; i++) { unsigned int mux = pins[i].mux_id; unsigned int pin_id = pins[i].pin_id; unsigned int afunction = MX1_MUX_FUNCTION(mux); unsigned int gpio_in_use = MX1_MUX_GPIO(mux); unsigned int direction = MX1_MUX_DIR(mux); unsigned int gpio_oconf = MX1_MUX_OCONF(mux); unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux); unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux); dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n", __func__, pin_id, afunction, gpio_in_use, direction, gpio_oconf, gpio_iconfa, gpio_iconfb); imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS); imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR); if (gpio_in_use) { imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR); imx1_write_2bit(ipctl, pin_id, gpio_iconfa, MX1_ICONFA); imx1_write_2bit(ipctl, pin_id, gpio_iconfb, MX1_ICONFB); } else { imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR); } } return 0; }
static int wmt_pmx_get_function_groups(struct pinctrl_dev *pctldev, unsigned selector, const char * const **groups, unsigned * const num_groups) { struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); /* every pin does every function */ *groups = data->groups; *num_groups = data->ngroups; return 0; }
static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned offset) { struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d", imx1_read_bit(ipctl, offset, MX1_GIUS), imx1_read_bit(ipctl, offset, MX1_GPR), imx1_read_bit(ipctl, offset, MX1_DDIR), imx1_read_2bit(ipctl, offset, MX1_OCR), imx1_read_2bit(ipctl, offset, MX1_ICONFA), imx1_read_2bit(ipctl, offset, MX1_ICONFB)); }
static int sprd_pmx_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, const char * const **groups, unsigned int * const num_groups) { struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct sprd_pinctrl_soc_info *info = pctl->info; *groups = info->grp_names; *num_groups = info->ngroups; return 0; }
static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg; const unsigned *pins, *mux; unsigned int npins, pin_id; int i; /* * Configure the mux mode for each pin in the group for a specific * function. */ pins = info->groups[group].pins; npins = info->groups[group].npins; mux = info->groups[group].mux_mode; WARN_ON(!pins || !npins || !mux); dev_dbg(ipctl->dev, "enable function %s group %s\n", info->functions[selector].name, info->groups[group].name); for (i = 0; i < npins; i++) { pin_id = pins[i]; pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]); if (!pin_reg) return -EINVAL; if (!pin_reg->mux_reg) { dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", info->pins[pin_id].name); return -EINVAL; } writel(mux[i], ipctl->base + pin_reg->mux_reg); dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", pin_reg->mux_reg, mux[i]); /* some pins also need select input setting, set it if found */ if (pin_reg->input_reg) { writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg); dev_dbg(ipctl->dev, "==>select_input: offset 0x%x val 0x%x\n", pin_reg->input_reg, pin_reg->input_val); } } return 0; }
static const char *hi6402_get_group_name(struct pinctrl_dev *pctldev, unsigned selector) { struct hi6402_pinctrl_device *pindev; pindev = pinctrl_dev_get_drvdata(pctldev); if (!(&pindev->pin_groups[selector])) { dev_err(pindev->dev, "%s could not find pingroup%i\n", __func__, selector); return NULL; } return pindev->pin_groups[selector].name; }
/* --------- pinconf related code --------- */ static int xway_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) { struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config); int port = PORT(pin); u32 reg; switch (param) { case LTQ_PINCONF_PARAM_OPEN_DRAIN: if (port == PORT3) reg = GPIO3_OD; else reg = GPIO_OD(pin); *config = LTQ_PINCONF_PACK(param, !gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); break; case LTQ_PINCONF_PARAM_PULL: if (port == PORT3) reg = GPIO3_PUDEN; else reg = GPIO_PUDEN(pin); if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) { *config = LTQ_PINCONF_PACK(param, 0); break; } if (port == PORT3) reg = GPIO3_PUDSEL; else reg = GPIO_PUDSEL(pin); if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) *config = LTQ_PINCONF_PACK(param, 2); else *config = LTQ_PINCONF_PACK(param, 1); break; case LTQ_PINCONF_PARAM_OUTPUT: reg = GPIO_DIR(pin); *config = LTQ_PINCONF_PACK(param, gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); break; default: dev_err(pctldev->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; } return 0; }
static void nmk_pmx_disable(struct pinctrl_dev *pctldev, unsigned function, unsigned group) { struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); const struct nmk_pingroup *g; g = &npct->soc->groups[group]; if (g->altsetting < 0) return; /* Poke out the mux, set the pin to some default state? */ dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); }
static int amlogic_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) { struct pin_desc *desc; struct amlogic_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); desc = pin_desc_get(pctldev, offset); if (desc->mux_owner) { pr_info("%s is using the pin %s as pinmux\n", desc->mux_owner, desc->name); return -EINVAL; } return pmx->soc->meson_clear_pinmux(pmx, offset); }
static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; int idx = sh_pfc_get_pin_index(pfc, offset); struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; unsigned long flags; spin_lock_irqsave(&pfc->lock, flags); cfg->type = PINMUX_TYPE_NONE; spin_unlock_irqrestore(&pfc->lock, flags); }
static int oxnas_pinmux_enable(struct pinctrl_dev *pctldev, unsigned int func, unsigned int group) { struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); const struct oxnas_pin_group *pg = &pctl->groups[group]; const struct oxnas_function *pf = &pctl->functions[func]; const char *fname = pf->name; struct oxnas_desc_function *functions = pg->functions; u32 mask = BIT(pg->pin); while (functions->name) { if (!strcmp(functions->name, fname)) { dev_dbg(pctl->dev, "setting function %s bank %d pin %d fct %d mask %x\n", fname, pg->bank, pg->pin, functions->fct, mask); regmap_write_bits(pctl->regmap, (pg->bank ? PINMUX_PRIMARY_SEL1 : PINMUX_PRIMARY_SEL0), mask, (functions->fct == 1 ? mask : 0)); regmap_write_bits(pctl->regmap, (pg->bank ? PINMUX_SECONDARY_SEL1 : PINMUX_SECONDARY_SEL0), mask, (functions->fct == 2 ? mask : 0)); regmap_write_bits(pctl->regmap, (pg->bank ? PINMUX_TERTIARY_SEL1 : PINMUX_TERTIARY_SEL0), mask, (functions->fct == 3 ? mask : 0)); return 0; } functions++; } dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func); return -EINVAL; }
static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *npins) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; if (selector >= info->ngroups) return -EINVAL; *pins = info->groups[selector].pins; *npins = info->groups[selector].npins; return 0; }
static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id, unsigned long *config) { struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id); unsigned int param = pinconf_to_config_param(*config); unsigned int reg, arg; if (!pin) return -EINVAL; if (pin->type == GLOBAL_CTRL_PIN) { reg = (readl((void __iomem *)pin->reg) >> pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width); } else {
static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, unsigned group) { int i, ret; struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct zynq_pctrl_group *pgrp = &pctrl->groups[group]; const struct zynq_pinmux_function *func = &pctrl->funcs[function]; /* * SD WP & CD are special. They have dedicated registers * to mux them in */ if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp || function == ZYNQ_PMUX_sdio1_cd || function == ZYNQ_PMUX_sdio1_wp) { u32 reg; ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + func->mux, ®); if (ret) return ret; reg &= ~func->mux_mask; reg |= pgrp->pins[0] << func->mux_shift; ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + func->mux, reg); if (ret) return ret; } else { for (i = 0; i < pgrp->npins; i++) { unsigned int pin = pgrp->pins[i]; u32 reg, addr = pctrl->pctrl_offset + (4 * pin); ret = regmap_read(pctrl->syscon, addr, ®); if (ret) return ret; reg &= ~ZYNQ_PINMUX_MUX_MASK; reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT; ret = regmap_write(pctrl->syscon, addr, reg); if (ret) return ret; } } return 0; }