void platform_pre_init(void) { u32 i2c_ret, pmic_ret; u32 pwrap_ret=0,i=0; int pll_ret; /* 2012/11/27 * Sten * Add MT6589 MCI downsizer workaround start*/ *(volatile unsigned int*)(0x10001200) |= (0x1); /* Add MT6589 MCI downsizer workaround end*/ /* init timer */ mtk_timer_init(); /* init boot time */ g_boot_time = get_timer(0); #if 0 /* FIXME */ /* * NoteXXX: CPU 1 may not be reset clearly after power-ON. * Need to apply a S/W workaround to manualy reset it first. */ { U32 val; val = DRV_Reg32(0xC0009010); DRV_WriteReg32(0xC0009010, val | 0x2); gpt_busy_wait_us(10); DRV_WriteReg32(0xC0009010, val & ~0x2); gpt_busy_wait_us(10); } #ifndef SLT_BOOTLOADER /* power off cpu1 for power saving */ power_off_cpu1(); #endif #endif /* init pll */ pll_ret = mt_pll_init(); /*GPIO init*/ mt_gpio_init(); /* init uart baudrate when pll on */ mtk_uart_init(UART_SRC_CLK_FRQ, CFG_LOG_BAUDRATE); if (pll_ret != 0) print("MEMPLL 3PLL mode calibration fail\n"); /* init pmic i2c interface and pmic */ i2c_ret = i2c_v1_init(); //retry 3 times for pmic wrapper init pwrap_init_preloader(); pmic_ret = pmic6320_init(); //enable long press reboot function*************** #ifndef EVB_PLATFORM #ifdef KPD_PMIC_LPRST_TD #ifdef ONEKEY_REBOOT_NORMAL_MODE_PL pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT);//pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT); pmic_config_interface(GPIO_SMT_CON3,0x01, PMIC_RG_HOMEKEY_PUEN_MASK, PMIC_RG_HOMEKEY_PUEN_SHIFT);//pull up homekey pin of PMIC for 89 project pmic_config_interface(TOP_RST_MISC, (U32)KPD_PMIC_LPRST_TD, PMIC_RG_PWRKEY_RST_TD_MASK, PMIC_RG_PWRKEY_RST_TD_SHIFT); #endif #ifdef TWOKEY_REBOOT_NORMAL_MODE_PL pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT);//pmic package function for long press reboot function setting// pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_HOMEKEY_RST_EN_MASK, PMIC_RG_HOMEKEY_RST_EN_SHIFT);;//pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_HOMEKEY_RST_EN_MASK, PMIC_RG_HOMEKEY_RST_EN_SHIFT); pmic_config_interface(GPIO_SMT_CON3,0x01, PMIC_RG_HOMEKEY_PUEN_MASK, PMIC_RG_HOMEKEY_PUEN_SHIFT);//pull up homekey pin of PMIC for 89 project pmic_config_interface(TOP_RST_MISC, (U32)KPD_PMIC_LPRST_TD, PMIC_RG_PWRKEY_RST_TD_MASK, PMIC_RG_PWRKEY_RST_TD_SHIFT); #endif #endif #endif //************************************************ print("%s Init I2C: %s(%d)\n", MOD, i2c_ret ? "FAIL" : "OK", i2c_ret); print("%s Init PWRAP: %s(%d)\n", MOD, pwrap_ret ? "FAIL" : "OK", pwrap_ret); print("%s Init PMIC: %s(%d)\n", MOD, pmic_ret ? "FAIL" : "OK", pmic_ret); print("%s chip[%x]\n", MOD, platform_chip_ver()); }
void mt_pll_init(void) { kal_uint32 temp = 0; *ARMPLL_CON2 = 0x0652; // ARMPLL_BR = 1; ARMPLL_BP = 1; ARMPLL_DIVEN = 2 *MAINPLL_CON2 = 0x0652; // MAINPLL_BR = 1; MAINPLL_BP = 1; MAINPLL_DIVEN = 2 *IPLL_CON2 = 0x0652; // IPLL_BR = 1; IPLL_BP = 1; IPLL_DIVEN = 2 *PLL_CON2 = 0x0000; // WPLL, MDPLL, MEMPLL, MAINPLL, ARMPLL from ap_sleep control. CLKSQ_EN from SRCLKEN *PLL_CON9 = 0x271B; // TVDDS stable time0 for tuning TVDDS enable timing *PLL_CON10 = 0x0229; // TVDDS stable time2 for tuning TVDDS enable timing if (platform_chip_ver() >= CHIP_6577_E1) { if ((DRV_Reg32(HW_RESV) & (0x1 << 23)) && ((DRV_Reg32(HW_RESV) & (0x1 << 20)) == 0)) { *ARMPLL_CON0 = 0x5CA0; } else { if (DRV_Reg32(HW_RESV) & (0x1 << 12)) { if ((DRV_Reg32(HW_RESV) & (0x1 << 17)) && ((DRV_Reg32(HW_RESV) & (0x1 << 16)) == 0)) { *ARMPLL_CON0 = 0x5CA0; } else { *ARMPLL_CON0 = 0x4CA0; } } else { *ARMPLL_CON0 = 0x4CA0; } } gpt_busy_wait_us(120); } else { if ((DRV_Reg32(HW_RESV) & (0x1 << 28))) { *ARMPLL_CON0 = 0x48A0; } else { *ARMPLL_CON0 = 0x4CA0; } gpt_busy_wait_us(120); } *MAINPLL_CON0 = 0x2460; // MAINPLL 962Mhz gpt_busy_wait_us(120); // wait 80us (min delay is 20us) *IPLL_CON1 = 0x0036; // 2^6 * Tin *IPLL_CON0 = 0x5741; // init ISPLL 143Mhz but default disable gpt_busy_wait_us(80); // wait 80 (min delay is 20us) *UPLL_CON0 = 0x1710; // USBPLL 624MHz (for USB 2.0 and 1.0 Phy) gpt_busy_wait_us(80); // wait 80us (min delay is 20us) *UPLL_CON0 = 0x1712; // Set USBPLL to 48Mhz output enable #if 0 *MDPLL_CON0 = 0x1310; // enable MDPLL 1040Mhz gpt_busy_wait_us(80); // wait 80us (min delay is 20us) *MDPLL_CON0 = 0x1312; // Set MDPLL to 297.14Mhz output enable #else if (CHIP_VER_E1 != platform_chip_ver()) *MDPLL_CON0 = 0x1310; // enable MDPLL 1040Mhz else *MDPLL_CON0 = 0x1311; // restore to default value to turn off MDPLL and controlled by SRCLKEN #endif if (CHIP_VER_E1 != platform_chip_ver()) { *TOPCKGEN_CON3 = 0xC000; //[14] = 1, choose MDPLL instead of MAINPLL. [15] = 1, Enable MDPLL clock path } *WPLL_CON0 = 0x403B; // 3GPLL 197Mhz, 492Mhz, 61Mhz enable, turn on enable bit gpt_busy_wait_us(120); // wait 120us (min delay is 30us) #if 0 *WPLL_CON0 = 0x403E; // 3GPLL 197Mhz, 281Mhz, 492Mhz, 61Mhz enable #endif *PLL_CON1 = 0x4113; // Reference clock is from ANA 26Mhz (Clock to MEMPLL enable) *MEMPLL_CON0 = 0x0910; // VCO = (BUS Freq/10) * (9+1) * 4 / 1 *MEMPLL_CON1 = 0x0026; // MEMPLL = VCO/4 gpt_busy_wait_us(80); // wait 80us (min delay is 20us) if (platform_chip_ver() >= CHIP_6577_E1) { *TOP_MISC = 0x102; // Force MUX1 to use 26Mhz and turn on enable_gen } else { *TOP_MISC = 0x101; // Force MUX1 to use 26Mhz and turn on enable_gen } *TOP_CKDIV0 = 0x10; // BUS clock will divide by 5 *TOP_CKDIV1 = 0xA; // CA9 clock will divide by 2 if (CHIP_VER_E1 != platform_chip_ver()) *TOP_CKDIV23 = 0x1; // enable clock divider 2 to export /4 clock to mm system else *TOP_CKDIV23 = 0x0; // disable clock divider 2 to export /4 clock to mm system if (CHIP_VER_E1 != platform_chip_ver()) *TOP_CKMUXSEL = 0x259; // Mux0 using MAINPLL, Mux1 using ARMPLL, MUX2 using MAINPLL, Mux3 From Mux1, MUX4 using CLKSQ, MUX6 using CLKSQ else *TOP_CKMUXSEL = 0x249; // Mux0 using MAINPLL, Mux1 using ARMPLL, MUX2 using CLKSQ, Mux3 From Mux1, MUX4 using CLKSQ, MUX6 using CLKSQ *TVDAC_CON0 = 0x1012; // Power down TVDAC for power saving temp = *CLK_CTL0; temp |= 0x00000200; *CLK_CTL0 = temp; // enable the L2C clock gating while SCU is in idle state temp = *PERI_PDN0; *PERI_PDN0 = temp | 0x7C; // gate all PWM clock bits }
void platform_pre_init(void) { u32 ret; u32 pmic_ret; u32 pwrap_ret,i; #ifdef PL_PROFILING u32 profiling_time; profiling_time = 0; #endif pwrap_ret = 0; i = 0; ret = 0; /* init timer */ mtk_timer_init(); /* init boot time */ g_boot_time = get_timer(0); #if 0 /* FIXME */ /* * NoteXXX: CPU 1 may not be reset clearly after power-ON. * Need to apply a S/W workaround to manualy reset it first. */ { U32 val; val = DRV_Reg32(0xC0009010); DRV_WriteReg32(0xC0009010, val | 0x2); gpt_busy_wait_us(10); DRV_WriteReg32(0xC0009010, val & ~0x2); gpt_busy_wait_us(10); } #ifndef SLT_BOOTLOADER /* power off cpu1 for power saving */ power_off_cpu1(); #endif #endif ptp_init1(); /* move pll code to audio_sys_ram */ memcpy((char *)&Image$$PLL_INIT$$Base, &__load_start_pll_text, &__load_stop_pll_text - &__load_start_pll_text); /* init pll */ /* for memory preserved mode */ // do not init pll/emi in memory preserved mode, due to code is located in EMI // set all pll except EMI mtk_pll_init(); /*GPIO init*/ #if (!(CFG_FPGA_PLATFORM)) && defined(DUMMY_AP_BOOTLOADER) mt_gpio_set_default(); #endif //set UART1 GPIO to mode1, AP mt_gpio_init_post(0); /* init uart baudrate when pll on */ mtk_uart_init(UART_SRC_CLK_FRQ, CFG_LOG_BAUDRATE); /* init pmic i2c interface and pmic */ /* no need in MT6572*/ //i2c_ret = i2c_v1_init(); //retry 3 times for pmic wrapper init #ifdef PL_PROFILING profiling_time = get_timer(0); #endif pwrap_init_preloader(); /* check is uart cable in*/ #if (CFG_USB_UART_SWITCH) platform_vusb_on(); if (is_uart_cable_inserted()) { print("\n%s Switch to UART Mode\n", MOD); mt_usb_set_to_uart_mode(); } else { print("\n%s Keep stay in USB Mode\n", MOD); } #endif if (platform_sram_repair_enable_check()) { //MM SRAM Repair ret = MFG_MM_SRAM_repair(); if (ret < 0 ) printf("MFG_MM_SRAM_repair fail\n"); else printf("MFG_MM_SRAM_repair OK\n"); } #ifdef PL_PROFILING printf("#T#pwrap_init=%d\n", get_timer(profiling_time)); profiling_time = get_timer(0); //for next #endif pmic_ret = pmic_init(); //enable long press reboot function*************** #ifndef CFG_EVB_PLATFORM #ifdef KPD_PMIC_LPRST_TD #ifdef ONEKEY_REBOOT_NORMAL_MODE_PL printf("ONEKEY_REBOOT_NORMAL_MODE_PL OK\n"); pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT);//pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT); pmic_config_interface(TOP_RST_MISC, (U32)KPD_PMIC_LPRST_TD, PMIC_RG_PWRKEY_RST_TD_MASK, PMIC_RG_PWRKEY_RST_TD_SHIFT); #endif #endif #endif //************************************************ #ifdef PL_PROFILING printf("#T#pmic_init=%d\n", get_timer(profiling_time)); #endif print("%s Init PWRAP: %s(%d)\n", MOD, pwrap_ret ? "FAIL" : "OK", pwrap_ret); print("%s Init PMIC: %s(%d)\n", MOD, pmic_ret ? "FAIL" : "OK", pmic_ret); print("%s chip[%x]\n", MOD, platform_chip_ver()); }