static int pmu_parse_irqs(struct arm_pmu *pmu) { int i = 0, num_irqs; struct platform_device *pdev = pmu->plat_device; struct pmu_hw_events __percpu *hw_events = pmu->hw_events; num_irqs = platform_irq_count(pdev); if (num_irqs < 0) { pr_err("unable to count PMU IRQs\n"); return num_irqs; } /* * In this case we have no idea which CPUs are covered by the PMU. * To match our prior behaviour, we assume all CPUs in this case. */ if (num_irqs == 0) { pr_warn("no irqs for PMU, sampling events not supported\n"); pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; cpumask_setall(&pmu->supported_cpus); return 0; } if (num_irqs == 1) { int irq = platform_get_irq(pdev, 0); if (irq && irq_is_percpu(irq)) return pmu_parse_percpu_irq(pmu, irq); } if (!pmu_has_irq_affinity(pdev->dev.of_node)) { pr_warn("no interrupt-affinity property for %pOF, guessing.\n", pdev->dev.of_node); } /* * Some platforms have all PMU IRQs OR'd into a single IRQ, with a * special platdata function that attempts to demux them. */ if (dev_get_platdata(&pdev->dev)) cpumask_setall(&pmu->supported_cpus); for (i = 0; i < num_irqs; i++) { int cpu, irq; irq = platform_get_irq(pdev, i); if (WARN_ON(irq <= 0)) continue; if (irq_is_percpu(irq)) { pr_warn("multiple PPIs or mismatched SPI/PPI detected\n"); return -EINVAL; } cpu = pmu_parse_irq_affinity(pdev->dev.of_node, i); if (cpu < 0) return cpu; if (cpu >= nr_cpu_ids) continue; if (per_cpu(hw_events->irq, cpu)) { pr_warn("multiple PMU IRQs for the same CPU detected\n"); return -EINVAL; } per_cpu(hw_events->irq, cpu) = irq; cpumask_set_cpu(cpu, &pmu->supported_cpus); } return 0; }
static int pmic_mpp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pindesc; struct pinctrl_desc *pctrldesc; struct pmic_mpp_pad *pad, *pads; struct pmic_mpp_state *state; int ret, npins, i; u32 reg; ret = of_property_read_u32(dev->of_node, "reg", ®); if (ret < 0) { dev_err(dev, "missing base address"); return ret; } npins = platform_irq_count(pdev); if (!npins) return -EINVAL; if (npins < 0) return npins; BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); if (!state) return -ENOMEM; platform_set_drvdata(pdev, state); state->dev = &pdev->dev; state->map = dev_get_regmap(dev->parent, NULL); pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); if (!pindesc) return -ENOMEM; pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); if (!pads) return -ENOMEM; pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); if (!pctrldesc) return -ENOMEM; pctrldesc->pctlops = &pmic_mpp_pinctrl_ops; pctrldesc->pmxops = &pmic_mpp_pinmux_ops; pctrldesc->confops = &pmic_mpp_pinconf_ops; pctrldesc->owner = THIS_MODULE; pctrldesc->name = dev_name(dev); pctrldesc->pins = pindesc; pctrldesc->npins = npins; pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings); pctrldesc->custom_params = pmic_mpp_bindings; #ifdef CONFIG_DEBUG_FS pctrldesc->custom_conf_items = pmic_conf_items; #endif for (i = 0; i < npins; i++, pindesc++) { pad = &pads[i]; pindesc->drv_data = pad; pindesc->number = i; pindesc->name = pmic_mpp_groups[i]; pad->irq = platform_get_irq(pdev, i); if (pad->irq < 0) return pad->irq; pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; ret = pmic_mpp_populate(state, pad); if (ret < 0) return ret; } state->chip = pmic_mpp_gpio_template; state->chip.parent = dev; state->chip.base = -1; state->chip.ngpio = npins; state->chip.label = dev_name(dev); state->chip.of_gpio_n_cells = 2; state->chip.can_sleep = false; state->ctrl = pinctrl_register(pctrldesc, dev, state); if (IS_ERR(state->ctrl)) return PTR_ERR(state->ctrl); ret = gpiochip_add_data(&state->chip, state); if (ret) { dev_err(state->dev, "can't add gpio chip\n"); goto err_chip; } ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); if (ret) { dev_err(dev, "failed to add pin range\n"); goto err_range; } return 0; err_range: gpiochip_remove(&state->chip); err_chip: pinctrl_unregister(state->ctrl); return ret; }