long int pcl_configure_usb_clock(void) { #ifndef AVR32_PM_VERSION_RESETVALUE // Implementation for UC3A, UC3A3, UC3B parts. pm_configure_usb_clock(); return PASS; #else #ifdef AVR32_PM_410_H_INCLUDED const scif_pll_opt_t opt = { .osc = SCIF_OSC0, // Sel Osc0 or Osc1 .lockcount = 16, // lockcount in main clock for the PLL wait lock .div = 1, // DIV=1 in the formula .mul = 5, // MUL=7 in the formula .pll_div2 = 1, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) .pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. .pll_freq = 1, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. }; /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */ scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock /* Enable PLL1 */ scif_pll_enable(SCIF_PLL1); /* Wait for PLL1 locked */ scif_wait_for_pll_locked(SCIF_PLL1) ; // Implementation for UC3C parts. // Setup the generic clock for USB scif_gc_setup(AVR32_SCIF_GCLK_USB, SCIF_GCCTRL_PLL1, AVR32_SCIF_GC_NO_DIV_CLOCK, 0); // Now enable the generic clock scif_gc_enable(AVR32_SCIF_GCLK_USB); return PASS; #else return PCL_NOT_SUPPORTED; #endif #endif } #if UC3L #else void pcl_write_gplp(unsigned long gplp, unsigned long value) { #ifndef AVR32_PM_VERSION_RESETVALUE // Implementation for UC3A, UC3A3, UC3B parts. pm_write_gplp(&AVR32_PM,gplp,value); #else scif_write_gplp(gplp,value); #endif }
/*! \brief Initializes the USB clock. */ static void init_usb_clock(void) { pm_configure_usb_clock(); }