static void fsl_booke_reg_setup(struct op_counter_config *ctr,
struct op_system_config *sys,
int num_ctrs)
{
int i;
num_counters = num_ctrs;
/* freeze all counters */
pmc_stop_ctrs();
/* Our counters count up, and "count" refers to
* how much before the next interrupt, and we interrupt
* on overflow. So we calculate the starting value
* which will give us "count" until overflow.
* Then we set the events on the enabled counters */
for (i = 0; i < num_counters; ++i) {
reset_value[i] = 0x80000000UL - ctr[i].count;
init_pmc_stop(i);
set_pmc_event(i, ctr[i].event);
set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
}
}
/* Configures the counters on this CPU based on the global
* settings */
static void fsl7450_cpu_setup(struct op_counter_config *ctr)
{
/* freeze all counters */
pmc_stop_ctrs();
mtspr(SPRN_MMCR0, mmcr0_val);
mtspr(SPRN_MMCR1, mmcr1_val);
mtspr(SPRN_MMCR2, mmcr2_val);
}
/* Stop the counters on this CPU */
static void fsl7450_stop(void)
{
/* freeze counters */
pmc_stop_ctrs();
oprofile_running = 0;
mb();
}
static void fsl7450_stop(void)
{
/* */
pmc_stop_ctrs();
oprofile_running = 0;
mb();
}
static void fsl_emb_stop(void)
{
/* freeze counters */
pmc_stop_ctrs();
oprofile_running = 0;
pr_debug("stop on cpu %d, pmgc0 %x\n", smp_processor_id(),
mfpmr(PMRN_PMGC0));
mb();
}
static int fsl7450_cpu_setup(struct op_counter_config *ctr)
{
/* */
pmc_stop_ctrs();
mtspr(SPRN_MMCR0, mmcr0_val);
mtspr(SPRN_MMCR1, mmcr1_val);
if (num_pmcs > 4)
mtspr(SPRN_MMCR2, mmcr2_val);
return 0;
}
static void fsl_booke_cpu_setup(struct op_counter_config *ctr)
{
int i;
/* freeze all counters */
pmc_stop_ctrs();
for (i = 0;i < num_counters;i++) {
init_pmc_stop(i);
set_pmc_event(i, ctr[i].event);
set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
}
}
