static int pmic_clk_enable(struct clk_hw *hw)
{
struct pmic_clk *clk_pmic = container_of(hw, struct pmic_clk, hw);
u32 reg_val = 0;
unsigned long rfclk_flag = 0;
spin_lock_irqsave(&g_pmic_xoinfo.xorf_lock, rfclk_flag);
/* 打开前写0 */
pmic_reg_read(clk_pmic->freq_addr_offset, ®_val);
reg_val &= (~(clk_pmic->freq_mask));
pmic_reg_write(clk_pmic->freq_addr_offset, reg_val);
/*enable clk*/
pmic_mutli_core_lock();
pmic_reg_read(clk_pmic->en_dis_offset, ®_val);
reg_val |= (((u32)0x1) << clk_pmic->en_dis_bit);
pmic_reg_write(clk_pmic->en_dis_offset, reg_val);
pmic_mutli_core_unlock();
/*delay 6us*/
udelay(clk_pmic->delay_us);
/* 打开后写1 */
pmic_reg_read(clk_pmic->freq_addr_offset, ®_val);
reg_val |= clk_pmic->freq_mask;
pmic_reg_write(clk_pmic->freq_addr_offset, reg_val);
spin_unlock_irqrestore(&g_pmic_xoinfo.xorf_lock, rfclk_flag);
return 0;
}
void exynos_lcd_power_on(void)
{
struct udevice *dev;
int ret;
u8 reg;
ret = pmic_get("max8998-pmic", &dev);
if (ret) {
puts("Failed to get MAX8998!\n");
return;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3);
reg |= MAX8998_LDO17;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg);
if (ret) {
puts("MAX8998 LDO setting error\n");
return;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
reg |= MAX8998_LDO7;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
if (ret) {
puts("MAX8998 LDO setting error\n");
return;
}
}
void ldo_mode_set(int ldo_bypass)
{
unsigned int value;
struct pmic *p = pfuze;
if (!p) {
printf("No PMIC found!\n");
return;
}
/* switch to ldo_bypass mode */
if (ldo_bypass) {
/* decrease VDDARM to 1.15V */
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
value &= ~0x3f;
value |= PFUZE100_SW1ABC_SETP(11500);
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
/* decrease VDDSOC to 1.15V */
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
value &= ~0x3f;
value |= PFUZE100_SW1ABC_SETP(11500);
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
set_anatop_bypass(1);
printf("switch to ldo_bypass mode!\n");
}
}
void power_init(void)
{
unsigned int val;
struct pmic *p;
pmic_init();
p = get_pmic();
/* Set VDDA to 1.25V */
pmic_reg_read(p, REG_SW_2, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_25;
pmic_reg_write(p, REG_SW_2, val);
/*
* Need increase VCC and VDDA to 1.3V
* according to MX53 IC TO2 datasheet.
*/
if (is_soc_rev(CHIP_REV_2_0) == 0) {
/* Set VCC to 1.3V for TO2 */
pmic_reg_read(p, REG_SW_1, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_30;
pmic_reg_write(p, REG_SW_1, val);
/* Set VDDA to 1.3V for TO2 */
pmic_reg_read(p, REG_SW_2, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_30;
pmic_reg_write(p, REG_SW_2, val);
}
}
void ldo_mode_set(int ldo_bypass)
{
unsigned int value;
u32 vddarm;
struct pmic *p = pfuze;
if (!p) {
printf("No PMIC found!\n");
return;
}
/* switch to ldo_bypass mode */
if (ldo_bypass) {
prep_anatop_bypass();
/* decrease VDDARM to 1.275V */
pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
value &= ~0x1f;
value |= PFUZE300_SW1AB_SETP(1275);
pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
set_anatop_bypass(1);
vddarm = PFUZE300_SW1AB_SETP(1175);
pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
value &= ~0x1f;
value |= vddarm;
pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
finish_anatop_bypass();
printf("switch to ldo_bypass mode!\n");
}
}
int power_init_board(void)
{
struct pmic *p;
unsigned int reg, ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
ret = pfuze_mode_init(p, APS_PFM);
if (ret < 0)
return ret;
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_2_80V;
pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
/* Increase VGEN5 from 2.8 to 3V */
pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_3_00V;
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
return 0;
}
static int s5pc210_phy_control(int on)
{
int ret = 0;
u32 val = 0;
struct pmic *p = get_pmic();
if (pmic_probe(p))
return -1;
if (on) {
ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
ENSAFEOUT1, LDO_ON);
ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
} else {
ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
ENSAFEOUT1, LDO_OFF);
}
if (ret) {
puts("MAX8997 LDO setting error!\n");
return -1;
}
return 0;
}
static int axp228_regu_set_voltage(struct pmic *p, int type, int vol)
{
int ret = 0;
u32 val = 0;
PMIC_DBGOUT("%s\n", __func__);
if (pmic_probe(p))
return -1;
switch(type)
{
case REGULATOR_ARM:
/* REG 22H:DCDC2 Output Voltage Set */
val = axp228_regu_get_vol_step(vol, AXP22_DCDC2_STEP, AXP22_DCDC2_MIN, AXP22_DCDC2_MAX);
pmic_reg_write(p, AXP22_DC2OUT_VOL, val);
p->regu->arm_vol = vol;
break;
case REGULATOR_CORE:
/* REG 23H:DCDC3 Output Voltage Set */
val = axp228_regu_get_vol_step(vol, AXP22_DCDC3_STEP, AXP22_DCDC3_MIN, AXP22_DCDC3_MAX);
pmic_reg_write(p, AXP22_DC3OUT_VOL, val);
p->regu->core_vol = vol;
break;
}
return ret;
}
void ldo_mode_set(int ldo_bypass)
{
u32 value;
int is_400M;
struct pmic *p = pfuze;
if (!p) {
printf("No pmic!\n");
return;
}
/* swith to ldo_bypass mode */
if (ldo_bypass) {
prep_anatop_bypass();
/* decrease VDDARM to 1.1V */
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
value &= ~0x3f;
value |= 0x20;
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
/* increase VDDSOC to 1.3V */
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
value &= ~0x3f;
value |= 0x28;
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
is_400M = set_anatop_bypass(0);
/*
* MX6SL: VDDARM:1.175V@800M; VDDSOC:1.175V@800M
* VDDARM:0.975V@400M; VDDSOC:1.175V@400M
*/
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
value &= ~0x3f;
if (is_400M)
value |= 0x1b;
else
value |= 0x23;
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
/* decrease VDDSOC to 1.175V */
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
value &= ~0x3f;
value |= 0x23;
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
finish_anatop_bypass();
printf("switch to ldo_bypass mode!\n");
}
}
static void power_init_mx51(void)
{
unsigned int val;
/* Write needed to Power Gate 2 register */
val = pmic_reg_read(REG_POWER_MISC);
/* enable VCAM with 2.775V to enable read from PMIC */
val = VCAMCONFIG | VCAMEN;
pmic_reg_write(REG_MODE_1, val);
/*
* Set switchers in Auto in NORMAL mode & STANDBY mode
* Setup the switcher mode for SW1 & SW2
*/
val = pmic_reg_read(REG_SW_4);
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
(SWMODE_MASK << SWMODE2_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
pmic_reg_write(REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
val = pmic_reg_read(REG_SW_5);
val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
(SWMODE_MASK << SWMODE3_SHIFT));
val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
pmic_reg_write(REG_SW_5, val);
/* Set VGEN3 to 1.8V, VCAM to 3.0V */
val = pmic_reg_read(REG_SETTING_0);
val &= ~(VCAM_MASK | VGEN3_MASK);
val |= VCAM_3_0;
pmic_reg_write(REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
val = pmic_reg_read(REG_SETTING_1);
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
pmic_reg_write(REG_SETTING_1, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = VGEN3CONFIG | VCAMCONFIG;
pmic_reg_write(REG_MODE_1, val);
udelay(200);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
VVIDEOEN | VAUDIOEN | VSDEN;
pmic_reg_write(REG_MODE_1, val);
val = pmic_reg_read(REG_POWER_CTL2);
val |= WDIRESET;
pmic_reg_write(REG_POWER_CTL2, val);
udelay(2500);
}
void board_pmic_gpadc_fixup(struct pmic *p_gpadc)
{
u32 val, buf0, buf1;
/*
* enable gpadc1 to detect battery, by default
* enable gpadc3 to measure board version
* enable vbat to measure battery voltage, by default
*/
pmic_reg_read(p_gpadc, 0x2, &val);
val |= 0x22;
pmic_reg_write(p_gpadc, 0x2, val);
/* set bias current for gpadc1: 11uA */
pmic_reg_read(p_gpadc, 0xc, &val);
val |= 0x2;
pmic_reg_write(p_gpadc, 0xc, val);
/* enable gpadc1 bias */
pmic_reg_read(p_gpadc, 0x14, &val);
val |= 0x22;
pmic_reg_write(p_gpadc, 0x14, val);
/* enable gpadc1 battery detection */
pmic_reg_read(p_gpadc, 0x8, &val);
val |= 0x60;
pmic_reg_write(p_gpadc, 0x8, val);
mdelay(1);
/* get dkb version */
pmic_reg_read(p_gpadc, 0xa6, &buf0);
pmic_reg_read(p_gpadc, 0xa7, &buf1);
val = (buf0 << 4) | (buf1 & 0xf);
val = ((val & 0xfff) * 7 * 100) >> 11;
printf("board id voltage value = %d\n", val);
/*
* board id:
* helandkb1.0->DKB_10 0.9V
* helandkb1.1->DKB_11 1.2V
* t7 tablet1.1->DKB_T7V1 0.6V
* t7 tablet1.2->DKB_T7V1 0.3V
*/
if ((val < 1050) && (val > 750))
dkb_version = DKB_10;
else if ((val < 1500) && (val > 1050))
dkb_version = DKB_11;
else if ((val < 750) && (val > 450))
dkb_version = DKB_T7V1;
else
dkb_version = DKB_T7V2;
}
static int init_pmic_lcd(void)
{
struct udevice *dev;
unsigned char val;
int ret = 0;
ret = pmic_get("max8998-pmic", &dev);
if (ret) {
puts("Failed to get MAX8998 for init_pmic_lcd()!\n");
return ret;
}
/* LDO7 1.8V */
val = 0x02; /* (1800 - 1600) / 100; */
ret |= pmic_reg_write(dev, MAX8998_REG_LDO7, val);
/* LDO17 3.0V */
val = 0xe; /* (3000 - 1600) / 100; */
ret |= pmic_reg_write(dev, MAX8998_REG_LDO17, val);
/* Disable unneeded regulators */
/*
* ONOFF1
* Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
* LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
*/
val = 0xB9;
ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, val);
/* ONOFF2
* LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
* LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
*/
val = 0x50;
ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, val);
/* ONOFF3
* LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
* EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
*/
val = 0x00;
ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF3, val);
if (ret) {
puts("LCD pmic initialisation error!\n");
return -EINVAL;
}
return 0;
}
static int pfuze_init(void)
{
struct pmic *p;
int ret;
unsigned int reg;
ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return ret;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return ret;
pmic_reg_read(p, PFUZE100_DEVICEID, ®);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
/* Set SW1AB standby voltage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
/* Enable power of VGEN5 3V3, needed for SD3 */
pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
reg &= ~0x1F;
reg |= 0x1F;
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
return 0;
}
static int power_init(void)
{
unsigned int val;
int ret = -1;
struct pmic *p;
if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
pmic_dialog_init();
p = get_pmic();
/* Set VDDA to 1.25V */
val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
val |= DA9052_SUPPLY_VBCOREGO;
ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
/* Set Vcc peripheral to 1.30V */
ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
}
if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
pmic_init();
p = get_pmic();
/* Set VDDGP to 1.25V for 1GHz on SW1 */
pmic_reg_read(p, REG_SW_0, &val);
val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
ret = pmic_reg_write(p, REG_SW_0, val);
/* Set VCC as 1.30V on SW2 */
pmic_reg_read(p, REG_SW_1, &val);
val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
ret |= pmic_reg_write(p, REG_SW_1, val);
/* Set global reset timer to 4s */
pmic_reg_read(p, REG_POWER_CTL2, &val);
val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
/* Set VUSBSEL and VUSBEN for USB PHY supply*/
pmic_reg_read(p, REG_MODE_0, &val);
val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
ret |= pmic_reg_write(p, REG_MODE_0, val);
/* Set SWBST to 5V in auto mode */
val = SWBST_AUTO;
ret |= pmic_reg_write(p, SWBST_CTRL, val);
}
return ret;
}
static int pm8916_gpio_set_direction(struct udevice *dev, unsigned offset,
bool input, int value)
{
struct pm8916_gpio_bank *priv = dev_get_priv(dev);
uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
int ret;
/* Disable the GPIO */
ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
REG_EN_CTL_ENABLE, 0);
if (ret < 0)
return ret;
/* Select the mode */
if (input)
ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL,
REG_CTL_MODE_INPUT);
else
ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL,
REG_CTL_MODE_INOUT | (value ? 1 : 0));
if (ret < 0)
return ret;
/* Set the right pull (no pull) */
ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
REG_DIG_PULL_NO_PU);
if (ret < 0)
return ret;
/* Configure output pin drivers if needed */
if (!input) {
/* Select the VIN - VIN0, pin is input so it doesn't matter */
ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
REG_DIG_VIN_VIN0);
if (ret < 0)
return ret;
/* Set the right dig out control */
ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_OUT_CTL,
REG_DIG_OUT_CTL_CMOS |
REG_DIG_OUT_CTL_DRIVE_L);
if (ret < 0)
return ret;
}
/* Enable the GPIO */
return pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, 0,
REG_EN_CTL_ENABLE);
}
static int s5pc1xx_phy_control(int on)
{
struct udevice *dev;
static int status;
int reg, ret;
ret = pmic_get("max8998-pmic", &dev);
if (ret)
return ret;
if (on && !status) {
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
reg |= MAX8998_LDO3;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -EINVAL;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
reg |= MAX8998_LDO8;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -EINVAL;
}
status = 1;
} else if (!on && status) {
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
reg &= ~MAX8998_LDO3;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -EINVAL;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
reg &= ~MAX8998_LDO8;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -EINVAL;
}
status = 0;
}
udelay(10000);
return 0;
}
int power_init_board(void)
{
struct pmic *p;
int ret;
unsigned int reg, rev_id;
ret = power_pfuze3000_init(I2C_PMIC);
if (ret)
return ret;
p = pmic_get("PFUZE3000");
ret = pmic_probe(p);
if (ret)
return ret;
pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
/* disable Low Power Mode during standby mode */
pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
reg |= 0x1;
pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
return 0;
}
/* setup board specific PMIC */
int power_init_board(void)
{
struct pmic *p;
u32 reg;
int ret;
power_pfuze100_init(1);
p = pmic_get("PFUZE100");
if (!p)
return -EINVAL;
ret = pmic_probe(p);
if (ret)
return ret;
pmic_reg_read(p, PFUZE100_DEVICEID, ®);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
/* Set SWBST to 5.0V and enable (for USB) */
pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
return 0;
}
static int lp873x_buck_enable(struct udevice *dev, int op, bool *enable)
{
int ret;
unsigned int adr;
struct dm_regulator_uclass_platdata *uc_pdata;
uc_pdata = dev_get_uclass_platdata(dev);
adr = uc_pdata->ctrl_reg;
ret = pmic_reg_read(dev->parent, adr);
if (ret < 0)
return ret;
if (op == PMIC_OP_GET) {
ret &= LP873X_BUCK_MODE_MASK;
if (ret)
*enable = true;
else
*enable = false;
return 0;
} else if (op == PMIC_OP_SET) {
if (*enable)
ret |= LP873X_BUCK_MODE_MASK;
else
ret &= ~(LP873X_BUCK_MODE_MASK);
ret = pmic_reg_write(dev->parent, adr, ret);
if (ret)
return ret;
}
return 0;
}
/**
* Set the power state for a FET
*
* @param pmic pmic structure for the tps65090
* @param fet_id Fet number to set (1..MAX_FET_NUM)
* @param set 1 to power on FET, 0 to power off
* @return -EIO if we got a comms error, -EAGAIN if the FET failed to
* change state. If all is ok, returns 0.
*/
static int tps65090_fet_set(struct pmic *pmic, int fet_id, bool set)
{
int retry;
u32 reg, value;
value = FET_CTRL_ADENFET | FET_CTRL_WAIT;
if (set)
value |= FET_CTRL_ENFET;
if (pmic_reg_write(pmic, REG_FET1_CTRL + fet_id - 1, value))
return -EIO;
/* Try reading until we get a result */
for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) {
if (pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®))
return -EIO;
/* Check that the fet went into the expected state */
if (!!(reg & FET_CTRL_PGFET) == set)
return 0;
/* If we got a timeout, there is no point in waiting longer */
if (reg & FET_CTRL_TOFET)
break;
mdelay(1);
}
debug("FET %d: Power good should have set to %d but reg=%#02x\n",
fet_id, set, reg);
return -EAGAIN;
}
int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV)
{
unsigned int val, adr;
int hex, ret;
if (buck < 5 || buck > 9) {
printf("%s: %d is an unsupported bucket number\n",
__func__, buck);
return -EINVAL;
}
adr = max77686_buck_addr[buck] + 1;
hex = max77686_buck_volt2hex(buck, uV);
if (hex < 0)
return hex;
ret = pmic_reg_read(p, adr, &val);
if (ret)
return ret;
val &= ~MAX77686_BUCK_VOLT_MASK;
ret |= pmic_reg_write(p, adr, val | hex);
return ret;
}
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
{
unsigned int val, ret, hex, adr;
if (ldo < 1 || ldo > 26) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
return -1;
}
adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
hex = max77686_ldo_volt2hex(ldo, uV);
if (!hex)
return -1;
ret = pmic_reg_read(p, adr, &val);
if (ret)
return ret;
val &= ~MAX77686_LDO_VOLT_MASK;
val |= hex;
ret |= pmic_reg_write(p, adr, val);
return ret;
}
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
{
unsigned int val, ret, adr, mode;
if (ldo < 1 || 26 < ldo) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
return -1;
}
adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
/* mode */
switch (opmode) {
case OPMODE_OFF:
mode = MAX77686_LDO_MODE_OFF;
break;
case OPMODE_STANDBY:
switch (ldo) {
case 2:
case 6:
case 7:
case 8:
case 10:
case 11:
case 12:
case 14:
case 15:
case 16:
mode = MAX77686_LDO_MODE_STANDBY;
break;
default:
mode = 0xff;
}
break;
case OPMODE_LPM:
mode = MAX77686_LDO_MODE_LPM;
break;
case OPMODE_ON:
mode = MAX77686_LDO_MODE_ON;
break;
default:
mode = 0xff;
}
if (mode == 0xff) {
printf("%s: %d is not supported on LDO%d\n",
__func__, opmode, ldo);
return -1;
}
ret = pmic_reg_read(p, adr, &val);
if (ret)
return ret;
val &= ~MAX77686_LDO_MODE_MASK;
val |= mode;
ret |= pmic_reg_write(p, adr, val);
return ret;
}
int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *cmd;
int nregs;
u32 val;
/* at least two arguments please */
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
cmd = argv[1];
if (strcmp(cmd, "dump") == 0) {
if (argc < 3) {
cmd_usage(cmdtp);
return 1;
}
nregs = simple_strtoul(argv[2], NULL, 16);
pmic_dump(nregs);
return 0;
}
if (strcmp(cmd, "write") == 0) {
if (argc < 4) {
cmd_usage(cmdtp);
return 1;
}
nregs = simple_strtoul(argv[2], NULL, 16);
val = simple_strtoul(argv[3], NULL, 16);
pmic_reg_write(nregs, val);
return 0;
}
/* No subcommand found */
return 1;
}
/**
* Interface to enable/disable PMIC USB type detection
*
* @pdata Pointer to the charger type detection driver data structure
* @enable Whether to enable/disable USB type detection
* return 0 on success, otherwise error code
*/
static int pmic_usb_enable_usb_det(struct pmic_usb_det_data *pdata, bool enable)
{
int ret;
u8 reg;
if (!pdata || !pdata->pdev)
return -EINVAL;
ret = pmic_reg_read(DEV3, USBPHYCTRL, ®);
if (ret) {
dev_err(pdata->pdev, "%s - fail to read DEV3 USBPHYCTRL\n",
__func__);
return ret;
}
if (enable) {
set_field(reg, USBPHYRSTB_O, 1, CLEAR);
set_field(reg, CTYP_DIS_O, 1, CLEAR);
} else {
set_field(reg, USBPHYRSTB_O, 1, SET);
set_field(reg, CTYP_DIS_O, 1, SET);
}
ret = pmic_reg_write(DEV3, USBPHYCTRL, reg);
if (ret) {
dev_err(pdata->pdev, "%s - fail to write DEV3 USBPHYCTRL\n",
__func__);
return ret;
}
return 0;
}
/**
* Interface to enable/disable USBID and ACA detection
*
* @pdata Pointer to the charger type detection driver data structure
* @id_enable Whether to enable/disable USBID detection
* @aca_enable Whether to enable/disable ACA detection
* return 0 on success, otherwise error code
*/
static int pmic_usb_enable_id_aca_det(struct pmic_usb_det_data *pdata,
bool id_enable, bool aca_enable)
{
int ret;
u8 reg;
if (!pdata || !pdata->pdev)
return -EINVAL;
ret = pmic_reg_read(DEV3, USBIDCTRL, ®);
if (ret) {
dev_err(pdata->pdev, "%s - fail to read DEV3 USBIDCTRL\n",
__func__);
return ret;
}
if (id_enable) {
set_field(reg, USB_IDEN_O, 1, SET);
if (aca_enable)
set_field(reg, ACA_DETEN_O, 1, SET);
} else {
set_field(reg, USB_IDEN_O, 1, CLEAR);
set_field(reg, ACA_DETEN_O, 1, CLEAR);
}
ret = pmic_reg_write(DEV3, USBIDCTRL, reg);
if (ret) {
dev_err(pdata->pdev, "%s - fail to write DEV3 USBIDCTRL\n",
__func__);
return ret;
}
return 0;
}
int rtc_set(struct rtc_time *rtc)
{
u32 time, day;
struct pmic *p = pmic_get("FSL_PMIC");
if (!p)
return -1;
time = rtc_mktime(rtc);
day = time / 86400;
time %= 86400;
pmic_reg_write(p, REG_RTC_DAY, day);
pmic_reg_write(p, REG_RTC_TIME, time);
return 0;
}
static int palmas_ldo_bypass_enable(struct udevice *dev, bool enabled)
{
int type = dev_get_driver_data(dev_get_parent(dev));
struct dm_regulator_uclass_platdata *p;
unsigned int adr;
int reg;
if (type == TPS65917) {
/* bypass available only on LDO1 and LDO2 */
if (dev->driver_data > 2)
return -ENOTSUPP;
} else if (type == TPS659038) {
/* bypass available only on LDO9 */
if (dev->driver_data != 9)
return -ENOTSUPP;
}
p = dev_get_uclass_platdata(dev);
adr = p->ctrl_reg;
reg = pmic_reg_read(dev->parent, adr);
if (reg < 0)
return reg;
if (enabled)
reg |= PALMAS_LDO_BYPASS_EN;
else
reg &= ~PALMAS_LDO_BYPASS_EN;
return pmic_reg_write(dev->parent, adr, reg);
}
static int adc_power_control(int on)
{
struct udevice *dev;
int ret;
u8 reg;
ret = pmic_get("max8998-pmic", &dev);
if (ret) {
puts("Failed to get MAX8998!\n");
return ret;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
if (on)
reg |= MAX8998_LDO4;
else
reg &= ~MAX8998_LDO4;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
if (ret) {
puts("MAX8998 LDO setting error\n");
return -EINVAL;
}
return 0;
}
void reset_cpu(ulong addr)
{
struct udevice *dev;
pmic_get("rn5t567", &dev);
/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
/*
* Re-power factor detection on PMIC side is not instant. 1ms
* proved to be enough time until reset takes effect.
*/
mdelay(1);
}
