void fg_bat_l_int_handler(void)
{
bm_print(BM_LOG_CRTI, "[fg_bat_l_int_handler] \n");
pmic_set_register_value(PMIC_RG_LBAT_IRQ_EN_MIN,0);
pmic_set_register_value(PMIC_RG_LBAT_EN_MIN,0);
pmic_set_register_value(PMIC_RG_INT_EN_BAT_L,0);
is_lbat_int=KAL_TRUE;
}
static kal_uint32 charging_reset_watch_dog_timer(void *data)
{
kal_uint32 status = STATUS_OK;
pmic_set_register_value(PMIC_RG_CHRWDT_TD,0); // CHRWDT_TD, 4s
pmic_set_register_value(PMIC_RG_CHRWDT_WR,1); // CHRWDT_WR
pmic_set_register_value(PMIC_RG_CHRWDT_INT_EN,1); // CHRWDT_INT_EN
pmic_set_register_value(PMIC_RG_CHRWDT_EN,1); // CHRWDT_EN
pmic_set_register_value(PMIC_RG_CHRWDT_FLAG_WR,1); // CHRWDT_WR
return status;
}
void trigger_hw_ocv(void)
{
pmic_set_register_value(PMIC_STRUP_AUXADC_START_SEL,0x1);
//udelay(50);
pmic_set_register_value(PMIC_STRUP_AUXADC_START_SW,0x0);
//udelay(50);
pmic_set_register_value(PMIC_STRUP_AUXADC_START_SW,0x1);
while(pmic_get_register_value(PMIC_RG_ADC_RDY_WAKEUP_PCHR)==0)
{
bm_print(BM_LOG_FULL, "[trigger_hw_ocv] delay\n");
udelay(100);
}
}
static void spm_sodi_post_process(void)
{
pmic_set_register_value(PMIC_VSRAM_VOSEL_ON_LB,vsram_vosel_on_lb);
/* set PMIC WRAP table for normal power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_NORMAL);
}
void vibr_power_set(void)
{
#ifdef CUST_VIBR_VOL
struct vibrator_hw* hw = get_cust_vibrator_hw();
printk("[vibrator]vibr_init: vibrator set voltage = %d\n", hw->vib_vol);
pmic_set_register_value(PMIC_RG_VIBR_VOSEL,hw->vib_vol);
#endif
}
INT32 mtk_wcn_consys_hw_vcn28_ctrl(UINT32 enable)
{
if(enable){
/*in co-clock mode,need to turn on vcn28 when fm on*/
#if CONSYS_PMIC_CTRL_ENABLE
pmic_set_register_value(PMIC_VCN28_ON_CTRL,1);
#endif
WMT_PLAT_INFO_FUNC("turn on vcn28 for fm/gps usage in co-clock mode\n");
}else{
/*in co-clock mode,need to turn off vcn28 when fm off*/
#if CONSYS_PMIC_CTRL_ENABLE
pmic_set_register_value(PMIC_VCN28_ON_CTRL,0);
#endif
WMT_PLAT_INFO_FUNC("turn off vcn28 for fm/gps usage in co-clock mode\n");
}
return 0;
}
static void spm_sodi_pre_process(void)
{
/* set PMIC WRAP table for deepidle power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_DEEPIDLE);
vsram_vosel_on_lb = pmic_get_register_value(PMIC_VSRAM_VOSEL_ON_LB);
spm_write(SPM_PCM_RESERVE3,(pmic_get_register_value(PMIC_VSRAM_VOSEL_OFFSET)<<8)|pmic_get_register_value(PMIC_VSRAM_VOSEL_DELTA));//delta = 0v
pmic_set_register_value(PMIC_VSRAM_VOSEL_ON_LB,(vsram_vosel_on_lb&0xff80)|0x28);//0.85v
}
static void spm_dpidle_post_process(void)
{
/* //TODO
spm_i2c_control(I2C_CHANNEL, 0);
spm_write(0xF0001070 , g_bus_ctrl); //26:26 enable
*/
pmic_set_register_value(PMIC_VSRAM_VOSEL_ON_LB,vsram_vosel_on_lb);
/* set PMIC WRAP table for normal power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_NORMAL);
}
static ssize_t vibr_vtg_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
{
unsigned int val;
struct vibrator_hw* hw = mt_get_cust_vibrator_hw();
sscanf(buf, "%u", &val);
if(val>=MIN_VIBR && val <=MAX_VIBR) {
pmic_set_register_value(PMIC_RG_VIBR_VOSEL,val);
hw->vib_vol=val;
}
return count;
}
static kal_uint32 charging_get_battery_status(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint32 val = 0;
#if defined(CONFIG_POWER_EXT) || defined(CONFIG_MTK_FPGA)
*(kal_bool*)(data) = 0; // battery exist
battery_log(BAT_LOG_CRTI,"bat exist for evb\n");
#else
val=pmic_get_register_value(PMIC_BATON_TDET_EN);
battery_log(BAT_LOG_FULL,"[charging_get_battery_status] BATON_TDET_EN = %d\n", val);
if (val) {
pmic_set_register_value(PMIC_BATON_TDET_EN,1);
pmic_set_register_value(PMIC_RG_BATON_EN,1);
*(kal_bool*)(data) = pmic_get_register_value(PMIC_RGS_BATON_UNDET);
} else {
*(kal_bool*)(data) = KAL_FALSE;
}
#endif
return status;
}
static kal_uint32 charging_set_cv_voltage(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint16 register_value;
register_value = charging_parameter_to_value(VBAT_CV_VTH, GETARRAYNUM(VBAT_CV_VTH) ,*(kal_uint32 *)(data));
cv_voltage=VBAT_CV_VTH[register_value];
/*
#if 0
mt6325_upmu_set_rg_vbat_cv_vth(register_value);
#else
//PCB workaround
if(mt6325_upmu_get_swcid() == PMIC6325_E1_CID_CODE)
{
pmic_config_interface(0xEFE,0x0,0xF,1); // [4:1]: RG_VBAT_OV_VTH; Set charger OV=3.9V
pmic_config_interface(0xEF8,0x3,0x3F,0); // [5:0]: RG_VBAT_CV_VTH; Set charger CV=3.8V
battery_log(BAT_LOG_CRTI,"[charging_set_cv_voltage] set low CV by 6325 E1\n");
}
else
{
if(is_mt6311_exist())
{
if(mt6311_get_chip_id()==PMIC6311_E1_CID_CODE)
{
pmic_config_interface(0xEFE,0x0,0xF,1); // [4:1]: RG_VBAT_OV_VTH; Set charger OV=3.9V
pmic_config_interface(0xEF8,0x3,0x3F,0); // [5:0]: RG_VBAT_CV_VTH; Set charger CV=3.8V
battery_log(BAT_LOG_CRTI,"[charging_set_cv_voltage] set low CV by 6311 E1\n");
}
else
{
mt6325_upmu_set_rg_vbat_cv_vth(register_value);
}
}
else
{
mt6325_upmu_set_rg_vbat_cv_vth(register_value);
}
}
#endif
*/
pmic_set_register_value(PMIC_RG_VBAT_CV_VTH,register_value);
battery_log(BAT_LOG_CRTI,"[charging_set_cv_voltage] [0x%x]=0x%x, [0x%x]=0x%x\n",
0xf54, upmu_get_reg_value(0xf54),
0xf4e, upmu_get_reg_value(0xf4e)
);
return status;
}
INT32 mtk_wcn_consys_hw_bt_paldo_ctrl(UINT32 enable)
{
if (enable) {
/*do BT PMIC on,depenency PMIC API ready */
/*switch BT PALDO control from SW mode to HW mode:0x416[5]-->0x1 */
#if CONSYS_PMIC_CTRL_ENABLE
/* VOL_DEFAULT, VOL_3300, VOL_3400, VOL_3500, VOL_3600 */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN33_BT, VOL_3300, "wcn_drv");
#else
if (reg_VCN33_BT) {
regulator_set_voltage(reg_VCN33_BT, VOL_3300, VOL_3300);
if (regulator_enable(reg_VCN33_BT))
WMT_PLAT_ERR_FUNC("WMT do BT PMIC on fail!\n");
}
#endif
pmic_set_register_value(PMIC_RG_VCN33_ON_CTRL_BT, 1);
#endif
WMT_PLAT_INFO_FUNC("WMT do BT PMIC on\n");
} else {
/*do BT PMIC off */
/*switch BT PALDO control from HW mode to SW mode:0x416[5]-->0x0 */
#if CONSYS_PMIC_CTRL_ENABLE
pmic_set_register_value(PMIC_RG_VCN33_ON_CTRL_BT, 0);
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN33_BT, "wcn_drv");
#else
if (reg_VCN33_BT)
regulator_disable(reg_VCN33_BT);
#endif
#endif
WMT_PLAT_INFO_FUNC("WMT do BT PMIC off\n");
}
return 0;
}
static kal_uint32 charging_set_current(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint32 set_chr_current;
kal_uint32 array_size;
kal_uint32 register_value;
array_size = GETARRAYNUM(CS_VTH);
set_chr_current = bmt_find_closest_level(CS_VTH, array_size, *(kal_uint32 *)data);
register_value = charging_parameter_to_value(CS_VTH, array_size ,set_chr_current);
pmic_set_register_value(PMIC_RG_CS_VTH,register_value);
return status;
}
static kal_uint32 charging_set_hv_threshold(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint32 set_hv_voltage;
kal_uint32 array_size;
kal_uint16 register_value;
kal_uint32 voltage = *(kal_uint32*)(data);
array_size = GETARRAYNUM(VCDT_HV_VTH);
set_hv_voltage = bmt_find_closest_level(VCDT_HV_VTH, array_size, voltage);
register_value = charging_parameter_to_value(VCDT_HV_VTH, array_size ,set_hv_voltage);
pmic_set_register_value(PMIC_RG_VCDT_HV_VTH,register_value);
return status;
}
static void spm_dpidle_pre_process(void)
{
/* //TODO
spm_i2c_control(I2C_CHANNEL, 1);//D1,D2 no ext bulk
g_bus_ctrl=spm_read(0xF0001070);
spm_write(0xF0001070 , g_bus_ctrl | (1 << 21)); //bus dcm disable
g_sys_ck_sel = spm_read(0xF0001108);
//spm_write(0xF0001108 , g_sys_ck_sel &~ (1<<1) );
spm_write(0xF0001108 , 0x0);
spm_write(0xF0000204 , spm_read(0xF0000204) | (1 << 0)); // BUS 26MHz enable
*/
/* set PMIC WRAP table for deepidle power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_DEEPIDLE);
vsram_vosel_on_lb = pmic_get_register_value(PMIC_VSRAM_VOSEL_ON_LB);
spm_write(SPM_PCM_RESERVE3,(pmic_get_register_value(PMIC_VSRAM_VOSEL_OFFSET)<<8)|pmic_get_register_value(PMIC_VSRAM_VOSEL_DELTA));//delta = 0v
pmic_set_register_value(PMIC_VSRAM_VOSEL_ON_LB,(vsram_vosel_on_lb&0xff80)|0x28);//0.85v
}
static kal_int32 get_refresh_hw_ocv(void *data)
{
#if defined(CONFIG_MTK_HAFG_20)
kal_int32 hwocv1,hwocv2;
pmic_turn_on_clock(1);
udelay(30);
hwocv1=get_hw_ocv();
trigger_hw_ocv();
hwocv2=get_hw_ocv();
bm_print(BM_LOG_CRTI, "[bat_get_zcv]%d %d\n",hwocv1,hwocv2);
pmic_set_register_value(PMIC_STRUP_AUXADC_START_SEL,0x0);
pmic_turn_on_clock(0);
*(kal_int32*)(data)=hwocv2;
#else
*(kal_int32*)(data)=0;
#endif
return STATUS_OK;
}
static kal_int32 fgauge_set_low_battery_interrupt(void *data)
{
#if defined(CONFIG_MTK_HAFG_20)
kal_uint32 voltage=*(kal_uint32*)(data);
kal_uint32 rawdata;
static int eint_init=0;
if(eint_init==0)
{
pmic_register_interrupt_callback(2,fg_bat_l_int_handler);
eint_init=1;
}
is_lbat_int=KAL_FALSE;
pmic_turn_on_clock(KAL_TRUE);
rawdata=voltage*4096/1800/4;
bm_print(BM_LOG_CRTI, "[fgauge_set_low_battery_interrupt] Battery voltage %d %d\n",rawdata,voltage);
// 0:set interrupt
pmic_set_register_value(PMIC_RG_INT_EN_BAT_L,1);
// 1.setup min voltage threshold 3.4v
pmic_set_register_value(PMIC_RG_LBAT_VOLT_MIN,rawdata);
// 2.setup detection period
pmic_set_register_value(PMIC_RG_LBAT_DET_PRD_19_16,0x0);
pmic_set_register_value(PMIC_RG_LBAT_DET_PRD_15_0,0x12f);
// 3.setup max/min debounce time
pmic_set_register_value(PMIC_RG_LBAT_DEBT_MIN,0x5a);//15mins
// 4.turn on IRQ
pmic_set_register_value(PMIC_RG_LBAT_IRQ_EN_MIN,0x1);
// 5. turn on LowBattery Detection
pmic_set_register_value(PMIC_RG_LBAT_EN_MIN,1);
#endif
return STATUS_OK;
}
static kal_uint32 charging_set_ta_current_pattern(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint32 increase = *(kal_uint32*)(data);
kal_uint32 debug_val = 0;
U8 count = 0;
pmic_set_register_value(PMIC_RG_CS_VTH,0xc);
if(increase == KAL_TRUE) {
/* Set communication mode high/low current */
pmic_set_register_value(PMIC_RG_CM_CS_VTHH,0xa);/* 650mA */
pmic_set_register_value(PMIC_RG_CM_CS_VTHL,0xf);/* 70mA */
/* Set CM_VINC high period time (HPRD1, HPRD2) */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD1,9);/* 100ms */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD2,9);/* 100ms */
/* Set CM_VINC high period time (HPRD3, HPRD4) */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD3,29);/* 300ms */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD4,29);/* 300ms */
/* Set CM_VINC high period time (HPRD5, HPRD6) */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD5,29);/* 300ms */
pmic_set_register_value(PMIC_RG_CM_VINC_HPRD6,49);/* 500ms */
/* Enable CM_VINC interrupt */
//mt6325_upmu_set_rg_int_en_pchr_cm_vinc(0x1);
pmic_set_register_value(PMIC_RG_INT_EN_PCHR_CM_VINC,1);
/* Select PCHR debug flag to monitor abnormal abort */
pmic_set_register_value(PMIC_RG_PCHR_FLAG_SEL,0x2e);
/* Enable PCHR debug flag */
pmic_set_register_value(PMIC_RG_PCHR_FLAG_EN,0x1);
/* Trigger CM VINC mode */
pmic_set_register_value(PMIC_RG_CM_VINC_TRIG,0x1);
/* wait for interrupt */
while(pmic_get_register_value(PMIC_PCHR_CM_VINC_STATUS) != 1) {
msleep(50);
count++;
if (count > 42)
break;
}
} else {
/* Set communication mode high/low current */
pmic_set_register_value(PMIC_RG_CM_CS_VTHH,0xa);/* 650mA */
pmic_set_register_value(PMIC_RG_CM_CS_VTHL,0xf);/* 70mA */
/* Set CM_VINC high period time (HPRD1, HPRD2) */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD1,29);/* 100ms */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD2,29);/* 100ms */
/* Set CM_VINC high period time (HPRD3, HPRD4) */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD3,29);/* 300ms */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD4,9);/* 300ms */
/* Set CM_VINC high period time (HPRD5, HPRD6) */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD5,9);/* 300ms */
pmic_set_register_value(PMIC_RG_CM_VDEC_HPRD6,49);/* 500ms */
/* Enable CM_VINC interrupt */
//mt6325_upmu_set_rg_int_en_pchr_cm_vinc(0x1);
pmic_set_register_value(PMIC_RG_INT_EN_PCHR_CM_VDEC,1);
/* Select PCHR debug flag to monitor abnormal abort */
pmic_set_register_value(PMIC_RG_PCHR_FLAG_SEL,0x2e);
/* Enable PCHR debug flag */
pmic_set_register_value(PMIC_RG_PCHR_FLAG_EN,0x1);
/* Trigger CM VINC mode */
pmic_set_register_value(PMIC_RG_CM_VDEC_TRIG,0x1);
/* wait for interrupt */
while(pmic_get_register_value(PMIC_PCHR_CM_VDEC_STATUS) != 1) {
msleep(50);
count++;
if (count > 42)
break;
}
}
debug_val = pmic_get_register_value(PMIC_RGS_PCHR_FLAG_OUT);
battery_log(BAT_LOG_CRTI, "[charging_set_ta_current_pattern] debug_val=0x%x cnt=%d\n", debug_val,count);
if (count > 10 || debug_val != 0) {
status = STATUS_FAIL;
}
return status;
}
static kal_uint32 charging_enable(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint32 enable = *(kal_uint32*)(data);
if(KAL_TRUE == enable)
{
pmic_set_register_value(PMIC_RG_CSDAC_DLY,4);// CSDAC_DLY
pmic_set_register_value(PMIC_RG_CSDAC_STP,1);// CSDAC_STP
pmic_set_register_value(PMIC_RG_CSDAC_STP_INC,1);// CSDAC_STP_INC
pmic_set_register_value(PMIC_RG_CSDAC_STP_DEC,2);// CSDAC_STP_DEC
pmic_set_register_value(PMIC_RG_CS_EN,1);// CS_EN, check me
pmic_set_register_value(PMIC_RG_HWCV_EN,1);
pmic_set_register_value(PMIC_RG_VBAT_CV_EN,1);// CV_EN
pmic_set_register_value(PMIC_RG_CSDAC_EN,1);// CSDAC_EN
pmic_set_register_value(PMIC_RG_PCHR_FLAG_EN,1);// enable debug falg output
pmic_set_register_value(PMIC_RG_CHR_EN,1);// CHR_EN
pmic_set_register_value(PMIC_RG_CSDAC_MODE,1);//CSDAC_MODE
pmic_set_register_value(PMIC_RG_CSDAC_EN,1);// CSDAC_EN
if(Enable_BATDRV_LOG == BAT_LOG_FULL)
charging_dump_register(NULL);
}
else
{
pmic_set_register_value(PMIC_RG_CHRWDT_INT_EN,0);// CHRWDT_INT_EN
pmic_set_register_value(PMIC_RG_CHRWDT_EN,0);// CHRWDT_EN
pmic_set_register_value(PMIC_RG_CHRWDT_FLAG_WR,0);// CHRWDT_FLAG
pmic_set_register_value(PMIC_RG_CSDAC_EN,0);// CSDAC_EN
pmic_set_register_value(PMIC_RG_CHR_EN,0);// CHR_EN
pmic_set_register_value(PMIC_RG_HWCV_EN,0);// RG_HWCV_EN
}
return status;
}
static kal_uint32 charging_hw_init(void *data)
{
kal_uint32 status = STATUS_OK;
pmic_set_register_value(PMIC_RG_CHRWDT_TD,0); // CHRWDT_TD, 4s
pmic_set_register_value(PMIC_RG_CHRWDT_INT_EN,1); // CHRWDT_INT_EN
pmic_set_register_value(PMIC_RG_CHRWDT_EN,1); // CHRWDT_EN
pmic_set_register_value(PMIC_RG_CHRWDT_WR,1);// CHRWDT_WR
pmic_set_register_value(PMIC_RG_VCDT_MODE,0);//VCDT_MODE
pmic_set_register_value(PMIC_RG_VCDT_HV_EN,1);//VCDT_HV_EN
pmic_set_register_value(PMIC_RG_USBDL_SET,0);//force leave USBDL mode
pmic_set_register_value(PMIC_RG_USBDL_RST,1);//force leave USBDL mode
pmic_set_register_value(PMIC_RG_BC11_BB_CTRL,1);//BC11_BB_CTRL
pmic_set_register_value(PMIC_RG_BC11_RST,1);//BC11_RST
pmic_set_register_value(PMIC_RG_CSDAC_MODE,1);//CSDAC_MODE
pmic_set_register_value(PMIC_RG_VBAT_OV_EN,1);//VBAT_OV_EN
#ifdef HIGH_BATTERY_VOLTAGE_SUPPORT
pmic_set_register_value(PMIC_RG_VBAT_OV_VTH,3);//VBAT_OV_VTH, 4.4V,
#else
pmic_set_register_value(PMIC_RG_VBAT_OV_VTH,1);//VBAT_OV_VTH, 4.3V,
#endif
pmic_set_register_value(PMIC_RG_BATON_EN,1);//BATON_EN
//Tim, for TBAT
pmic_set_register_value(PMIC_RG_BATON_HT_EN,0);//BATON_HT_EN
pmic_set_register_value(PMIC_RG_ULC_DET_EN,1);// RG_ULC_DET_EN=1
pmic_set_register_value(PMIC_RG_LOW_ICH_DB,1);// RG_LOW_ICH_DB=000001'b
#if defined(CONFIG_MTK_PUMP_EXPRESS_SUPPORT)
pmic_set_register_value(PMIC_RG_CSDAC_DLY,0);// CSDAC_DLY
pmic_set_register_value(PMIC_RG_CSDAC_STP,1);// CSDAC_STP
pmic_set_register_value(PMIC_RG_CSDAC_STP_INC,1);// CSDAC_STP_INC
pmic_set_register_value(PMIC_RG_CSDAC_STP_DEC,7);// CSDAC_STP_DEC
pmic_set_register_value(PMIC_RG_CS_EN,1);// CS_EN
pmic_set_register_value(PMIC_RG_HWCV_EN,1);
pmic_set_register_value(PMIC_RG_VBAT_CV_EN,1);// CV_EN
pmic_set_register_value(PMIC_RG_CHR_EN,1);// CHR_EN
pmic_set_register_value(PMIC_RG_CSDAC_EN,1);// CSDAC_EN
#endif
return status;
}
void vibr_Disable_HW(void)
{
pmic_set_register_value(PMIC_RG_VIBR_EN,0); //[bit 1]: VIBR_EN, 1=enable
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on, UINT32 co_clock_type)
{
INT32 iRet = -1;
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n", on);
if (on) {
WMT_PLAT_DBG_FUNC("++\n");
/*step1.PMIC ctrl*/
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol */
/*1.AP power on VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8 */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
/* VOL_DEFAULT, VOL_1200, VOL_1300, VOL_1500, VOL_1800... */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN18, VOL_1800, "wcn_drv");
#else
if (reg_VCN18) {
regulator_set_voltage(reg_VCN18, VOL_1800, VOL_1800);
if (regulator_enable(reg_VCN18))
WMT_PLAT_ERR_FUNC("enable VCN18 fail\n");
else
WMT_PLAT_DBG_FUNC("enable VCN18 ok\n");
}
#endif
udelay(150);
if (co_clock_type) {
/*step0,clk buf ctrl */
WMT_PLAT_INFO_FUNC("co clock type(%d),turn on clk buf\n", co_clock_type);
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 1);
#endif
/*if co-clock mode: */
/*2.set VCN28 to SW control mode (with PMIC_WRAP API) */
/*turn on VCN28 LDO only when FMSYS is activated" */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
} else {
/*if NOT co-clock: */
/*2.1.switch VCN28 to HW control mode (with PMIC_WRAP API) */
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 1);
/*2.2.turn on VCN28 LDO (with PMIC_WRAP API)" */
/*fix vcn28 not balance warning */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerOn(MT6328_POWER_LDO_VCN28, VOL_2800, "wcn_drv");
#else
if (reg_VCN28) {
regulator_set_voltage(reg_VCN28, VOL_2800, VOL_2800);
if (regulator_enable(reg_VCN28))
WMT_PLAT_ERR_FUNC("enable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("enable VCN_2V8 ok\n");
}
#endif
}
#endif
/*step2.MTCMOS ctrl*/
#ifdef CONFIG_OF /*use DT */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE((conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET),
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) |
CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE((conn_reg.spm_base + CONSYS_PWRON_CONFG_EN_OFFSET), CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner. */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT &
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) &
~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until chipid is returned 0x18070008 */
while (retry-- > 0) {
consysHwChipId = CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_CHIP_ID_OFFSET);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
WMT_PLAT_ERR_FUNC("Read CONSYS chipId(0x%08x)", consysHwChipId);
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET));
WMT_PLAT_ERR_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET,
CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET) |
CONSYS_MCU_CFG_ACR_MBIST_BIT);
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88 (key)" */
CONSYS_REG_WRITE(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET,
(CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) &
~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);
#else /*use HADRCODE, maybe no use.. */
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) | CONSYS_CPU_SW_RST_BIT |
CONSYS_CPU_SW_RST_CTRL_KEY));
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
iRet = conn_power_on(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_on ok\n");
#else
iRet = clk_prepare_enable(clk_scp_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_scp_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("clk_prepare_enable(clk_scp_conn_main) ok\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG)))
NULL;
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG)))
NULL;
/*9.release connsys ISO, conn_top1_iso_en=0 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_RST_BIT);
/*disable AXI BUS protect */
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN, CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) & ~CONSYS_PROT_MASK);
while (CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK)
NULL;
#endif
/*11.26M is ready now, delay 10us for mem_pd de-assert */
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++?? */
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
enable_clock(MT_CG_INFRA_CONNMCU_BUS, "WCN_MOD");
WMT_PLAT_DBG_FUNC("enable MT_CG_INFRA_CONNMCU_BUS CLK\n");
#else
iRet = clk_prepare_enable(clk_infra_conn_main);
if (iRet)
WMT_PLAT_ERR_FUNC("clk_prepare_enable(clk_infra_conn_main) fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("[CCF]enable clk_infra_conn_main\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
/*12.poll CONNSYS CHIP ID until 6752 is returned 0x18070008 32'h6752 */
while (retry-- > 0) {
WMT_PLAT_DBG_FUNC("CONSYS_CHIP_ID_REG(0x%08x)", CONSYS_REG_READ(CONSYS_CHIP_ID_REG));
consysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if ((consysHwChipId == 0x0321) || (consysHwChipId == 0x0335) || (consysHwChipId == 0x0337)) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry, consysHwChipId);
break;
}
msleep(20);
}
if ((0 == retry) || (0 == consysHwChipId)) {
WMT_PLAT_ERR_FUNC("Maybe has a consys power on issue,(0x%08x)\n", consysHwChipId);
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 */
/*
*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST
*(default write "1") ACR 0x18070110[18] 1'b1
*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)
*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz)
*inclulding low CPU frequence
*/
CONSYS_REG_WRITE(CONSYS_MCU_CFG_ACR_REG,
CONSYS_REG_READ(CONSYS_MCU_CFG_ACR_REG) | CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*update ANA_WBG(AFE) CR. AFE setting file: AP Offset = 0x180B2000 */
#if 0
/*15.default no need,update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01, CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02, CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01, CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset 0x10007018 "[12]=1'b0 [31:24] =8'h88(key)" */
CONSYS_REG_WRITE(CONSYS_CPU_SW_RST_REG,
(CONSYS_REG_READ(CONSYS_CPU_SW_RST_REG) & ~CONSYS_CPU_SW_RST_BIT) |
CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
msleep(20); /* msleep < 20ms can sleep for up to 20ms */
} else {
#ifdef CONFIG_OF
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
WMT_PLAT_DBG_FUNC("[CCF] clk_disable_unprepare(clk_infra_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET,
CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) |
CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) &
CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |
CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET,
CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#else
#if CONSYS_PWR_ON_OFF_API_AVAILABLE
#if CONSYS_AHB_CLK_MAGEMENT
#if defined(CONFIG_MTK_CLKMGR)
disable_clock(MT_CG_INFRA_CONNMCU_BUS, "WMT_MOD");
#else
clk_disable_unprepare(clk_infra_conn_main);
#endif /* defined(CONFIG_MTK_CLKMGR) */
#endif
#if defined(CONFIG_MTK_CLKMGR)
/*power off connsys by API: conn_power_off() */
iRet = conn_power_off(); /* consult clkmgr owner */
if (iRet)
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n", iRet);
WMT_PLAT_DBG_FUNC("conn_power_off ok\n");
#else
clk_disable_unprepare(clk_scp_conn_main);
WMT_PLAT_DBG_FUNC("clk_disable_unprepare(clk_scp_conn_main) calling\n");
#endif /* defined(CONFIG_MTK_CLKMGR) */
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(CONSYS_TOPAXI_PROT_EN,
CONSYS_REG_READ(CONSYS_TOPAXI_PROT_EN) | CONSYS_PROT_MASK);
while ((CONSYS_REG_READ(CONSYS_TOPAXI_PROT_STA1) & CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
count++;
if (count > 1000)
break;
}
}
/*release connsys ISO, conn_top1_iso_en=1 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) & ~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG,
CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) | CONSYS_CLK_CTRL_BIT);
/*wait 1us */
udelay(1);
/*write conn_top1_pwr_on=0, power off conn_top1 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(CONSYS_TOP1_PWR_CTRL_REG, CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG) &
~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#endif
#if CONSYS_PMIC_CTRL_ENABLE
if (co_clock_type) {
/*VCN28 has been turned off by GPS OR FM */
#if CONSYS_CLOCK_BUF_CTRL
clk_buf_ctrl(CLK_BUF_CONN, 0);
#endif
} else {
pmic_set_register_value(PMIC_RG_VCN28_ON_CTRL, 0);
/*turn off VCN28 LDO (with PMIC_WRAP API)" */
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN28, "wcn_drv");
#else
if (reg_VCN28) {
if (regulator_disable(reg_VCN28))
WMT_PLAT_ERR_FUNC("disable VCN_2V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_2V8 ok\n");
}
#endif
}
/*AP power off MT6625L VCN_1V8 LDO */
pmic_set_register_value(PMIC_RG_VCN18_ON_CTRL, 0);
#if defined(CONFIG_MTK_PMIC_LEGACY)
hwPowerDown(MT6328_POWER_LDO_VCN18, "wcn_drv");
#else
if (reg_VCN18) {
if (regulator_disable(reg_VCN18))
WMT_PLAT_ERR_FUNC("disable VCN_1V8 fail!\n");
else
WMT_PLAT_DBG_FUNC("disable VCN_1V8 ok\n");
}
#endif
#endif
}
WMT_PLAT_WARN_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n", on);
return 0;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{
UINT32 retry = 10;
UINT32 consysHwChipId = 0;
#if PWR_ON_OFF_API_AVALIABLE
INT32 iRet = -1;
#endif
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
WMT_PLAT_DBG_FUNC("CONSYS_EMI_MAPPING dump before power on/off(0x%08x)\n",CONSYS_REG_READ(CONSYS_EMI_MAPPING));
if(on)
{
#if CONSYS_PMIC_CTRL_ENABLE
if(mtk_wcn_regulator_get()){
WMT_PLAT_ERR_FUNC("regulator_get fail\n");
return -1;
}
/*need PMIC driver provide new API protocol */
/*1.AP power on MT6350 VCN_1V8 LDO (with PMIC_WRAP API) VCN_1V8 0x0510[1] "1'b0 0x0512[14]" 1'b1"*/
pmic_set_register_value(PMIC_VCN_1V8_ON_CTRL,0);
if(reg_V18){
regulator_enable(reg_V18);
WMT_PLAT_INFO_FUNC("wmt_dev enable VCN_1V8\n");
}
udelay(300);
if(co_clock_en)
{
/*if co-clock mode:*/
/*2.set RF XO BUF source from CellularRF DA_XOBUF_SEL 0x1000513C[7:6] 2'b10*/
CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) & ~(0x1 << 6) );
CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) | (0x1 << 7) );
WMT_PLAT_INFO_FUNC("co_clock mode reg dump:XO BUFFER(0x%08x)\n",CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET));
}
else
{
/*if NOT co-clock:*/
/*2.1 switch VCN28 to HW control mode (with PMIC_WRAP API) RG_VCN28_ON_CTRL 0x041C[14] 1'b1*/
pmic_set_register_value(PMIC_VCN28_ON_CTRL,1);
/*2.2 turn on VCN28 LDO (with PMIC_WRAP API) DA_XOBUF_SEL 0x1000513C[7:6]" " 2'b11"*/
CONSYS_REG_WRITE((conn_reg.da_xobuf_base+ CONSYS_DA_XOBUF_OFFSET), CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET) | ((0x1 << 7) |(0x1 << 6)));
WMT_PLAT_INFO_FUNC("NOT co_clock mode reg dump:XO BUFFER(0x%08x)\n",CONSYS_REG_READ(conn_reg.da_xobuf_base + CONSYS_DA_XOBUF_OFFSET));
udelay(300);
}
#endif
/*3.assert CONNSYS CPU SW reset 0x10007018 "[12]=1'b1 [31:24]=8'h88 (key)"*/
CONSYS_REG_WRITE((conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET), CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) | CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_CPU_SW_RST_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET));
/*turn on top clock gating enable TOP_CLKCG_CLR 0x10000084[26] 1'b1 */
// CONSYS_REG_WRITE((conn_reg.topckgen_base + CONSYS_TOP_CLKCG_CLR_OFFSET), CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOP_CLKCG_CLR_OFFSET) | CONSYS_TOP_CLKCG_BIT);
/*turn on SPM clock gating enable PWRON_CONFG_EN 0x10006000 32'h0b160001 */
CONSYS_REG_WRITE((conn_reg.spm_base + CONSYS_PWRON_CONFG_EN_OFFSET), CONSYS_PWRON_CONFG_EN_VALUE);
#if PWR_ON_OFF_API_AVALIABLE
iRet = conn_power_on(); //consult clkmgr owner.
if(iRet)
{
WMT_PLAT_ERR_FUNC("conn_power_on fail(%d)\n",iRet);
}else
{
WMT_PLAT_INFO_FUNC("conn_power_on ok\n");
}
#else
/*2.write conn_top1_pwr_on=1, power on conn_top1 (MT6572 with the same addr) conn_spm_pwr_on 0x10006280 [2] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ON_BIT);
/*3.read conn_top1_pwr_on_ack =1, power on ack ready (MT6572 with the same addr) pwr_conn_ack 0x1000660C [1] */
while (0 == (CONSYS_PWR_ON_ACK_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET)));
/*4.write conn_top1_mem_PD=0, power on MCU memory (MT6572 with the same addr) sram_conn_pd 0x10006280 [3] 1'b1 */
//CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SRAM_CONN_PD_BIT);
/*5.write conn_top1_pwr_on_s=1, power on conn_top1 (MT6572 with the same addr) conn_spm_pwr_on_s 0x10006280 [3] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ON_S_BIT);
/*6.write conn_clk_dis=0, enable connsys clock (MT6572 with the same addr) conn_clk_dis 0x10006280 [4] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_CLK_CTRL_BIT);
/*7.wait 1us */
udelay(1);
/*8.read conn_top1_pwr_on_ack_s =1, power on ack ready (MT6572 with the same addr) pwr_conn_ack_s 0x10006610 [1] */
while (0 == (CONSYS_PWR_CONN_ACK_S_BIT & CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET)));
/*9.release connsys ISO, conn_top1_iso_en=0 (MT6572 with the same addr) conn_spm_pwr_iso 0x10006280 [1] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SPM_PWR_ISO_S_BIT);
/*10.release SW reset of connsys, conn_ap_sw_rst_b=1 (MT6572 with the same addr) conn_spm_pwr_rst_b 0x10006280[0] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_RST_BIT);
/*Disable AXI bus protect 0x10001220[8] 0x10001220[9] 1'b0 1'b0*/
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET, CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) & ~CONSYS_PROT_MASK);
// while (CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK) {
// }
#endif
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_OFFSET));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_PWR_CONN_ACK_S_OFFSET));
WMT_PLAT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET));
/*11.26M is ready now, delay 10us for mem_pd de-assert*/
udelay(10);
/*enable AP bus clock : connmcu_bus_pd API: enable_clock() ++??*/
/*12.poll CONNSYS CHIP ID until 6580 is returned 0x18070008 32'h6580 */
while (retry-- > 0)
{
consysHwChipId = CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_CHIP_ID_OFFSET);
if(consysHwChipId == 0x6580) {
WMT_PLAT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,consysHwChipId);
break;
} else {
WMT_PLAT_INFO_FUNC("Read CONSYS chipId(0x%08x)",consysHwChipId);
}
msleep(20);
}
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed 0x18070114 "[3:0] ROM DELSEL [7:4] RAM4Kx32 DELSEL" ??*/
/*14.write 1 to conn_mcu_confg ACR[1] if real speed MBIST (default write "1") ACR 0x18070110[18] 1'b1*/
/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
CONSYS_REG_WRITE(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET, CONSYS_REG_READ(conn_reg.mcu_base + CONSYS_MCU_CFG_ACR_OFFSET) | CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*"update ANA_WBG(AFE) CR. AFE setting file: MT6752_AFE_SW_patch_REG_xxxx.xlsx" AP Offset = 0x180B2000" AP Offset = 0x180B2000*/
#if 0
/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
#endif
/*16.deassert CONNSYS CPU SW reset (need to check MT6752) 0x10007018 "[12]=1'b0 [31:24]=8'h88 (key)"*/
CONSYS_REG_WRITE(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET,
(CONSYS_REG_READ(conn_reg.ap_rgu_base + CONSYS_CPU_SW_RST_OFFSET) & ~CONSYS_CPU_SW_RST_BIT) | CONSYS_CPU_SW_RST_CTRL_KEY);
msleep(5);
}else{
#if PWR_ON_OFF_API_AVALIABLE
WMT_PLAT_INFO_FUNC("\n conn_power_off begin\n");
/*power off connsys by API (MT6582, MT6572 are different) API: conn_power_off() */
iRet = conn_power_off();//consult clkmgr owner
WMT_PLAT_INFO_FUNC("\n conn_power_off end\n");
if(iRet)
{
WMT_PLAT_ERR_FUNC("conn_power_off fail(%d)\n",iRet);
}else
{
WMT_PLAT_INFO_FUNC("conn_power_off ok\n");
}
#else
{
INT32 count = 0;
CONSYS_REG_WRITE(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET, CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_EN_OFFSET) | CONSYS_PROT_MASK);
//while ((CONSYS_REG_READ(conn_reg.topckgen_base + CONSYS_TOPAXI_PROT_STA1_OFFSET) & CONSYS_PROT_MASK) != CONSYS_PROT_MASK) {
// count++;
// if(count>1000)
// break;
//}
}
/*release connsys ISO, conn_top1_iso_en=1 (MT6572 with the same addr) 0x10006280 [1] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) | CONSYS_SPM_PWR_ISO_S_BIT);
/*assert SW reset of connsys, conn_ap_sw_rst_b=0 (MT6572 with the same addr) 0x10006280[0] 1'b0 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SPM_PWR_RST_BIT);
/*write conn_clk_dis=1, disable connsys clock (MT6572 with the same addr) conn_clk_dis 0x10006280 [4] 1'b1 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) |CONSYS_CLK_CTRL_BIT);
/*DA_WBG_EN_XBUF=0 */
/*wait 1us */
udelay(1);
/*write conn_top1_mem_PD=1, power off MCU memory (MT6572 with the same addr) 0x10006280 [8] 1'b0 */
//CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~CONSYS_SRAM_CONN_PD_BIT);
/*write conn_top1_pwr_on=0, power off conn_top1 (MT6572 with the same addr) 0x10006280 [3:2] 2'b00 */
CONSYS_REG_WRITE(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET, CONSYS_REG_READ(conn_reg.spm_base + CONSYS_TOP1_PWR_CTRL_OFFSET) & ~(CONSYS_SPM_PWR_ON_BIT | CONSYS_SPM_PWR_ON_S_BIT));
#endif
#if CONSYS_PMIC_CTRL_ENABLE
/*set VCN_28 to SW control mode (with PMIC_WRAP API) "1. VCN28_ON_CTRL "0x041C[14] 1'b0*/
//mt6325_upmu_set_rg_vcn28_on_ctrl(0);
/*turn off VCN28 LDO (with PMIC_WRAP API)" 2. RG_VCN28_EN" 0x041C[12]" 1'b0*/
//hwPowerDown(MT6325_POWER_LDO_VCN28, "wcn_drv");
/*AP power off MT6323 VCN_1V8 LDO (with PMIC_WRAP API) RG_VCN18_ON_CTRL "0x0510[1] "1'b0 RG_VCN18_EN" 0x0512[14]" 1'b0"*/
pmic_set_register_value(PMIC_VCN_1V8_ON_CTRL,0);
if(reg_V18){
regulator_disable(reg_V18);
WMT_PLAT_INFO_FUNC("wmt_dev disable VCN_1V8\n");
}
#endif
}
WMT_PLAT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
return 0;
}
