static void f81865f_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
(dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
pnp_exit_conf_state(dev);
}
static void pc87309_enable_serial(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
void pc87366_enable_serial(pnp_devfn_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
void sch4037_early_init(unsigned port)
{
pnp_devfn_t dev;
dev = PNP_DEV(port, SMSCSUPERIO_SP1);
pnp_enter_conf_state(dev);
/* Auto power management */
pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */
pnp_write_config(dev, 0x23, 0);
/* Enable SMSC UART 0 */
dev = PNP_DEV(port, SMSCSUPERIO_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4);
/* Enabled High speed, disabled MIDI support. */
pnp_write_config(dev, 0xF0, 0x02);
pnp_set_enable(dev, 1);
/* Enable keyboard */
dev = PNP_DEV(port, SCH4037_KBC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */
pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
void it8716f_enable_dev(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
static void init(struct device *dev)
{
u8 reg8;
if (!dev->enabled)
return;
switch(dev->path.pnp.device) {
case PC97307_KBCK:
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); /* Disable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */
pnp_set_enable(dev, 1); /* Enable keyboard. */
pc_keyboard_init();
break;
case PC97307_FDC:
/* Set up floppy in PS/2 mode. */
outb(0x09, SIO_CONFIG_RA);
reg8 = inb(SIO_CONFIG_RD);
reg8 = (reg8 & 0x3F) | 0x40;
outb(reg8, SIO_CONFIG_RD);
outb(reg8, SIO_CONFIG_RD); /* Have to write twice to change! */
break;
default:
break;
}
}
static void pc8374_enable_dev(pnp_devfn_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
if (iobase)
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
/*
* Function: lpc47b272_enable_serial
* Parameters: dev - high 8 bits = Super I/O port,
* low 8 bits = logical device number (per lpc47b272.h)
* iobase - processor I/O port address to assign to this serial device
* Return Value: bool
* Description: Configure the base I/O port of the specified serial device
* and enable the serial device.
*/
static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
void w83627hf_enable_serial(device_t dev, unsigned iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
static void disable_sio_watchdog(device_t dev)
{
#if 0
/* FIXME move me somewhere more appropriate */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1);
pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
/* disable the sio watchdog */
outb(0, NSC_WDBASE + 0);
pnp_set_enable(dev, 0);
#endif
}
static void init(device_t dev)
{
struct superio_nsc_pc97317_config *conf;
struct resource *res0, *res1;
if (!dev->enabled) {
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case PC97317_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case PC97317_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case PC97317_KBCK:
/* Enable keyboard */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); /* Disable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 Mhz */
pnp_set_enable(dev, 1); /* Enable keyboard */
res0 = find_resource(dev, PNP_IDX_IO0);
res1 = find_resource(dev, PNP_IDX_IO1);
pc_keyboard_init(&conf->keyboard);
break;
#if 0
case PC97317_FDC:
{
unsigned reg;
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
break;
}
#endif
default:
break;
}
}
static void superio_init(void)
{
/* Enter the configuration state. */
pnp_enter_ext_func_mode(PNP_PORT);
/* COMA */
pnp_set_logical_device(PNP_PORT, 2);
pnp_set_enable(PNP_PORT, 0);
pnp_set_iobase0(PNP_PORT, CONFIG_SERIAL_PORT);
pnp_set_irq0(PNP_PORT, 4);
pnp_set_enable(PNP_PORT, 1);
/* Exit the configuration state. */
pnp_exit_ext_func_mode(PNP_PORT);
}
static void superio_init(void)
{
/* Enter the configuration state. */
pnp_enter_ext_func_mode_alt(0x2e);
/* COMA */
pnp_set_logical_device(0x2e, 4);
pnp_set_enable(0x2e, 0);
pnp_set_iobase0(0x2e, 0x3f8);
pnp_set_irq0(0x2e, 4);
pnp_set_enable(0x2e, 1);
/* Exit the configuration state. */
pnp_exit_ext_func_mode(0x2e);
}
static void it8712f_pnp_enable(device_t dev)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, !!dev->enabled);
pnp_exit_ext_func_mode(dev);
}
/**
* If so configured, enable the specified device, otherwise
* explicitly disable it.
*
* @param dev The device to use.
*/
static void smsc_pnp_enable(device_t dev)
{
smsc_pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, !!dev->enabled);
smsc_pnp_exit_conf_state(dev);
}
static void lpc47m10x_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, !!dev->enabled);
pnp_exit_conf_state(dev);
}
static void superio_init(void)
{
pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT);
/* Disable the watchdog. */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7);
pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00);
/* Enable the serial port. */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT);
}
static void init(struct device *dev)
{
if (!dev->enabled)
return;
switch(dev->path.pnp.device) {
case PC97317_KBCK:
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); /* Disable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */
pnp_set_enable(dev, 1); /* Enable keyboard */
pc_keyboard_init();
break;
default:
break;
}
}
static void pilot_disable_serial(device_t dev)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
pnp_set_enable(dev, 0);
pnp_exit_ext_func_mode(dev);
}
static void wilco_ec_serial_init(void)
{
pnp_devfn_t dev = PNP_DEV(PNP_CFG_IDX, PNP_LDN_SERIAL);
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1);
pnp_set_iobase(dev, PNP_IDX_IO1, cpu_to_be16(CONFIG_TTYS0_BASE));
pnp_write_config(dev, PNP_IDX_IO0, 1);
pnp_exit_conf_state(dev);
}
static void superio_init(void)
{
pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT);
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 4); /* COM1 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
#if 0
/* Must route GPIO to UART2 before enabling this */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 3);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
#endif
pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT);
}
static void superio_init(void)
{
/* Set base address of power management unit */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 8);
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, PM_BASE);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
/* Use on-chip clock multiplier */
outb(0x03, PM_BASE);
outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1);
/* Wait for the clock to stabilise */
while (!(inb(PM_BASE + 1) & 0x80)) ;
/* Enable the serial ports. */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 6); /* COM1 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
/* Set LDN 5 UART Mode */
outb(0x21, SUPERIO_CONFIG_PORT);
outb(inb(SUPERIO_CONFIG_PORT + 1) | (1 << 3), SUPERIO_CONFIG_PORT + 1);
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 3);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
}
/* The PC97317 needs clocks to be set up before the serial port will operate. */
static void pc97317_enable_serial(device_t dev, u16 iobase)
{
/* Set base address of power management unit. */
pnp_set_logical_device(PM_DEV);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE);
pnp_set_enable(dev, 1);
/* Use on-chip clock multiplier. */
outb(0x03, PM_BASE);
outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1);
/* Wait for the clock to stabilise. */
while(!(inb(PM_BASE + 1) & 0x80))
;
/* Set the base address of the port. */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
static inline void kbc1100_early_init(unsigned port)
{
device_t dev;
dev = PNP_DEV (port, KBC1100_KBC);
pnp_enter_conf_state(dev);
/* Serial IRQ enabled */
outb(0x25, port);
outb(0x04, port + 1);
/* Enable SMSC UART 0 */
dev = PNP_DEV (port, SMSCSUPERIO_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
pnp_set_enable(dev, 1);
/* Enable keyboard */
dev = PNP_DEV (port, KBC1100_KBC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */
pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */
pnp_set_enable(dev, 1);
/* Enable EC Channel 0 */
dev = PNP_DEV (port, KBC1100_EC0);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
/* disable the 1s timer */
outb(0xE7, 0x64);
}
static void early_superio_config(void)
{
int timeout = 100000;
pnp_devfn_t dev = PNP_DEV(0x2e, 3);
pnp_write_config(dev, 0x29, 0x06);
while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--)
udelay(1000);
/* Enable COM1 */
pnp_set_logical_device(dev);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
pnp_set_enable(dev, 1);
}
void shc4307_init(void)
{
shc4307_enter_ext_func_mode(CMOS_DEV);
pnp_set_logical_device(CMOS_DEV); /* CMOS/RTC */
pnp_set_iobase(CMOS_DEV, PNP_IDX_IO0, 0x70);
pnp_set_iobase(CMOS_DEV, PNP_IDX_IO1, 0x72);
pnp_set_irq(CMOS_DEV, PNP_IDX_IRQ0, 8);
/* pnp_set_enable(CMOS_DEV, 3); */
pnp_write_config(CMOS_DEV, 0x30, 3);
pnp_set_logical_device(KBD_DEV); /* Keyboard */
pnp_set_irq(KBD_DEV, PNP_IDX_IRQ0, 1);
pnp_set_enable(KBD_DEV, 1);
pnp_set_logical_device(DBG_DEV); /* Debug */
pnp_set_iobase(DBG_DEV, PNP_IDX_IO0, 0x80);
pnp_set_enable(DBG_DEV, 1);
pnp_set_logical_device(REGS_DEV);
pnp_set_iobase(REGS_DEV, PNP_IDX_IO0, 0x600);
pnp_set_enable(REGS_DEV, 1);
shc4307_exit_ext_func_mode(CMOS_DEV);
}
static void superio_init(void)
{
pnp_enter_ext_func_mode(0x2e);
pnp_set_logical_device(0x2e, 2); // COM-A
pnp_set_enable(0x2e, 0);
pnp_set_iobase0(0x2e, 0x3f8);
pnp_set_irq0(0x2e, 4);
pnp_set_enable(0x2e, 1);
pnp_set_logical_device(0x2e, 3); // COM-B
pnp_set_enable(0x2e, 0);
pnp_set_iobase0(0x2e, 0x2f8);
pnp_set_irq0(0x2e, 3);
pnp_set_enable(0x2e, 1);
pnp_exit_ext_func_mode(0x2e);
pnp_enter_ext_func_mode(0x4e);
// Set COM3 to sane non-conflicting values
pnp_set_logical_device(0x4e, 2); // COM-A
pnp_set_enable(0x4e, 0);
pnp_set_iobase0(0x4e, 0x3e8);
pnp_set_irq0(0x4e, 11);
pnp_set_enable(0x4e, 1);
// Set COM4 to sane non-conflicting values
pnp_set_logical_device(0x4e, 3); // COM-B
pnp_set_enable(0x4e, 0);
pnp_set_iobase0(0x4e, 0x2e8);
pnp_set_irq0(0x4e, 10);
pnp_set_enable(0x4e, 1);
pnp_exit_ext_func_mode(0x4e);
}
/* This box has one superio
* Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method.
*/
static void early_superio_config_w83627ehg(void)
{
device_t dev;
dev = DUMMY_DEV;
pnp_enter_ext_func_mode(dev);
pnp_write_config(dev, 0x24, 0xc4); // PNPCSV
pnp_write_config(dev, 0x29, 0x01); // GPIO settings
pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02
pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings?
pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
dev=PNP_DEV(0x4e, W83627EHG_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_SP2);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
// pnp_write_config(dev, 0xf1, 4); // IRMODE0
pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
//pnp_write_config(dev, 0xf0, 0x82);
pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_GPIO2);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1); // Just enable it
dev=PNP_DEV(0x4e, W83627EHG_GPIO3);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
dev=PNP_DEV(0x4e, W83627EHG_FDC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
dev=PNP_DEV(0x4e, W83627EHG_PP);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
/* Enable HWM */
dev=PNP_DEV(0x4e, W83627EHG_HWM);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
/* Early mainboard specific GPIO setup. */
static void mb_gpio_init(void)
{
device_t dev;
uint16_t port;
uint32_t set_gpio;
/* Southbridge GPIOs. */
/* Set the LPC device statically. */
dev = PCI_DEV(0x0, 0x1f, 0x0);
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));
pci_write_config8(dev, GPIO_CNTL, 0x10);
/* Set GPIO23 to high, this enables the LAN controller. */
udelay(10);
set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
set_gpio |= 1 << 23;
outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
/* Disable AC97 Modem */
pci_write_config8(dev, 0xf2, 0x40);
/* Super I/O GPIOs. */
dev = PME_DEV;
port = dev >> 8;
/* Enter the configuration state. */
outb(0x55, port);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
pnp_set_enable(dev, 1);
/* GP21 - LED_RED */
outl(0x01, PME_IO_BASE_ADDR + 0x2c);
/* GP30 - FAN2_TACH */
outl(0x05, PME_IO_BASE_ADDR + 0x33);
/* GP31 - FAN1_TACH */
outl(0x05, PME_IO_BASE_ADDR + 0x34);
/* GP32 - FAN2_CTRL */
outl(0x04, PME_IO_BASE_ADDR + 0x35);
/* GP33 - FAN1_CTRL */
outl(0x04, PME_IO_BASE_ADDR + 0x36);
/* GP34 - AUD_MUTE_OUT_R */
outl(0x00, PME_IO_BASE_ADDR + 0x37);
/* GP36 - KBRST */
outl(0x00, PME_IO_BASE_ADDR + 0x39);
/* GP37 - A20GATE */
outl(0x00, PME_IO_BASE_ADDR + 0x3a);
/* GP42 - GPIO_PME_OUT */
outl(0x00, PME_IO_BASE_ADDR + 0x3d);
/* GP50 - SER2_RI */
outl(0x05, PME_IO_BASE_ADDR + 0x3f);
/* GP51 - SER2_DCD */
outl(0x05, PME_IO_BASE_ADDR + 0x40);
/* GP52 - SER2_RX */
outl(0x05, PME_IO_BASE_ADDR + 0x41);
/* GP53 - SER2_TX */
outl(0x04, PME_IO_BASE_ADDR + 0x42);
/* GP55 - SER2_RTS */
outl(0x04, PME_IO_BASE_ADDR + 0x44);
/* GP56 - SER2_CTS */
outl(0x05, PME_IO_BASE_ADDR + 0x45);
/* GP57 - SER2_DTR */
outl(0x04, PME_IO_BASE_ADDR + 0x46);
/* GP60 - LED_GREEN */
outl(0x01, PME_IO_BASE_ADDR + 0x47);
/* GP61 - LED_YELLOW */
outl(0x01, PME_IO_BASE_ADDR + 0x48);
/* GP3 */
outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
/* GP4 */
outl(0x04, PME_IO_BASE_ADDR + 0x4e);
/* FAN1 */
outl(0x01, PME_IO_BASE_ADDR + 0x56);
/* FAN2 */
outl(0x01, PME_IO_BASE_ADDR + 0x57);
/* Fan Control */
outl(0x50, PME_IO_BASE_ADDR + 0x58);
/* Fan1 Tachometer */
outl(0xff, PME_IO_BASE_ADDR + 0x59);
/* Fan2 Tachometer */
outl(0xff, PME_IO_BASE_ADDR + 0x5a);
/* LED1 */
outl(0x00, PME_IO_BASE_ADDR + 0x5d);
/* LED2 */
outl(0x00, PME_IO_BASE_ADDR + 0x5e);
/* Keyboard Scan Code */
outl(0x00, PME_IO_BASE_ADDR + 0x5f);
/* Exit the configuration state. */
outb(0xaa, port);
}
