void pc87366_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); }
static void pc87309_enable_serial(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); }
void sch4037_early_init(unsigned port) { pnp_devfn_t dev; dev = PNP_DEV(port, SMSCSUPERIO_SP1); pnp_enter_conf_state(dev); /* Auto power management */ pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ pnp_write_config(dev, 0x23, 0); /* Enable SMSC UART 0 */ dev = PNP_DEV(port, SMSCSUPERIO_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); /* Enabled High speed, disabled MIDI support. */ pnp_write_config(dev, 0xF0, 0x02); pnp_set_enable(dev, 1); /* Enable keyboard */ dev = PNP_DEV(port, SCH4037_KBC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); }
void it8716f_enable_dev(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); }
static void pc8374_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); if (iobase) pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); }
static void pilot_disable_serial(device_t dev) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); }
/* Serial config is a fairly standard procedure. */ static void pilot_enable_serial(device_t dev, unsigned iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); }
static inline void w83627thg_enable_serial(device_t dev, unsigned int iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); }
void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); }
/* * Function: lpc47b272_enable_serial * Parameters: dev - high 8 bits = Super I/O port, * low 8 bits = logical device number (per lpc47b272.h) * iobase - processor I/O port address to assign to this serial device * Return Value: bool * Description: Configure the base I/O port of the specified serial device * and enable the serial device. */ static void lpc47b272_enable_serial(device_t dev, unsigned iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); }
static void wilco_ec_serial_init(void) { pnp_devfn_t dev = PNP_DEV(PNP_CFG_IDX, PNP_LDN_SERIAL); pnp_enter_conf_state(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); pnp_set_iobase(dev, PNP_IDX_IO1, cpu_to_be16(CONFIG_TTYS0_BASE)); pnp_write_config(dev, PNP_IDX_IO0, 1); pnp_exit_conf_state(dev); }
static void disable_sio_watchdog(device_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ pnp_set_logical_device(dev); pnp_set_enable(dev, 1); pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); /* disable the sio watchdog */ outb(0, NSC_WDBASE + 0); pnp_set_enable(dev, 0); #endif }
/* The PC97317 needs clocks to be set up before the serial port will operate. */ static void pc97317_enable_serial(device_t dev, u16 iobase) { /* Set base address of power management unit. */ pnp_set_logical_device(PM_DEV); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE); pnp_set_enable(dev, 1); /* Use on-chip clock multiplier. */ outb(0x03, PM_BASE); outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1); /* Wait for the clock to stabilise. */ while(!(inb(PM_BASE + 1) & 0x80)) ; /* Set the base address of the port. */ pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); }
static inline void kbc1100_early_init(unsigned port) { device_t dev; dev = PNP_DEV (port, KBC1100_KBC); pnp_enter_conf_state(dev); /* Serial IRQ enabled */ outb(0x25, port); outb(0x04, port + 1); /* Enable SMSC UART 0 */ dev = PNP_DEV (port, SMSCSUPERIO_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); pnp_set_enable(dev, 1); /* Enable keyboard */ dev = PNP_DEV (port, KBC1100_KBC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ pnp_set_enable(dev, 1); /* Enable EC Channel 0 */ dev = PNP_DEV (port, KBC1100_EC0); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); /* disable the 1s timer */ outb(0xE7, 0x64); }
static void early_superio_config(void) { int timeout = 100000; pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0x06); while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) udelay(1000); /* Enable COM1 */ pnp_set_logical_device(dev); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_enable(dev, 1); }
void shc4307_init(void) { shc4307_enter_ext_func_mode(CMOS_DEV); pnp_set_logical_device(CMOS_DEV); /* CMOS/RTC */ pnp_set_iobase(CMOS_DEV, PNP_IDX_IO0, 0x70); pnp_set_iobase(CMOS_DEV, PNP_IDX_IO1, 0x72); pnp_set_irq(CMOS_DEV, PNP_IDX_IRQ0, 8); /* pnp_set_enable(CMOS_DEV, 3); */ pnp_write_config(CMOS_DEV, 0x30, 3); pnp_set_logical_device(KBD_DEV); /* Keyboard */ pnp_set_irq(KBD_DEV, PNP_IDX_IRQ0, 1); pnp_set_enable(KBD_DEV, 1); pnp_set_logical_device(DBG_DEV); /* Debug */ pnp_set_iobase(DBG_DEV, PNP_IDX_IO0, 0x80); pnp_set_enable(DBG_DEV, 1); pnp_set_logical_device(REGS_DEV); pnp_set_iobase(REGS_DEV, PNP_IDX_IO0, 0x600); pnp_set_enable(REGS_DEV, 1); shc4307_exit_ext_func_mode(CMOS_DEV); }
/* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ static void early_superio_config_w83627ehg(void) { device_t dev; dev = DUMMY_DEV; pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x24, 0xc4); // PNPCSV pnp_write_config(dev, 0x29, 0x01); // GPIO settings pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? dev=PNP_DEV(0x4e, W83627EHG_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 4); pnp_set_enable(dev, 1); dev=PNP_DEV(0x4e, W83627EHG_SP2); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 3); // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1); dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); //pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1); dev=PNP_DEV(0x4e, W83627EHG_GPIO2); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); // Just enable it dev=PNP_DEV(0x4e, W83627EHG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient dev=PNP_DEV(0x4e, W83627EHG_FDC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); dev=PNP_DEV(0x4e, W83627EHG_PP); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); /* Enable HWM */ dev=PNP_DEV(0x4e, W83627EHG_HWM); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); }
/* Early mainboard specific GPIO setup. */ static void mb_gpio_init(void) { device_t dev; uint16_t port; uint32_t set_gpio; /* Southbridge GPIOs. */ /* Set the LPC device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x0); /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1)); pci_write_config8(dev, GPIO_CNTL, 0x10); /* Set GPIO23 to high, this enables the LAN controller. */ udelay(10); set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c); set_gpio |= 1 << 23; outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c); /* Disable AC97 Modem */ pci_write_config8(dev, 0xf2, 0x40); /* Super I/O GPIOs. */ dev = PME_DEV; port = dev >> 8; /* Enter the configuration state. */ outb(0x55, port); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR); pnp_set_enable(dev, 1); /* GP21 - LED_RED */ outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP30 - FAN2_TACH */ outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP31 - FAN1_TACH */ outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP32 - FAN2_CTRL */ outl(0x04, PME_IO_BASE_ADDR + 0x35); /* GP33 - FAN1_CTRL */ outl(0x04, PME_IO_BASE_ADDR + 0x36); /* GP34 - AUD_MUTE_OUT_R */ outl(0x00, PME_IO_BASE_ADDR + 0x37); /* GP36 - KBRST */ outl(0x00, PME_IO_BASE_ADDR + 0x39); /* GP37 - A20GATE */ outl(0x00, PME_IO_BASE_ADDR + 0x3a); /* GP42 - GPIO_PME_OUT */ outl(0x00, PME_IO_BASE_ADDR + 0x3d); /* GP50 - SER2_RI */ outl(0x05, PME_IO_BASE_ADDR + 0x3f); /* GP51 - SER2_DCD */ outl(0x05, PME_IO_BASE_ADDR + 0x40); /* GP52 - SER2_RX */ outl(0x05, PME_IO_BASE_ADDR + 0x41); /* GP53 - SER2_TX */ outl(0x04, PME_IO_BASE_ADDR + 0x42); /* GP55 - SER2_RTS */ outl(0x04, PME_IO_BASE_ADDR + 0x44); /* GP56 - SER2_CTS */ outl(0x05, PME_IO_BASE_ADDR + 0x45); /* GP57 - SER2_DTR */ outl(0x04, PME_IO_BASE_ADDR + 0x46); /* GP60 - LED_GREEN */ outl(0x01, PME_IO_BASE_ADDR + 0x47); /* GP61 - LED_YELLOW */ outl(0x01, PME_IO_BASE_ADDR + 0x48); /* GP3 */ outl(0xc0, PME_IO_BASE_ADDR + 0x4d); /* GP4 */ outl(0x04, PME_IO_BASE_ADDR + 0x4e); /* FAN1 */ outl(0x01, PME_IO_BASE_ADDR + 0x56); /* FAN2 */ outl(0x01, PME_IO_BASE_ADDR + 0x57); /* Fan Control */ outl(0x50, PME_IO_BASE_ADDR + 0x58); /* Fan1 Tachometer */ outl(0xff, PME_IO_BASE_ADDR + 0x59); /* Fan2 Tachometer */ outl(0xff, PME_IO_BASE_ADDR + 0x5a); /* LED1 */ outl(0x00, PME_IO_BASE_ADDR + 0x5d); /* LED2 */ outl(0x00, PME_IO_BASE_ADDR + 0x5e); /* Keyboard Scan Code */ outl(0x00, PME_IO_BASE_ADDR + 0x5f); /* Exit the configuration state. */ outb(0xaa, port); }
/* * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ static void pilot_early_init(device_t dev) { unsigned port = dev >> 8; print_debug("Using port: "); print_debug_hex16(port); print_debug("\n"); pilot_disable_serial(PNP_DEV(port, 0x1)); print_debug("disable serial 1\n"); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x3)); pnp_set_enable(dev, 0); pnp_set_iobase(dev, 0x60, 0x0b00); pnp_set_iobase(dev, 0x62, 0x0b80); pnp_set_iobase(dev, 0x64, 0x0b84); pnp_set_iobase(dev, 0x66, 0x0b86); pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); /* pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x3)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x3), 0); pnp_exit_ext_func_mode(dev); */ pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x4)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable( PNP_DEV(port, 0x4), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x5)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x5), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x6)); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); pnp_set_irq(dev, PNP_IDX_IRQ0, 1); pnp_set_drq(dev, 0x71, 3); pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0xe)); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x70); pnp_set_iobase(dev, PNP_IDX_IO1, 0x72); pnp_set_irq(dev, PNP_IDX_IRQ0, 8); pnp_set_drq(dev, 0x71, 3); pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x7)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x7), 0); pnp_exit_ext_func_mode(dev); /* pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x8)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x8), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x9)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x9), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x10)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x10), 0); pnp_exit_ext_func_mode(dev); */ }
/* Early mainboard specific GPIO setup. */ static void mb_gpio_init(void) { device_t dev; uint16_t port; /* Southbridge GPIOs. */ /* Set the LPC device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x0); /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); pci_write_config8(dev, GPIO_CNTL, 0x10); udelay(10); outl(0x1a203180, GPIO_BASE_ADDR + 0x00); /* GPIO_USE_SEL */ outl(0x0000ffff, GPIO_BASE_ADDR + 0x04); /* GP_IO_SEL */ outl(0x13bf0000, GPIO_BASE_ADDR + 0x0c); /* GP_LVL */ outl(0x00040000, GPIO_BASE_ADDR + 0x18); /* GPO_BLINK */ outl(0x000039ff, GPIO_BASE_ADDR + 0x2c); /* GPI_INV */ /* Super I/O GPIOs. */ dev = PME_DEV; port = dev >> 8; /* Enter the configuration state. */ outb(0x55, port); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR); pnp_set_enable(dev, 1); /* GP10 - J1B1 */ outl(0x01, PME_IO_BASE_ADDR + 0x23); /* GP11 - J1B2 */ outl(0x01, PME_IO_BASE_ADDR + 0x24); /* GP12 - J2B1 */ outl(0x01, PME_IO_BASE_ADDR + 0x25); /* GP13 - J2B2 */ outl(0x01, PME_IO_BASE_ADDR + 0x26); /* GP14 - J1X */ outl(0x01, PME_IO_BASE_ADDR + 0x27); /* GP15 - J1Y */ outl(0x01, PME_IO_BASE_ADDR + 0x28); /* GP16 - J2X */ outl(0x01, PME_IO_BASE_ADDR + 0x29); /* GP17 - J2Y */ outl(0x01, PME_IO_BASE_ADDR + 0x2a); /* GP20 - 8042 P17 */ outl(0x01, PME_IO_BASE_ADDR + 0x2b); /* GP21 - 8042 P16 */ outl(0x00, PME_IO_BASE_ADDR + 0x2c); /* GP22 - 8042 P12 */ outl(0x00, PME_IO_BASE_ADDR + 0x2d); /* GP24 */ outl(0x00, PME_IO_BASE_ADDR + 0x2f); /* GP25 - MIDI_IN */ outl(0x01, PME_IO_BASE_ADDR + 0x30); /* GP26 - MIDI_OUT */ outl(0x01, PME_IO_BASE_ADDR + 0x31); /* GP27 - nIO_SMI */ outl(0x04, PME_IO_BASE_ADDR + 0x32); /* GP30 - FAN_TACH2 */ outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP31 - FAN_TACH1 */ outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP32 - FAN2 */ outl(0x04, PME_IO_BASE_ADDR + 0x35); /* GP33 - FAN1 */ outl(0x04, PME_IO_BASE_ADDR + 0x36); /* GP34 - IRRX2 */ outl(0x05, PME_IO_BASE_ADDR + 0x37); /* GP35 - IRTX2 */ outl(0x04, PME_IO_BASE_ADDR + 0x38); /* GP36 - nKBDRST */ outl(0x84, PME_IO_BASE_ADDR + 0x39); /* GP37 - A20M */ outl(0x84, PME_IO_BASE_ADDR + 0x3a); /* GP40 - DRVDEN0 */ outl(0x04, PME_IO_BASE_ADDR + 0x3b); /* GP41 - DRVDEN1 */ outl(0x04, PME_IO_BASE_ADDR + 0x3c); /* GP42 - nIO_PME */ outl(0x84, PME_IO_BASE_ADDR + 0x3d); /* GP43 */ outl(0x00, PME_IO_BASE_ADDR + 0x3e); /* GP50 - nIR2 */ outl(0x05, PME_IO_BASE_ADDR + 0x3f); /* GP51 - nDCD2 */ outl(0x05, PME_IO_BASE_ADDR + 0x40); /* GP52 - RXD2 */ outl(0x05, PME_IO_BASE_ADDR + 0x41); /* GP53 - TXD2 */ outl(0x04, PME_IO_BASE_ADDR + 0x42); /* GP54 - nDSR2 */ outl(0x05, PME_IO_BASE_ADDR + 0x43); /* GP55 - nRTS2 */ outl(0x04, PME_IO_BASE_ADDR + 0x44); /* GP56 - nCTS2 */ outl(0x05, PME_IO_BASE_ADDR + 0x45); /* GP57 - nDTR2 */ outl(0x04, PME_IO_BASE_ADDR + 0x46); /* GP60 - LED1 */ outl(0x84, PME_IO_BASE_ADDR + 0x47); /* GP61 - LED2 */ outl(0x84, PME_IO_BASE_ADDR + 0x48); /* GP1 */ outl(0x00, PME_IO_BASE_ADDR + 0x4b); /* GP2 */ outl(0x14, PME_IO_BASE_ADDR + 0x4c); /* GP3 */ outl(0xda, PME_IO_BASE_ADDR + 0x4d); /* GP4 */ outl(0x08, PME_IO_BASE_ADDR + 0x4e); /* GP5 */ outl(0x00, PME_IO_BASE_ADDR + 0x4f); /* GP6 */ outl(0x00, PME_IO_BASE_ADDR + 0x50); /* FAN1 */ outl(0x01, PME_IO_BASE_ADDR + 0x56); /* FAN2 */ outl(0x01, PME_IO_BASE_ADDR + 0x57); /* Fan Control */ outl(0xf0, PME_IO_BASE_ADDR + 0x58); /* Fan1 Preload */ outl(0x00, PME_IO_BASE_ADDR + 0x5b); /* Fan2 Preload */ outl(0x00, PME_IO_BASE_ADDR + 0x5c); /* LED1 */ outl(0x03, PME_IO_BASE_ADDR + 0x5d); /* LED2 */ outl(0x03, PME_IO_BASE_ADDR + 0x5e); /* Keyboard Scan Code */ outl(0x00, PME_IO_BASE_ADDR + 0x5f); /* Exit the configuration state. */ outb(0xaa, port); }