void f71869ad_multifunc_init(struct device *dev)
{
const struct superio_fintek_f71869ad_config *conf = dev->chip_info;
pnp_enter_conf_mode(dev);
/* multi-func select reg1 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG1,
conf->multi_function_register_1);
/* multi-func select reg2 (CLK_TUNE_EN=0) */
pnp_write_config(dev, MULTI_FUNC_SEL_REG2,
conf->multi_function_register_2);
/* multi-func select reg3 (CLK_TUNE_EN=0) */
pnp_write_config(dev, MULTI_FUNC_SEL_REG3,
conf->multi_function_register_3);
/* multi-func select reg4 (CLK_TUNE_EN=0) */
pnp_write_config(dev, MULTI_FUNC_SEL_REG4,
conf->multi_function_register_4);
/* multi-func select reg5 (CLK_TUNE_EN=0) */
pnp_write_config(dev, MULTI_FUNC_SEL_REG5,
conf->multi_function_register_5);
pnp_exit_conf_mode(dev);
}
void sch4037_early_init(unsigned port)
{
pnp_devfn_t dev;
dev = PNP_DEV(port, SMSCSUPERIO_SP1);
pnp_enter_conf_state(dev);
/* Auto power management */
pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */
pnp_write_config(dev, 0x23, 0);
/* Enable SMSC UART 0 */
dev = PNP_DEV(port, SMSCSUPERIO_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4);
/* Enabled High speed, disabled MIDI support. */
pnp_write_config(dev, 0xF0, 0x02);
pnp_set_enable(dev, 1);
/* Enable keyboard */
dev = PNP_DEV(port, SCH4037_KBC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */
pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
void mainboard_config_superio(void)
{
const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);
const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);
const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);
/* Select HWM/LED functions instead of floppy functions. */
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);
/* Power RAM in S3 and let the PCH handle power failure actions. */
pnp_set_logical_device(ACPI_DEV);
pnp_write_config(ACPI_DEV, 0xe4, 0x70);
/*
* Don't know what's needed here, just set the same as the vendor
* firmware.
*/
pnp_set_logical_device(IR_DEV);
pnp_write_config(IR_DEV, 0xf1, 0x5c);
nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);
}
void f71808a_multifunc_init(struct device *dev)
{
const struct superio_fintek_f71808a_config *conf = dev->chip_info;
pnp_enter_conf_mode(dev);
/* multi-func select reg0 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG0,
conf->multi_function_register_0);
/* multi-func select reg1 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG1,
conf->multi_function_register_1);
/* multi-func select reg2 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG2,
conf->multi_function_register_2);
/* multi-func select reg3 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG3,
conf->multi_function_register_3);
/* multi-func select reg4 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG4,
conf->multi_function_register_4);
pnp_exit_conf_mode(dev);
}
static void nct5572d_init(struct device *dev)
{
uint8_t byte;
uint8_t power_status;
uint8_t mouse_detected;
if (!dev->enabled)
return;
switch (dev->path.pnp.device) {
/* TODO: Might potentially need code for HWM or FDC etc. */
case NCT5572D_KBC:
/* Enable mouse controller */
pnp_enter_conf_mode_8787(dev);
byte = pnp_read_config(dev, 0x2a);
byte &= ~(0x1 << 1);
pnp_write_config(dev, 0x2a, byte);
pnp_exit_conf_mode_aa(dev);
mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE);
if (!mouse_detected) {
printk(BIOS_INFO, "%s: Disable mouse controller.",
__func__);
pnp_enter_conf_mode_8787(dev);
byte = pnp_read_config(dev, 0x2a);
byte |= 0x1 << 1;
pnp_write_config(dev, 0x2a, byte);
pnp_exit_conf_mode_aa(dev);
}
break;
case NCT5572D_ACPI:
/* Set power state after power fail */
power_status = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&power_status, "power_on_after_fail");
pnp_enter_conf_mode_8787(dev);
pnp_set_logical_device(dev);
byte = pnp_read_config(dev, 0xe4);
byte &= ~0x60;
if (power_status == 1)
byte |= (0x1 << 5); /* Force power on */
else if (power_status == 2)
byte |= (0x2 << 5); /* Use last power state */
pnp_write_config(dev, 0xe4, byte);
pnp_exit_conf_mode_aa(dev);
printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off");
break;
}
}
void lpc47n227_pnp_set_irq(struct device *dev, u8 irq)
{
u8 irq_config_register = 0, irq_config_mask = 0;
u8 current_config, new_config;
switch (dev->path.pnp.device) {
case LPC47N227_PP:
irq_config_register = 0x27;
irq_config_mask = 0x0F;
break;
case LPC47N227_SP1:
irq_config_register = 0x28;
irq_config_mask = 0xF0;
irq <<= 4;
break;
case LPC47N227_SP2:
irq_config_register = 0x28;
irq_config_mask = 0x0F;
break;
case LPC47N227_KBDC:
break;
default:
BUG();
return;
}
current_config = pnp_read_config(dev, irq_config_register);
new_config = (current_config & ~irq_config_mask) | irq;
pnp_write_config(dev, irq_config_register, new_config);
}
static void lpc47n217_pnp_set_enable(device_t dev, int enable)
{
u8 power_register = 0, power_mask = 0, current_power, new_power;
switch(dev->path.pnp.device) {
case LPC47N217_PP:
power_register = 0x01;
power_mask = 0x04;
break;
case LPC47N217_SP1:
power_register = 0x02;
power_mask = 0x08;
break;
case LPC47N217_SP2:
power_register = 0x02;
power_mask = 0x80;
break;
default:
BUG();
return;
}
current_power = pnp_read_config(dev, power_register);
new_power = current_power & ~power_mask; /* Disable by default. */
if (enable) {
struct resource* ioport_resource;
ioport_resource = find_resource(dev, PNP_IDX_IO0);
lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
new_power |= power_mask; /* Enable. */
} else {
lpc47n217_pnp_set_iobase(dev, 0);
}
pnp_write_config(dev, power_register, new_power);
}
static void lpc47n217_pnp_set_irq(device_t dev, u8 irq)
{
u8 irq_config_register = 0, irq_config_mask = 0;
u8 current_config, new_config;
switch(dev->path.pnp.device) {
case LPC47N217_PP:
irq_config_register = 0x27;
irq_config_mask = 0x0F;
break;
case LPC47N217_SP1:
irq_config_register = 0x28;
irq_config_mask = 0xF0;
irq <<= 4;
break;
case LPC47N217_SP2:
irq_config_register = 0x28;
irq_config_mask = 0x0F;
break;
default:
BUG();
return;
}
ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range? */
current_config = pnp_read_config(dev, irq_config_register);
new_config = (current_config & ~irq_config_mask) | irq;
pnp_write_config(dev, irq_config_register, new_config);
}
static void init(struct device *dev)
{
u8 reg8;
if (!dev->enabled)
return;
switch(dev->path.pnp.device) {
case PC97307_KBCK:
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); /* Disable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */
pnp_set_enable(dev, 1); /* Enable keyboard. */
pc_keyboard_init();
break;
case PC97307_FDC:
/* Set up floppy in PS/2 mode. */
outb(0x09, SIO_CONFIG_RA);
reg8 = inb(SIO_CONFIG_RD);
reg8 = (reg8 & 0x3F) | 0x40;
outb(reg8, SIO_CONFIG_RD);
outb(reg8, SIO_CONFIG_RD); /* Have to write twice to change! */
break;
default:
break;
}
}
static void vt1211_set_iobase(struct device *dev, u8 index, u16 iobase)
{
switch (dev->path.pnp.device) {
case VT1211_FDC:
case VT1211_PP:
case VT1211_SP1:
case VT1211_SP2:
pnp_write_config(dev, index + 0, (iobase >> 2) & 0xff);
break;
case VT1211_ROM:
/* TODO: Error. VT1211_ROM doesn't have an I/O base. */
break;
case VT1211_MIDI:
case VT1211_GAME:
case VT1211_GPIO:
case VT1211_WDG:
case VT1211_WUC:
case VT1211_HWM:
case VT1211_FIR:
default:
pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
pnp_write_config(dev, index + 1, iobase & 0xff);
break;
}
}
static void route_pins_to_uart(struct device *dev, bool to_uart)
{
u8 reg;
reg = pnp_read_config(dev, 0x1c);
switch (dev->path.pnp.device) {
case NCT5104D_SP3:
case NCT5104D_GPIO0:
/* Route pins 33 - 40. */
if (to_uart)
reg |= (1 << 3);
else
reg &= ~(1 << 3);
break;
case NCT5104D_SP4:
case NCT5104D_GPIO1:
/* Route pins 41 - 48. */
if (to_uart)
reg |= (1 << 2);
else
reg &= ~(1 << 2);
break;
default:
break;
}
pnp_write_config(dev, 0x1c, reg);
}
static void enable_hwm_smbus(device_t dev)
{
/* Enable SensorBus register access. */
u8 reg8;
reg8 = pnp_read_config(dev, 0xf0);
reg8 |= (1 << 1);
pnp_write_config(dev, 0xf0, reg8);
}
static void enable_hwm_smbus(struct device *dev)
{
u8 reg8;
/* Configure pins 91/92 as SDA/SCL (I2C bus). */
reg8 = pnp_read_config(dev, 0x2a);
reg8 |= (1 << 1);
pnp_write_config(dev, 0x2a, reg8);
}
static void w83627dhg_enable_UR2(struct device *dev)
{
u8 reg8;
pnp_enter_conf_mode(dev);
reg8 = pnp_read_config(dev, 0x2c);
reg8 |= (0x3);
pnp_write_config(dev, 0x2c, reg8); // Set pins 78-85-> UART B
pnp_exit_conf_mode(dev);
}
static void wilco_ec_serial_init(void)
{
pnp_devfn_t dev = PNP_DEV(PNP_CFG_IDX, PNP_LDN_SERIAL);
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1);
pnp_set_iobase(dev, PNP_IDX_IO1, cpu_to_be16(CONFIG_TTYS0_BASE));
pnp_write_config(dev, PNP_IDX_IO0, 1);
pnp_exit_conf_state(dev);
}
/*
* Set the UART clock source.
*
* Possible UART clock source speeds are:
*
* 0 = 1.8462 MHz (default)
* 1 = 2 MHz
* 2 = 24 MHz
* 3 = 14.769 MHz
*
* The faster clocks allow for BAUD rates up to 2mbits.
*
* Warning: The kernel will need to be adjusted since it assumes
* a 1.8462 MHz clock.
*/
static void set_uart_clock_source(device_t dev, u8 uart_clock)
{
u8 value;
w83627uhg_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
value = pnp_read_config(dev, 0xf0);
value &= ~0x03;
value |= (uart_clock & 0x03);
pnp_write_config(dev, 0xf0, value);
w83627uhg_exit_ext_func_mode(dev);
}
/*
* Set the UART clock source.
*
* Possible UART clock source speeds are:
*
* 0 = 1.8462 MHz (default)
* 1 = 2 MHz
* 2 = 24 MHz
* 3 = 14.769 MHz
*
* The faster clocks allow for BAUD rates up to 2mbits.
*
* Warning: The kernel will need to be adjusted since it assumes
* a 1.8462 MHz clock.
*/
static void set_uart_clock_source(struct device *dev, u8 uart_clock)
{
u8 value;
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
value = pnp_read_config(dev, 0xf0);
value &= ~0x03;
value |= (uart_clock & 0x03);
pnp_write_config(dev, 0xf0, value);
pnp_exit_conf_mode(dev);
}
static void mb_lpc_setup(void)
{
u32 reg32;
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
/* Set GPIOs on superio, enable UART */
if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776)) {
nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2);
pnp_set_logical_device(SERIAL_DEV_R2);
pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80);
pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80);
pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60);
nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2);
nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE);
} else {
winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE);
}
/* IRQ routing */
RCBA16(D31IR) = 0x0132;
RCBA16(D29IR) = 0x0237;
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
RCBA8(OIC);
reg32 = RCBA32(GCS);
reg32 |= (1 << 5);
RCBA32(GCS) = reg32;
RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
| FD_ACAUD | 1;
RCBA32(CG) = 0x00000001;
}
static void mainboard_set_e7520_pll(unsigned bits)
{
uint16_t gpio_index;
uint8_t data;
device_t dev;
/* currently only handle the Jarrell/PC87427 case */
dev = PC87427_GPIO_DEV;
pnp_set_logical_device(dev);
gpio_index = pnp_read_iobase(dev, 0x60);
/* select SIO GPIO port 4, pin 2 */
pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x42));
/* set to push-pull, enable output */
pnp_write_config(dev, PC87427_GPCFG1, 0x03);
/* select SIO GPIO port 4, pin 4 */
pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x44));
/* set to push-pull, enable output */
pnp_write_config(dev, PC87427_GPCFG1, 0x03);
/* set gpio 42,44 signal levels */
data = inb(gpio_index + PC87427_GPDO_4);
if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
print_debug("set_pllsel: correct settings detected!\n");
return; /* settings already configured */
} else {
outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
/* reset */
print_debug("set_pllsel: settings adjusted, now resetting...\n");
// hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
// mch_reset();
full_reset();
}
return;
}
static void sio_init(void)
{
u8 reg;
pnp_enter_ext_func_mode(SERIAL_DEV);
reg = pnp_read_config(SERIAL_DEV, 0x24);
/* 4 Mbit flash */
reg = (reg & ~0x30) | 0x20;
/* We have 24MHz input. */
reg &= ~0x40;
/* enable MEMW#, so flash can be written */
reg |= 0x08;
pnp_write_config(SERIAL_DEV, 0x24, reg);
}
static void init(device_t dev)
{
struct superio_nsc_pc97317_config *conf;
struct resource *res0, *res1;
if (!dev->enabled) {
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case PC97317_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case PC97317_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case PC97317_KBCK:
/* Enable keyboard */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); /* Disable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 Mhz */
pnp_set_enable(dev, 1); /* Enable keyboard */
res0 = find_resource(dev, PNP_IDX_IO0);
res1 = find_resource(dev, PNP_IDX_IO1);
pc_keyboard_init(&conf->keyboard);
break;
#if 0
case PC97317_FDC:
{
unsigned reg;
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
break;
}
#endif
default:
break;
}
}
static void early_superio_config(void)
{
int timeout = 100000;
pnp_devfn_t dev = PNP_DEV(0x2e, 3);
pnp_write_config(dev, 0x29, 0x06);
while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--)
udelay(1000);
/* Enable COM1 */
pnp_set_logical_device(dev);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
pnp_set_enable(dev, 1);
}
static void init_acpi(struct device *dev)
{
u8 value;
int power_on = 1;
get_option(&power_on, "power_on_after_fail");
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
value = pnp_read_config(dev, 0xe4);
value &= ~(3 << 5);
if (power_on)
value |= (1 << 5);
pnp_write_config(dev, 0xe4, value);
pnp_exit_conf_mode(dev);
}
static void init_acpi(device_t dev)
{
u8 value = 0x20; /* TODO: 0x20 value here never used? */
int power_on = 1;
get_option(&power_on, "power_on_after_fail");
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
value = pnp_read_config(dev, 0xe4);
value &= ~(3 << 5);
if (power_on)
value |= (1 << 5);
pnp_write_config(dev, 0xe4, value);
pnp_exit_conf_mode(dev);
}
void xbus_cfg(pnp_devfn_t dev)
{
u8 i;
u16 xbus_index;
pnp_set_logical_device(dev);
/* Select proper BIOS size (4MB). */
pnp_write_config(dev, PC87417_XMEMCNF2,
(pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04);
xbus_index = pnp_read_iobase(dev, 0x60);
/* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */
for (i = 0; i <= 0xf; i++)
outb((i << 4), xbus_index + PC87417_HAP0);
}
static void set_irq_trigger_type(struct device *dev, bool trig_level)
{
u8 reg10, reg11, reg26;
//Before accessing CR10 OR CR11 Bit 4 in CR26 must be set to 1
reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
reg26 |= CR26_LOCK_REG;
pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26);
switch(dev->path.pnp.device) {
//SP1 (UARTA) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 5
case NCT5104D_SP1:
reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
if (trig_level)
reg10 |= (1 << 5);
else
reg10 &= ~(1 << 5);
pnp_write_config(dev, IRQ_TYPE_SEL_CR10, reg10);
break;
//SP2 (UARTB) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 4
case NCT5104D_SP2:
reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
if (trig_level)
reg10 |= (1 << 4);
else
reg10 &= ~(1 << 4);
pnp_write_config(dev, IRQ_TYPE_SEL_CR10, reg10);
break;
//SP3 (UARTC) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 5
case NCT5104D_SP3:
reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
if (trig_level)
reg11 |= (1 << 5);
else
reg11 &= ~(1 << 5);
pnp_write_config(dev, IRQ_TYPE_SEL_CR11, reg11);
break;
//SP4 (UARTD) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 4
case NCT5104D_SP4:
reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
if (trig_level)
reg11 |= (1 << 4);
else
reg11 &= ~(1 << 4);
pnp_write_config(dev, IRQ_TYPE_SEL_CR11, reg11);
break;
default:
break;
}
//Clear access control register
reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
reg26 &= ~CR26_LOCK_REG;
pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26);
}
static void lpc47n217_pnp_set_drq(device_t dev, u8 drq)
{
const u8 PP_DMA_MASK = 0x0F;
const u8 PP_DMA_SELECTION_REGISTER = 0x26;
u8 current_config, new_config;
if (dev->path.pnp.device == LPC47N217_PP) {
current_config = pnp_read_config(dev,
PP_DMA_SELECTION_REGISTER);
ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range? */
new_config = (current_config & ~PP_DMA_MASK) | drq;
pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
} else {
BUG();
}
}
void lpc47n227_pnp_set_drq(device_t dev, unsigned drq)
{
if (dev->path.pnp.device == LPC47N227_PP) {
const uint8_t PP_DMA_MASK = 0x0F;
const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
uint8_t current_config =
pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
uint8_t new_config;
ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range??
new_config = (current_config & ~PP_DMA_MASK) | drq;
pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
} else {
BUG();
}
}
static void init(struct device *dev)
{
if (!dev->enabled)
return;
switch(dev->path.pnp.device) {
case PC97317_KBCK:
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); /* Disable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */
pnp_set_enable(dev, 1); /* Enable keyboard */
pc_keyboard_init();
break;
default:
break;
}
}
void shc4307_init(void)
{
shc4307_enter_ext_func_mode(CMOS_DEV);
pnp_set_logical_device(CMOS_DEV); /* CMOS/RTC */
pnp_set_iobase(CMOS_DEV, PNP_IDX_IO0, 0x70);
pnp_set_iobase(CMOS_DEV, PNP_IDX_IO1, 0x72);
pnp_set_irq(CMOS_DEV, PNP_IDX_IRQ0, 8);
/* pnp_set_enable(CMOS_DEV, 3); */
pnp_write_config(CMOS_DEV, 0x30, 3);
pnp_set_logical_device(KBD_DEV); /* Keyboard */
pnp_set_irq(KBD_DEV, PNP_IDX_IRQ0, 1);
pnp_set_enable(KBD_DEV, 1);
pnp_set_logical_device(DBG_DEV); /* Debug */
pnp_set_iobase(DBG_DEV, PNP_IDX_IO0, 0x80);
pnp_set_enable(DBG_DEV, 1);
pnp_set_logical_device(REGS_DEV);
pnp_set_iobase(REGS_DEV, PNP_IDX_IO0, 0x600);
pnp_set_enable(REGS_DEV, 1);
shc4307_exit_ext_func_mode(CMOS_DEV);
}
