static void superio_init(void)
{
pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT);
/* Disable the watchdog. */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7);
pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00);
/* Enable the serial port. */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT);
}
static void early_superio_config(void)
{
pnp_devfn_t dev;
dev = PNP_DEV(0x4e, 0x00);
pnp_enter_ext_func_mode(dev);
pnp_write_register(dev, 0x02, 0x0e); // UART power
pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base
pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base
pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ
pnp_write_register(dev, 0x1e, 1); // no 32khz clock
pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ
pnp_write_register(dev, 0x2c, 0); // DMA0 FIR
pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR
pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
pnp_write_register(dev, 0x33, 0x0f); // GPIO2 DIR
pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
pnp_write_register(dev, 0x35, 0xa8); // GPIO3 DIR
pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
pnp_write_register(dev, 0x37, 0xa8); // GPIO4 DIR
pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
pnp_write_register(dev, 0x39, 0x00); // GPIO1 OUT
pnp_write_register(dev, 0x40, 0x80); // GPIO2/MISC OUT
pnp_write_register(dev, 0x41, 0x00); // GPIO5 OUT
pnp_write_register(dev, 0x42, 0xa8); // GPIO5 DIR
pnp_write_register(dev, 0x43, 0x00); // GPIO5 POL
pnp_write_register(dev, 0x44, 0x00); // GPIO ALT1
pnp_write_register(dev, 0x45, 0x50); // GPIO ALT2
pnp_write_register(dev, 0x46, 0x00); // GPIO ALT3
pnp_write_register(dev, 0x48, 0x55); // GPIO ALT5
pnp_write_register(dev, 0x49, 0x55); // GPIO ALT6
pnp_write_register(dev, 0x4a, 0x55); // GPIO ALT7
pnp_write_register(dev, 0x4b, 0x55); // GPIO ALT8
pnp_write_register(dev, 0x4c, 0x55); // GPIO ALT9
pnp_write_register(dev, 0x4d, 0x55); // GPIO ALT10
pnp_exit_ext_func_mode(dev);
}
static void early_superio_config(void)
{
device_t dev;
dev=PNP_DEV(0x2e, 0x00);
pnp_enter_ext_func_mode(dev);
pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes
pnp_write_register(dev, 0x02, 0x88); // UART power on
pnp_write_register(dev, 0x03, 0x72); // Floppy
pnp_write_register(dev, 0x04, 0x01); // EPP + SPP
pnp_write_register(dev, 0x14, 0x03); // Floppy
pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy
pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base
pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base
pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA
pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA
pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ
/* These are the SMI status registers in the SIO: */
pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR
pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR
pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR
pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR
pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL
pnp_exit_ext_func_mode(dev);
}
