static int mvgbe_write_hwaddr(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
/* Programs net device MAC address after initialization */
port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
return 0;
}
static int kwgbe_init(struct eth_device *dev)
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
kwgbe_init_rx_desc_ring(dkwgbe);
/* Clear the ethernet port interrupts */
KWGBEREG_WR(regs->ic, 0);
KWGBEREG_WR(regs->ice, 0);
/* Unmask RX buffer and TX end interrupt */
KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
/* Unmask phy and link status changes interrupts */
KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
set_dram_access(regs);
port_init_mac_tables(regs);
port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
/* Assign port configuration and command. */
KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
/* Disable port initially */
KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
/* Assign port SDMA configuration */
KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
/* Turn off the port/RXUQ bandwidth limitation */
KWGBEREG_WR(regs->pmtu, 0);
/* Set maximum receive buffer to 9700 bytes */
KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
| (KWGBEREG_RD(regs->psc0) & MRU_MASK));
/*
* Set ethernet MTU for leaky bucket mechanism to 0 - this will
* disable the leaky bucket mechanism .
*/
KWGBEREG_WR(regs->pmtu, 0);
/* Assignment of Rx CRDB of given RXUQ */
KWGBEREG_WR(regs->rxcdp[RXUQ].rxcdp, (u32) dkwgbe->p_rxdesc_curr);
/* Enable port Rx. */
KWGBEREG_WR(regs->rqc, (1 << RXUQ));
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
/* Wait up to 5s for the link status */
for (i = 0; i < 5; i++) {
u16 phyadr;
miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
/* Return if we get link up */
if (miiphy_link(dev->name, phyadr))
return 0;
udelay(1000000);
}
printf("No link on %s\n", dev->name);
return -1;
#endif
return 0;
}
