static void enable_cpu_power_partitions(void)
{
/* Bring up fast cluster, non-CPU, CPU0, and CPU1 partitions. */
power_ungate_partition(POWER_PARTID_CRAIL);
power_ungate_partition(POWER_PARTID_C0NC);
power_ungate_partition(POWER_PARTID_CE0);
power_ungate_partition(POWER_PARTID_CE1);
}
void soc_configure_i2c6pad(void)
{
/*
* I2C6 on Tegra124/132 requires some special init.
* The SOR block must be unpowergated, and a couple of
* display-based peripherals must be clocked and taken
* out of reset so that a DPAUX register can be
* configured to enable the I2C6 mux routing.
* Afterwards, we can disable clocks to the display blocks
* and put Host1X back in reset. DPAUX must remain out of
* reset and the SOR partition must remained unpowergated.
*/
power_ungate_partition(POWER_PARTID_SOR);
/* Host1X needs a valid clock source so DPAUX can be accessed */
clock_configure_source(host1x, PLLP, 204000);
enable_sor_periph_clocks();
remove_clamps(POWER_PARTID_SOR);
unreset_sor_periphs();
/* Now we can write the I2C6 mux in DPAUX */
write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
/*
* Delay before turning off Host1X/DPAUX clocks.
* This delay is needed to keep the sequence from
* hanging the system.
*/
udelay(CLOCK_PLL_STABLE_DELAY_US);
/* Stop Host1X/DPAUX clocks and reset Host1X */
disable_sor_periph_clocks();
clock_set_reset_l(CLK_L_HOST1X);
}
void soc_configure_host1x(void)
{
power_ungate_partition(POWER_PARTID_SOR);
/* Host1X needs a valid clock source so DPAUX can be accessed. */
clock_configure_source(host1x, PLLP, 204000);
enable_sor_periph_clocks();
remove_clamps(POWER_PARTID_SOR);
unreset_sor_periphs();
}
void power_enable_and_ungate_cpu(void)
{
/*
* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (150MHz),
* set it for 5ms as per SysEng (5ms * PCLK_KHZ * 1000 / 1s).
*/
write32(&pmc->cpupwrgood_timer, (TEGRA_PCLK_KHZ * 5));
uint32_t cntrl = read32(&pmc->cntrl);
cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY;
cntrl |= PMC_CNTRL_CPUPWRREQ_OE;
write32(&pmc->cntrl, cntrl);
power_ungate_partition(POWER_PARTID_CRAIL);
// Ungate power to the non-core parts of the fast cluster.
power_ungate_partition(POWER_PARTID_C0NC);
// Ungate power to CPU0 in the fast cluster.
power_ungate_partition(POWER_PARTID_CE0);
}
static void enable_cpu_power_partitions(void)
{
/* Bring up fast cluster, non-CPU, CPU0, CPU1, CPU2 and CPU3 parts. */
power_ungate_partition(POWER_PARTID_CRAIL);
power_ungate_partition(POWER_PARTID_C0NC);
power_ungate_partition(POWER_PARTID_CE0);
if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) {
/*
* Deassert reset signal of all the secondary CPUs.
* PMC and flow controller will take over the power sequence
* controller in the ATF.
*/
uint32_t reg = CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_DBG1 |
CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CX1 |
CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_DBG2 |
CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CX2 |
CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG3 |
CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX3;
write32(CLK_RST_REG(rst_cpug_cmplx_clr), reg);
}
}
