void jabber_change_status(GGaduStatusPrototype *sp, gboolean keep_desc)
{
enum states status;
LmMessage *m = NULL;
gchar *show = NULL;
gchar *show_away = "away";
gchar *show_xa = "xa";
gchar *show_dnd = "dnd";
gchar *show_chat = "chat";
print_debug("jabber_change_status start");
if (!sp)
return;
status = sp->status;
/* Just a simple esthetic functionality */
if((jabber_data.status == JABBER_STATUS_UNAVAILABLE) && sp->status == JABBER_STATUS_UNAVAILABLE)
{
GGaduStatusPrototype *sp_temp = ggadu_find_status_prototype(p, jabber_data.status);
sp_temp->status = JABBER_STATUS_UNAVAILABLE;
if(sp_temp->status_description)
{
g_free(sp_temp->status_description);
sp_temp->status_description = NULL;
}
signal_emit("jabber", "gui status changed", sp_temp, "main-gui");
GGaduStatusPrototype_free(sp_temp);
return;
}
if (status == JABBER_STATUS_UNAVAILABLE)
{
lm_connection_close(jabber_data.connection, NULL);
return;
}
/* connect if switched to any other than unavailable */
if ((jabber_data.status == JABBER_STATUS_UNAVAILABLE) && (status != JABBER_STATUS_UNAVAILABLE) &&
(!jabber_data.connection || !lm_connection_is_open(jabber_data.connection) ||
!lm_connection_is_authenticated(jabber_data.connection)))
{
g_thread_create(jabber_login_connect, (gpointer) status, FALSE, NULL);
return;
}
if (jabber_data.connection && !lm_connection_is_authenticated(jabber_data.connection))
{
print_debug("You are not yet authenticated!");
return;
}
m = lm_message_new_with_sub_type(NULL, LM_MESSAGE_TYPE_PRESENCE,
(status == JABBER_STATUS_UNAVAILABLE) ?
LM_MESSAGE_SUB_TYPE_UNAVAILABLE : LM_MESSAGE_SUB_TYPE_AVAILABLE);
/* switch (status == JABBER_STATUS_DESCR ? jabber_data.status : status) */
switch (status)
{
case JABBER_STATUS_AWAY:
show = show_away;
break;
case JABBER_STATUS_XA:
show = show_xa;
break;
case JABBER_STATUS_DND:
show = show_dnd;
break;
case JABBER_STATUS_CHAT:
show = show_chat;
break;
case JABBER_STATUS_AVAILABLE:
show = NULL;
break;
default:
break;
}
if (show)
lm_message_node_add_child(m->node, "show", show);
if(keep_desc)
{
if(sp->status_description) g_free(sp->status_description);
sp->status_description = g_strdup(jabber_data.description);
}
if(jabber_data.description)
{
g_free(jabber_data.description);
jabber_data.description = NULL;
}
if (sp->status_description)
{
print_debug("jabber: status description %s %s",sp->status_description,show);
lm_message_node_add_child(m->node, "status", sp->status_description);
jabber_data.description = g_strdup(sp->status_description);
}
print_debug(lm_message_node_to_string(m->node));
if (!lm_connection_send(jabber_data.connection, m, NULL))
{
print_debug("jabber: Couldn't change status!\n");
}
else
{
jabber_data.status = status;
signal_emit("jabber", "gui status changed", sp, "main-gui");
}
lm_message_unref(m);
print_debug("jabber_change_status end");
}
int camera_agent_set_flash_mode(camera_flash flash_mode)
{
u16 OpCode = ISPCMD_BASIC_SET_FLASHLIGHTMODE;
u32 cmd;
u8 buf[1]={0};
int errorcode;
#if debug_flicker
u8 mode = 0;
switch(flash_mode)
{
case CAMERA_FLASH_ON:
mode = 0;
break;
case CAMERA_FLASH_TORCH:
mode = 3;
break;
case CAMERA_FLASH_OFF:
mode = 1;
break;
case CAMERA_FLASH_AUTO:
mode = 2;
break;
default:
buf[0] = 1;
break;
}
camera_agent_set_ANTIFLICKER(0,mode);
#endif
#if debug_focus_mode
u8 mode = 0;
switch(flash_mode)
{
case CAMERA_FLASH_ON:
mode = 2;
break;
case CAMERA_FLASH_TORCH:
mode = 1;
break;
case CAMERA_FLASH_OFF:
mode = 4;//manual af
break;
case CAMERA_FLASH_AUTO:
mode = 0;
break;
default:
mode = 0;
break;
}
camera_agent_set_focusmode(0,mode);
#endif
#if debug_ae_mode
u8 mode = 0;
switch(flash_mode)
{
case CAMERA_FLASH_ON:
mode = 1;
break;
case CAMERA_FLASH_TORCH:
mode = 2;
break;
case CAMERA_FLASH_OFF:
mode = 3;
break;
case CAMERA_FLASH_AUTO:
mode = 0;
break;
default:
buf[0] = 1;
break;
}
camera_agent_set_ae_mode(0,mode);
#endif
#if debug_exposure_gain
u32 expo = 0;
u8 gain = 0;
switch(flash_mode)
{
case CAMERA_FLASH_ON:
expo = 10000;
gain = 100;
break;
case CAMERA_FLASH_TORCH:
expo = 10000;
gain = 100;
break;
case CAMERA_FLASH_OFF:
expo = 10;
gain = 100;
break;
case CAMERA_FLASH_AUTO:
expo = 0;
gain = 0;
break;
default:
expo = 0;
gain = 0;
break;
}
camera_agent_set_exposuretime(expo);
camera_agent_set_ADgain(gain);
#endif
print_debug("Enter Function:%s ", __func__);
cmd = misp_construct_opcode(OpCode,SET_CMD,sizeof(buf));
switch(flash_mode)
{
case CAMERA_FLASH_ON:
buf[0] = 8;
break;
case CAMERA_FLASH_TORCH:
buf[0] = 1;
break;
case CAMERA_FLASH_OFF:
buf[0] = 1;
break;
case CAMERA_FLASH_AUTO:
buf[0] = 4;
break;
default:
buf[0] = 4;
break;
}
print_debug("flash_mode = %d ", buf[0]);
errorcode = misp_exec_cmd(cmd,buf);
if (errorcode) {
print_error("%s fail, error code = %d", __func__, errorcode);
return -1;
}
return 0;
}
int mini_isp_debug_load_cfg(char *cfg_file,char *key_name,u8 *key_var)
{
struct kstat stat;
mm_segment_t fs;
struct file *fp = NULL;
int file_flag = O_RDONLY;
ssize_t ret = 0;
char temp_array[64] = {0};
char temp;
int cnt=0;
bool bRegStart = false;
bool bKeyFound = false;
bool bKeyCfg = false;
print_debug("enter %s", __func__);
if (NULL == cfg_file) {
print_error("%s cfg_file null ptr.", __func__);
return -EINVAL;
}
if (NULL == key_name) {
print_error("%s key_name null ptr.", __func__);
return -EINVAL;
}
if (NULL == key_var) {
print_error("%s key_var null ptr.", __func__);
return -EINVAL;
}
/* must have the following 2 statement */
fs = get_fs();
set_fs(KERNEL_DS);
fp = filp_open(cfg_file, file_flag, 0666);
if (IS_ERR_OR_NULL(fp)) {
print_debug("no debug configuration file(%s) - do nothing, just skip it!\n",cfg_file);
return -1;
}
if (0 != vfs_stat(cfg_file, &stat)) {
print_error("failed to get file %s state!",cfg_file);
goto ERROR;
}
print_debug("%s size : %d",cfg_file, (u32)stat.size);
while (0 < vfs_read(fp, &temp, 1, &fp->f_pos)) {
switch (temp) {
case '{':
bRegStart = true;
cnt = 0;
bKeyFound = false;
memset(temp_array,sizeof(char),sizeof(temp_array));
break;
case '}':
bRegStart = false;
if(bKeyFound)
{
*key_var = mini_atoi16(temp_array);
bKeyCfg = true;
print_debug("%s:0x%x",key_name,*key_var);
}
break;
case '=':
if (bRegStart)
{
bKeyFound = false;
if (0 == strncmp(key_name,temp_array,strlen(key_name)))
{
bKeyFound = true;
}
cnt = 0;
}
break;
default:
if (bRegStart){
if (cnt >= 64)
{
bRegStart = false;
}
else
{
temp_array[cnt] = temp;
cnt=cnt+1;
}
}
break;
}
if (bKeyCfg)
{
break;
}
}
/* must have the following 1 statement */
set_fs(fs);
ERROR:
if (NULL != fp)
filp_close(fp, 0);
return ret;
}
static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat)
{
u8 Channel;
u32 TestAddr0;
u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0;
u16 MaxRdLatDly;
u8 RcvrEnDly = 0;
u32 PatternBuffer[60]; // FIXME: why not 48 + 4
u32 Margin;
u32 addr;
u32 cr4;
u32 lo, hi;
u8 valid;
u32 pattern_buf;
cr4 = read_cr4();
if(cr4 & (1<<9)) { /* save the old value */
_SSE2 = 1;
}
cr4 |= (1<<9); /* OSFXSR enable SSE2 */
write_cr4(cr4);
addr = HWCR;
_RDMSR(addr, &lo, &hi);
if(lo & (1<<17)) { /* save the old value */
_Wrap32Dis = 1;
}
lo |= (1<<17); /* HWCR.wrap32dis */
lo &= ~(1<<15); /* SSEDIS */
/* Setting wrap32dis allows 64-bit memory references in
real mode */
_WRMSR(addr, lo, hi);
_DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat);
pattern_buf = SetupMaxRdPattern(pMCTstat, pDCTstat, PatternBuffer);
for (Channel = 0; Channel < 2; Channel++) {
print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1);
pDCTstat->Channel = Channel;
if( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel)
break; /*if ganged mode, skip DCT 1 */
TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid);
if(!valid) /* Address not supported on current CS */
continue;
/* rank 1 of DIMM, testpattern 0 */
WriteMaxRdLat1CLTestPattern_D(pattern_buf, TestAddr0);
MaxRdLatDly = mct_GetStartMaxRdLat_D(pMCTstat, pDCTstat, Channel, RcvrEnDly, &Margin);
print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly start ", MaxRdLatDly, 2);
print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly Margin ", Margin, 2);
while(MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */
mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly);
ReadMaxRdLat1CLTestPattern_D(TestAddr0);
if( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS)
break;
SetTargetWTIO_D(TestAddr0);
FlushMaxRdLatTestPattern_D(TestAddr0);
ResetTargetWTIO_D();
MaxRdLatDly++;
}
print_debug_dqs("\tMaxRdLatencyTrain53: MaxRdLatDly end ", MaxRdLatDly, 2);
mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly + Margin);
}
if(_DisableDramECC) {
mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);
}
if(!_Wrap32Dis) {
addr = HWCR;
_RDMSR(addr, &lo, &hi);
lo &= ~(1<<17); /* restore HWCR.wrap32dis */
_WRMSR(addr, lo, hi);
}
if(!_SSE2){
cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
}
#if DQS_TRAIN_DEBUG > 0
{
u8 Channel;
print_debug("maxRdLatencyTrain: CH_MaxRdLat:\n");
for(Channel = 0; Channel<2; Channel++) {
print_debug("Channel:"); print_debug_hex8(Channel);
print_debug(": ");
print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] );
print_debug("\n");
}
}
#endif
}
/*---------------------------------------------------------------------------*/
static void
handle_incoming_rrep(void)
{
struct uaodv_msg_rrep *rm = (struct uaodv_msg_rrep *)uip_appdata;
struct uaodv_rt_entry *rt;
/* Useless HELLO message? */
if(uip_ipaddr_cmp(&BUF->destipaddr, &uip_broadcast_addr)) {
#ifdef AODV_RESPOND_TO_HELLOS
u32_t net_seqno;
#ifdef CC2420_RADIO
int ret = cc2420_check_remote(uip_udp_sender()->u16[1]);
if(ret == REMOTE_YES) {
print_debug("HELLO drop is remote\n");
return;
} else if (ret == REMOTE_NO) {
/* Is neigbour, accept it. */
} else if(cc2420_last_rssi < RSSI_THRESHOLD) {
print_debug("HELLO drop %d %d\n", cc2420_last_rssi, cc2420_last_correlation);
return;
}
#endif
/* Sometimes it helps to send a non-requested RREP in response! */
net_seqno = htonl(my_hseqno);
send_rrep(&uip_hostaddr, &BUF->srcipaddr, &BUF->srcipaddr, &net_seqno, 0);
#endif
return;
}
print_debug("RREP %d.%d.%d.%d -> %d.%d.%d.%d"
" dest=%d.%d.%d.%d seq=%lu hops=%u orig=%d.%d.%d.%d\n",
uip_ipaddr_to_quad(&BUF->srcipaddr),
uip_ipaddr_to_quad(&BUF->destipaddr),
uip_ipaddr_to_quad(&rm->dest_addr), ntohl(rm->dest_seqno),
rm->hop_count,
uip_ipaddr_to_quad(&rm->orig_addr));
rt = uaodv_rt_lookup(&rm->dest_addr);
/* New forward route? */
if(rt == NULL || (SCMP32(ntohl(rm->dest_seqno), rt->hseqno) > 0)) {
print_debug("Inserting3\n");
rt = uaodv_rt_add(&rm->dest_addr, uip_udp_sender(),
rm->hop_count, &rm->dest_seqno);
#ifdef CC2420_RADIO
/* This link is ok since he is unicasting back to us! */
cc2420_recv_ok(uip_udp_sender());
print_debug("RREP recv ok %d %d\n",
cc2420_last_rssi, cc2420_last_correlation);
#endif
} else {
print_debug("Not inserting\n");
}
/* Forward RREP towards originator? */
if(uip_ipaddr_cmp(&rm->orig_addr, &uip_hostaddr)) {
print_debug("ROUTE FOUND\n");
if(rm->flags & UAODV_RREP_ACK) {
struct uaodv_msg_rrep_ack *ack = (void *)uip_appdata;
ack->type = UAODV_RREP_ACK_TYPE;
ack->reserved = 0;
sendto(uip_udp_sender(), ack, sizeof(*ack));
}
} else {
rt = uaodv_rt_lookup(&rm->orig_addr);
if(rt == NULL) {
print_debug("RREP received, but no route back to originator... :-( \n");
return;
}
if(rm->flags & UAODV_RREP_ACK) {
print_debug("RREP with ACK request (ignored)!\n");
/* Don't want any RREP-ACKs in return! */
rm->flags &= ~UAODV_RREP_ACK;
}
rm->hop_count++;
print_debug("Fwd RREP to %d.%d.%d.%d\n", uip_ipaddr_to_quad(&rt->nexthop));
sendto(&rt->nexthop, rm, sizeof(struct uaodv_msg_rrep));
}
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
uint8_t tmp = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
pnp_enter_ext_func_mode(SERIAL_DEV);
/* The following line will set CLKIN to 24 MHz, external */
pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
/* Is serial flash enabled? Then enable writing to serial flash. */
if (tmp & 0x0e) {
pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
pnp_set_logical_device(GPIO_DEV);
/* Set Serial Flash interface to 0x0820 */
pnp_write_config(GPIO_DEV, 0x64, 0x08);
pnp_write_config(GPIO_DEV, 0x65, 0x20);
}
it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
setup_mb_resource_map();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
init_timer(); // Need to use TMICT to synconize FID/VID
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
/* all ap stopped? */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
int Cconfigurator::loadConfig(QByteArray path, QByteArray filename)
{
int size;
QSettings conf(path + filename, QSettings::IniFormat);
conf.beginGroup("General");
setBaseFile( conf.value("mapFile", "database/mume.pmf").toByteArray() );
setWindowRect( conf.value("windowRect").toRect() );
setAlwaysOnTop( conf.value("alwaysOnTop", true ).toBool() );
setStartupMode( conf.value("startupMode", 1).toInt() );
setLogFileEnabled( conf.value("isLogFileEnabled", false).toBool() );
conf.endGroup();
conf.beginGroup("Networking");
setLocalPort( conf.value("localPort", 4242).toInt() );
setRemoteHost( conf.value("remoteHost", "193.134.218.111").toByteArray() );
setRemotePort( conf.value("remotePort", 443).toInt() );
conf.endGroup();
conf.beginGroup("OpenGL");
setTextureVisibility( conf.value("texturesVisibility", 500).toInt() );
setDetailsVisibility( conf.value("detailsVisibility", 300).toInt() );
setVisibleLayers( conf.value("visibleLayers", 5).toInt() );
setShowNotesRenderer( conf.value("showNotes", true).toBool() );
setShowRegionsInfo( conf.value("showRegions", false). toBool() );
setDisplayRegionsRenderer( conf.value("displayRegions", false).toBool() );
setMultisampling( conf.value("multisampling", true).toBool() );
setSelectOAnyLayer( conf.value("selectOnAnyLayer", true).toBool() );
setRendererAngles(conf.value("angleX", 0).toFloat(), conf.value("angleY", 0).toFloat(), conf.value("angleZ", 0).toFloat());
setRendererPosition(conf.value("userX", 0).toFloat(), conf.value("userY", 0).toFloat(), conf.value("userZ", 0).toFloat());
setNoteColor( conf.value("noteColor", "#F28003").toByteArray() );
setDrawPrespam( conf.value("drawPrespam", true).toBool() );
conf.endGroup();
conf.beginGroup("Engine");
setExitsCheck( conf.value("checkExits", false).toBool() );
setTerrainCheck( conf.value("checkTerrain", true).toBool() );
setBriefMode( conf.value("briefmode", true ).toBool() );
setAutomerge( conf.value("autoMerge", true ).toBool() );
setAngrylinker( conf.value("angryLinker", true ).toBool() );
setDuallinker( conf.value("dualLinker", false ).toBool() );
setAutorefresh( conf.value("autoRefresh", true ).toBool() );
setNameQuote( conf.value("roomNameQuote", 10 ).toInt() );
setDescQuote( conf.value("descQuote", 10 ).toInt() );
setRegionsAutoReplace( conf.value("regionsAutoReplace", false ).toBool() );
setRegionsAutoSet( conf.value("regionsAutoSet", false ).toBool() );
setMactionUsesPrespam( conf.value("mactionUsesPrespam", true).toBool() );
setPrespamTTL( conf.value("prespamTTL", 5000).toInt() );
conf.endGroup();
conf.beginGroup("Patterns");
setExitsPattern( conf.value("exitsPattern", "Exits: ").toByteArray() );
spells_pattern = conf.value("spellsEffectPattern", "Affected by:").toByteArray();
setScorePattern( conf.value("scorePattern", "[0-9]*/* hits, */* mana, and */* moves.").toByteArray() );
setShortScorePattern( conf.value("scorePatternShort", "[0-9]*/* hits and */* moves.").toByteArray() );
conf.endGroup();
conf.beginGroup("GroupManager");
setGroupManagerHost( conf.value("remoteHost", "localhost").toByteArray() );
setGroupManagerRemotePort( conf.value("remotePort", 4243 ).toInt() );
setGroupManagerLocalPort( conf.value("localServerPort", 4243 ).toInt() );
setGroupManagerCharName( conf.value("charName", "Charname" ).toByteArray() );
setGroupManagerColor( QColor( conf.value("charColor", "#F28003").toString() ) );
setGroupManagerShowSelf( conf.value("showSelf", false ).toBool() );
setGroupManagerNotifyArmour( conf.value("notifyArm", true ).toBool() );
setGroupManagerNotifySanc( conf.value("notifySanc", true ).toBool() );
setGroupManagerNotifyBash( conf.value("notifyBash", true ).toBool() );
setGroupManagerShowManager( conf.value("showGroupManager", true ).toBool() );
setGroupManagerRect( conf.value("windowRect").toRect() );
conf.endGroup();
size = conf.beginReadArray("Spells");
for (int i = 0; i < size; ++i) {
conf.setArrayIndex(i);
TSpell spell;
spell.up = false;
spell.silently_up = false;
spell.addon = conf.value("addon", 0).toBool();
spell.name = conf.value("name").toByteArray();
spell.up_mes = conf.value("upMessage").toByteArray();
spell.refresh_mes = conf.value("refreshMessage").toByteArray();
spell.down_mes = conf.value("downMessage").toByteArray();
addSpell(spell);
}
conf.endArray();
conf.beginGroup("Movement tracking");
size = conf.beginReadArray("Cancel Patterns");
for (int i = 0; i < size; ++i) {
conf.setArrayIndex(i);
moveCancelPatterns.append( conf.value("pattern").toByteArray() );
}
conf.endArray();
size = conf.beginReadArray("Force Patterns");
for (int i = 0; i < size; ++i) {
conf.setArrayIndex(i);
moveForcePatterns.append( conf.value("pattern").toByteArray() );
}
conf.endArray();
conf.endGroup();
size = conf.beginReadArray("Debug Settings");
for (int i = 0; i < size; ++i) {
conf.setArrayIndex(i);
QString s = conf.value("name").toString();
unsigned int z = 0;
while (debug_data[z].name != NULL) {
if (debug_data[z].name == s)
break;
z++;
}
if (debug_data[z].name == NULL) {
print_debug(DEBUG_CONFIG, "Warning, %s is a wrong debug descriptor/name!", qPrintable(s));
continue;
}
debug_data[i].state = conf.value("state", 0 ).toInt();
}
conf.endArray();
configFile = filename;
configPath = path;
setConfigModified(false);
return true;
}
void CEngine::tryDir()
{
unsigned int i;
CRoom *room;
CRoom *candidate;
nameMatch = 0;
descMatch = 0;
print_debug(DEBUG_ANALYZER, "in try_dir");
ExitDirection dir = numbydir(event.dir[0]);
if (dir == ED_UNKNOWN) {
print_debug(DEBUG_ANALYZER, "Error in try_dir - faulty DIR given as input!\r\n");
return;
}
CCommand cmd = commandQueue.peek();
if (cmd.timer.elapsed() > conf->getPrespamTTL() ) {
print_debug(DEBUG_ANALYZER, "The command queue has head entry with lifetime over limit. Resetting");
commandQueue.clear();
toggle_renderer_reaction();
} else if (cmd.dir == dir && !event.fleeing ) {
// we moved in awaited direction
commandQueue.dequeue();
}
if (stacker.amount() == 0) {
print_debug(DEBUG_ANALYZER, "leaving. No candidates in stack to check. This results in FULL RESYNC.");
return;
}
for (i = 0; i < stacker.amount(); i++) {
room = stacker.get(i);
if (room->isConnected(dir)) {
candidate = room->getExitRoom(dir);
if (testRoom(candidate) ) {
stacker.put(candidate);
}
} else {
if (stacker.amount() == 1 && mapping) {
print_debug(DEBUG_ANALYZER, "Going to add new room...");
mapCurrentRoom(room, dir);
return;
}
}
}
/* roomname update */
if (stacker.next() == 1) {
/* this means we have exactly one match */
// printf("nameMatch %i, descMatch %i\r\n", nameMatch, descMatch);
if (nameMatch > 0) {
/* Autorefresh only if case has been changed. */
if (conf->getAutorefresh() && event.name.toLower() == stacker.nextFirst()->getName().toLower()) {
send_to_user("--[ (AutoRefreshed) not exact room name match: %i errors.\r\n", nameMatch);
stacker.nextFirst()->setName(event.name);
} else {
send_to_user("--[ not exact room name match: %i errors. Use 'mrefresh' to fix it!\r\n", nameMatch);
}
}
if (conf->getAutorefresh() && descMatch > 0) {
send_to_user("--[ (AutoRefreshed) not exact room desc match: %i errors.\r\n", descMatch);
stacker.nextFirst()->setDesc(event.desc);
} else if (!conf->getAutorefresh() && descMatch > 0) {
send_to_user("--[ not exact room desc match: %i errors.\r\n", descMatch);
}
}
print_debug(DEBUG_ANALYZER, "leaving tryDir");
}
void CEngine::parseEvent()
{
print_debug(DEBUG_ANALYZER, "in parseEvent()");
if (event.movementBlocker) {
// notify renderer to remove all the unnecessary line drawn
commandQueue.dequeue();
toggle_renderer_reaction();
return;
}
if (event.name != "") {
print_debug(DEBUG_ANALYZER, "Converting Room Name to ascii format");
latinToAscii( event.name);
last_name = event.name;
}
if (event.desc != "") {
print_debug(DEBUG_ANALYZER, "Converting Description to ascii format");
latinToAscii( event.desc );
last_desc = event.desc;
}
if (event.exits != "") {
last_exits = event.exits;
}
if (event.terrain != -1) {
last_terrain = event.terrain;
}
setMgoto( false ); /* if we get a new room data incoming, mgoto has to go away */
print_debug(DEBUG_ANALYZER, "Entering the main part of the function");
print_debug(DEBUG_ANALYZER, "ANALYZER Event. \r\nNAME %s\r\nDESC %s\r\nEXITS %s\r\nBLIND %i, MOVEMENT %i SCOUT %i",
(const char *) event.name, (const char *) event.desc, (const char *) event.exits
/*(const char *) event.prompt*/, event.blind, event.movement, event.scout);
if (event.scout) {
print_debug(DEBUG_ANALYZER, "SCOUT flag is set. Dropping event");
return;
}
if (event.name.indexOf("It is pitch black...") == 0) {
print_debug(DEBUG_ANALYZER, "NO light BLIND set");
event.blind = true;
}
if (event.name == "" && event.movement == true) {
print_debug(DEBUG_ANALYZER, "NAME is empty and Movement is true. Assuming BLIND");
event.blind = true;
}
if (event.name == "" && event.blind == false) {
print_debug(DEBUG_ANALYZER, "EMPTY name and no blind set. Assuming addedroom-data update incoming.");
if (addedroom) {
addedroom->setTerrain(last_terrain);
resetAddedRoomVar();
toggle_renderer_reaction();
}
return;
}
if (event.movement == true) {
last_movement = event.dir;
if (event.dir =="") {
tryAllDirs();
// command's queue is useless then, no?
commandQueue.clear();
} else {
tryDir();
}
} else {
if (event.name != "")
tryLook();
}
swap();
if (stacker.amount() == 0)
resync();
print_debug(DEBUG_ANALYZER, "Done. Sending an event to the Renderer");
toggle_renderer_reaction();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
post_code(0x30);
agesawrapper_amdinitmmio();
post_code(0x31);
/* Halt if there was a built in self test failure */
post_code(0x33);
report_bist_failure(bist);
sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE);
sb7xx_51xx_disable_wideio(0);
post_code(0x34);
post_code(0x35);
console_init();
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
post_code(0x37);
val = agesawrapper_amdinitreset();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
}
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x38);
/*
* SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
* Disable all Pcie Bridges to work around It.
*/
sr56x0_rd890_disable_pcie_bridge();
post_code(0x39);
nb_Poweron_Init();
post_code(0x3A);
sb_Poweron_Init();
}
post_code(0x3B);
val = agesawrapper_amdinitearly();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
}
post_code(0x3C);
nb_Ht_Init();
post_code(0x3D);
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
distinguish_cpu_resets(0);
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
post_code(0x40);
val = agesawrapper_amdinitpost();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
}
post_code(0x41);
val = agesawrapper_amdinitenv();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
}
printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
post_code(0x42);
post_code(0x50);
print_debug("Disabling cache as ram ");
disable_cache_as_ram();
print_debug("done\n");
post_code(0x51);
copy_and_run();
/* We will not return, Should never see this message and post code. */
print_debug("should not be here -\n");
post_code(0x54);
}
/**
* Executes a rule. Contains evaluation of all conditions prior
* to execution.
*
* @1 Hotplug event structure
* @2 The rule to be executed
*
* Returns: 0 if success, -1 if the whole event is to be
* discared, 1 if bail out of this particular rule was required
*/
int rule_execute(struct hotplug2_event_t *event, struct rule_t *rule) {
int i, last_rv, res;
char **env;
for (i = 0; i < rule->conditions_c; i++) {
if (rule_condition_eval(event, &(rule->conditions[i])) != EVAL_MATCH)
return 0;
}
res = 0;
last_rv = 0;
env = xmalloc(sizeof(char *) * event->env_vars_c);
for (i = 0; i < event->env_vars_c; i++) {
env[i] = alloc_env(event->env_vars[i].key, event->env_vars[i].value);
putenv(env[i]);
}
for (i = 0; i < rule->actions_c; i++) {
switch (rule->actions[i].type) {
case ACT_STOP_PROCESSING:
res = 1;
break;
case ACT_STOP_IF_FAILED:
if (last_rv != 0)
res = 1;
break;
case ACT_NEXT_EVENT:
res = -1;
break;
case ACT_NEXT_IF_FAILED:
if (last_rv != 0)
res = -1;
break;
case ACT_MAKE_DEVICE:
last_rv = make_dev_from_event(event, rule->actions[i].parameter[0], strtoul(rule->actions[i].parameter[1], NULL, 0));
break;
case ACT_CHMOD:
last_rv = chmod_file(event, rule->actions[i].parameter[0], rule->actions[i].parameter[1]);
break;
case ACT_CHOWN:
case ACT_CHGRP:
last_rv = chown_chgrp(event, rule->actions[i].type, rule->actions[i].parameter[0], rule->actions[i].parameter[1]);
break;
case ACT_SYMLINK:
last_rv = make_symlink(event, rule->actions[i].parameter[0], rule->actions[i].parameter[1]);
break;
case ACT_RUN_SHELL:
last_rv = exec_shell(event, rule->actions[i].parameter[0]);
break;
case ACT_RUN_NOSHELL:
last_rv = exec_noshell(event, rule->actions[i].parameter[0], rule->actions[i].parameter);
break;
case ACT_SETENV:
last_rv = setenv(rule->actions[i].parameter[0], rule->actions[i].parameter[1], 1);
break;
case ACT_REMOVE:
last_rv = unlink(rule->actions[i].parameter[0]);
rmdir_p(rule->actions[i].parameter[0]);
break;
case ACT_DEBUG:
print_debug(event);
last_rv = 0;
break;
}
if (res != 0)
break;
}
for (i = 0; i < event->env_vars_c; i++) {
unsetenv(event->env_vars[i].key);
free(env[i]);
}
free(env);
return res;
}
static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu)
{
unsigned int actual_rate = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_CLOCK_RATE);
print_debug("cpu%d: freq=%d\n", cpu, actual_rate);
return actual_rate <= bcm2835_freq_table[0].frequency ? bcm2835_freq_table[0].frequency : bcm2835_freq_table[1].frequency;
}
/*
=============
Module exit
=============
*/
static void __exit bcm2835_cpufreq_module_exit(void)
{
print_debug("IN\n");
cpufreq_unregister_driver(&bcm2835_cpufreq_driver);
return;
}
/*
====================================================
Module Initialisation registers the cpufreq driver
====================================================
*/
static int __init bcm2835_cpufreq_module_init(void)
{
print_debug("IN\n");
return cpufreq_register_driver(&bcm2835_cpufreq_driver);
}
static void vt8237s_vlink_init(struct device *dev)
{
u8 reg;
device_t devfun7;
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
/* No pairing NB was found. */
if (!devfun7)
{
print_debug("vt8237s_vlink_init: No pairing NB was found.\n");
return;
}
/*
* This init code is valid only for the VT8237S! For different
* sounthbridges (e.g. VT8237A, VT8237S, VT8237R (without plus R)
* and VT8251) a different init code is required.
*/
/* disable auto disconnect */
reg = pci_read_config8(devfun7, 0x42);
reg &= ~0x4;
pci_write_config8(devfun7, 0x42, reg);
/* NB part setup */
pci_write_config8(devfun7, 0xb5, 0x66);
pci_write_config8(devfun7, 0xb6, 0x66);
pci_write_config8(devfun7, 0xb7, 0x64);
reg = pci_read_config8(devfun7, 0xb4);
reg |= 0x1;
reg &= ~0x10;
pci_write_config8(devfun7, 0xb4, reg);
pci_write_config8(devfun7, 0xb0, 0x6);
pci_write_config8(devfun7, 0xb1, 0x1);
/* SB part setup */
pci_write_config8(dev, 0xb7, 0x60);
pci_write_config8(dev, 0xb9, 0x88);
pci_write_config8(dev, 0xba, 0x88);
pci_write_config8(dev, 0xbb, 0x89);
reg = pci_read_config8(dev, 0xbd);
reg |= 0x3;
reg &= ~0x4;
pci_write_config8(dev, 0xbd, reg);
reg = pci_read_config8(dev, 0xbc);
reg &= ~0x7;
pci_write_config8(dev, 0xbc, reg);
/* Program V-link 8X 8bit full duplex, parity enabled. */
pci_write_config8(dev, 0x48, 0x23 | 0x80);
/* enable auto disconnect, for STPGNT and HALT */
reg = pci_read_config8(devfun7, 0x42);
reg |= 0x7;
pci_write_config8(devfun7, 0x42, reg);
}
// where from where to ... map it!
void CEngine::mapCurrentRoom(CRoom *room, ExitDirection dir)
{
print_debug(DEBUG_ANALYZER, "in mapCurrentRoom");
/* casual checks for data */
if (event.blind) {
send_to_user( "--[Pandora: Failed to add new room. Blind !\r\n");
mappingOff();
return;
} else if (event.name == "") {
send_to_user( "--[Pandora: Failed to add new room. Missing roomname!\r\n");
mappingOff();
return;
} else if (event.desc == "") {
send_to_user( "--[Pandora: Failed to add new room. Missing description!\r\n");
mappingOff();
return;
} else if (event.exits == "") {
send_to_user( "--[Pandora: Failed to add new room. Missing exits data!\r\n");
mappingOff();
return;
}
send_to_user("--[ Adding new room!\n");
int x = room->getX();
int y = room->getY();
int z = room->getZ();
if (dir == ED_NORTH)
y += 2;
if (dir == ED_SOUTH)
y -= 2;
if (dir == ED_EAST)
x+= 2;
if (dir == ED_WEST)
x -= 2;
if (dir == ED_UP)
z += 2;
if (dir == ED_DOWN)
z -= 2;
addedroom = map->createRoom(event.name, event.desc, x, y, z);
addedroom->setRegion( users_region );
room->setExitLeadsTo(dir, addedroom);
if (conf->getDuallinker() == true)
addedroom->setExitLeadsTo(reversenum(dir), room);
else
map->oneway_room_id = room->getId();
setExits(event.exits);
do_exits((const char *) event.exits);
//stacker.put(addedroom);
CRoom *checkedDups = map->isDuplicate(addedroom);
if (checkedDups == NULL) {
resetAddedRoomVar();
} else {
stacker.put(checkedDups);
if (checkedDups == addedroom) {
// was not a duplicate, so see what angryLinker might be able to achieve
angryLinker(addedroom);
} else {
resetAddedRoomVar();
send_to_user("--[Pandora: Twin rooms merged!\n");
proxy->send_line_to_user( (const char *) last_prompt );
print_debug(DEBUG_ANALYZER, "Twins merged");
}
}
print_debug(DEBUG_ANALYZER, "leaving mapCurrentRoom");
return;
}
static void vt8237a_vlink_init(struct device *dev)
{
u8 reg;
device_t devfun7;
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
/* No pairing NB was found. */
if (!devfun7)
{
print_debug("vt8237a_vlink_init: No pairing NB was found.\n");
return;
}
/*
* This init code is valid only for the VT8237A! For different
* sounthbridges (e.g. VT8237S, VT8237R and VT8251) a different
* init code is required.
*
* FIXME: This is based on vt8237r_vlink_init() in
* k8t890/k8t890_ctrl.c and modified to fit what the AMI
* BIOS on my M2V wrote to these registers (by looking
* at lspci -nxxx output).
* Works for me.
*/
/* disable auto disconnect */
reg = pci_read_config8(devfun7, 0x42);
reg &= ~0x4;
pci_write_config8(devfun7, 0x42, reg);
/* NB part setup */
pci_write_config8(devfun7, 0xb5, 0x88);
pci_write_config8(devfun7, 0xb6, 0x88);
pci_write_config8(devfun7, 0xb7, 0x61);
reg = pci_read_config8(devfun7, 0xb4);
reg |= 0x11;
pci_write_config8(devfun7, 0xb4, reg);
pci_write_config8(devfun7, 0xb0, 0x6);
pci_write_config8(devfun7, 0xb1, 0x1);
/* SB part setup */
pci_write_config8(dev, 0xb7, 0x50);
pci_write_config8(dev, 0xb9, 0x88);
pci_write_config8(dev, 0xba, 0x8a);
pci_write_config8(dev, 0xbb, 0x88);
reg = pci_read_config8(dev, 0xbd);
reg |= 0x3;
reg &= ~0x4;
pci_write_config8(dev, 0xbd, reg);
reg = pci_read_config8(dev, 0xbc);
reg &= ~0x7;
pci_write_config8(dev, 0xbc, reg);
pci_write_config8(dev, 0x48, 0x23);
/* enable auto disconnect, for STPGNT and HALT */
reg = pci_read_config8(devfun7, 0x42);
reg |= 0x7;
pci_write_config8(devfun7, 0x42, reg);
}
void CEngine::angryLinker(CRoom *r)
{
CRoom *p;
unsigned int i;
CRoom *candidates[6];
int distances[6];
int z;
if (!conf->getAngrylinker())
return;
print_debug(DEBUG_ROOMS && DEBUG_ANALYZER, "in AngryLinker");
if (r == NULL) {
print_debug(DEBUG_ROOMS, "given room is NULL");
return;
}
if (r->anyUndefinedExits() != true) {
print_debug(DEBUG_ROOMS, "returning, no undefined exits in room found");
return; /* no need to try and link this room - there are no undefined exits */
}
/* reset the data */
for (i=0; i <= 5; i++) {
distances[i] = 15000;
candidates[i] = 0;
}
z = 0;
// if you are performing the full run over all rooms, it's better
// to lock the Map completely.
// else the other thread might delete the room you are examining at the moment!
//map->lockForWrite();
QVector<CRoom *> rooms = map->getRooms();
/* find the closest neighbours by coordinate */
for (i = 0; i < map->size(); i++) {
p = rooms[i];
/* z-axis: up and down exits */
if (p->getZ() != r->getZ()) {
if ((p->getX() != r->getX()) || (p->getY() != r->getY()))
continue;
/* up exit */
if (p->getZ() > r->getZ()) {
z = p->getZ() - r->getZ();
if (z < distances[ED_UP]) {
/* update */
distances[ED_UP] = z;
candidates[ED_UP] = p;
}
}
/* DOWN exit */
if (r->getZ() > p->getZ()) {
z = r->getZ() - p->getZ();
if (z < distances[ED_DOWN]) {
/* update */
distances[ED_DOWN] = z;
candidates[ED_DOWN] = p;
}
}
}
/* done with z-axis */
/* x-axis. */
if ((p->getY() == r->getY()) && (p->getZ() == r->getZ())) {
if (p->getX() == r->getX())
continue; /* all coordinates are the same - skip */
/* EAST exit */
if (p->getX() > r->getX()) {
z = p->getX() - r->getX();
if (z < distances[ED_EAST]) {
/* update */
distances[ED_EAST] = z;
candidates[ED_EAST] = p;
}
}
/* WEST exit */
if (r->getX() > p->getX()) {
z = r->getX() - p->getX();
if (z < distances[ED_WEST]) {
/* update */
distances[ED_WEST] = z;
candidates[ED_WEST] = p;
}
}
}
/* y-axis. */
if ((p->getX() == r->getX()) && (p->getZ() == r->getZ())) {
if (p->getY() == r->getY())
continue; /* all coordinates are the same - skip */
/* NORTH exit */
if (p->getY() > r->getY()) {
z = p->getY() - r->getY();
if (z < distances[ED_NORTH]) {
/* update */
distances[ED_NORTH] = z;
candidates[ED_NORTH] = p;
}
}
/* SOUTH exit */
if (r->getY() > p->getY()) {
z = r->getY() - p->getY();
if (z < distances[ED_SOUTH]) {
/* update */
distances[ED_SOUTH] = z;
candidates[ED_SOUTH] = p;
}
}
}
}
print_debug(DEBUG_ROOMS, "candidates gathered");
/* ok, now we have candidates for linking - lets check directions and connections*/
for (i=0; i <= 5; i++) {
ExitDirection iDir = static_cast<ExitDirection> (i);
if (r->isExitUndefined(iDir) && candidates[i] != NULL)
if (candidates[i]->isExitUndefined( reversenum(iDir) ) == true) {
if (distances[ i ] <= 2) {
print_debug(DEBUG_ROOMS, "we have a match for AngryLinker!");
print_debug(DEBUG_ROOMS, "ID: %i to %i exit %s.", r->getId(), candidates[i]->getId(), exits[i] );
/* ok, do the linking */
candidates[ i ]->setExitLeadsTo( reversenum(iDir), r);
r->setExitLeadsTo(iDir, candidates[ i ]);
print_debug(DEBUG_ROOMS, "Linked.", r->getId(), candidates[i]->getId(), exits[i] );
send_to_user("--[ (AngryLinker) Linked exit %s with %s [%i].\r\n",
exits[ i ], (const char*) candidates[i]->getName(), candidates[i]->getId());
}
}
}
//map->unlock();
}
static void aza_init(struct device *dev)
{
u32 base;
struct resource *res;
u32 codec_mask;
print_debug("AZALIA_INIT:---------->\n");
//-------------- enable AZA (SiS7502) -------------------------
{
u8 temp8;
int i=0;
while(SiS_SiS7502_init[i][0] != 0)
{
temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
temp8 &= SiS_SiS7502_init[i][1];
temp8 |= SiS_SiS7502_init[i][2];
pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
i++;
};
}
//-----------------------------------------------------------
// put audio to D0 state
pci_write_config8(dev, 0x54,0x00);
#if DEBUG_AZA
{
int i;
print_debug("****** Azalia PCI config ******");
print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){
if((i%16)==0){
print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
print_debug_hex32(pci_read_config32(dev,i));
print_debug(" ");
}
print_debug("\n");
}
#endif
res = find_resource(dev, 0x10);
if(!res)
return;
base = res->base;
printk(BIOS_DEBUG, "base = 0x%08x\n", base);
codec_mask = codec_detect(base);
if(codec_mask) {
printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
codecs_init(base, codec_mask);
}
print_debug("AZALIA_INIT:<----------\n");
}
/* ********************************
Multiplicative model for the placement of
a file at a given depth taking into
account the mean bytes at the depth
and the count of files at that depth
********************************/
int fn_depthsize_prob (long double filesize) {
double meansizediff[DEPTH_ENTRIES];
double final_prob[DEPTH_ENTRIES];
double totalsize_prob=0, totalprob=0;
double sum1=0, sum2=0, sum3=0;
int i =0;
float token_until_now=0;
int token;
int factor = 100000;
double depthsize_prob[DEPTH_ENTRIES];
srand(deseeder());
if(filesize ==0)
return rand()%max_dir_depth+1;
for(i=0; i< DEPTH_ENTRIES; i++) {
meansizediff[i]=(double) 1/fabsl(log2l(filesize)-(long double)depth_meansize[i]);
print_debug(0,"%Lf %Lf %f\n", log2l(filesize), (long double)depth_meansize[i], meansizediff[i]);
totalsize_prob+=meansizediff[i];
}
for(i=0; i< DEPTH_ENTRIES; i++) {
final_prob[i]=(depthcount_prob[i]/Total_depthcount_prob)*\
(meansizediff[i]/totalsize_prob);
}
for(i=0; i< DEPTH_ENTRIES; i++) {
totalprob+=final_prob[i];
}
for(i=0; i< DEPTH_ENTRIES; i++) {
print_debug(0, "Probsize[%d] %f; Probcount %f; Finalprob %f\n", i+1, \
meansizediff[i]/totalsize_prob*100, depthcount_prob[i]/Total_depthcount_prob*100,\
final_prob[i]/totalprob*100);
sum1+= meansizediff[i]/totalsize_prob;
sum2+= depthcount_prob[i]/Total_depthcount_prob;
sum3+= final_prob[i]/totalprob;
}
print_debug(0,"sums %f, sumc %f sumt %f\n", sum1, sum2, sum3);
i=0;
do {
token_until_now=0;
token = rand() % factor;
i=0;
token_until_now=final_prob[i]/totalprob*factor;
while (token_until_now < token) {
print_debug(0,"%f %d\n", token_until_now , token);
i++;
token_until_now+=final_prob[i]/totalprob*factor;
}
if(i== DEPTH_ENTRIES-1) { // last bin is actually 20 to infinite ..not just 20
i+= rand()%10; // e.g., any depth between 20 and 30, if DEPTH_ENTRIES=20
}
print_debug(0,"Chosen %d, max_dir %d\n", i, max_dir_depth);
}
while(i > max_dir_depth);
return i+1;
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
post_code(0x30);
agesawrapper_amdinitmmio();
post_code(0x31);
/* Halt if there was a built in self test failure */
post_code(0x33);
report_bist_failure(bist);
sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
w83627dhg_set_clksel_48(DUMMY_DEV);
w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
sb7xx_51xx_disable_wideio(0);
post_code(0x34);
uart_init();
post_code(0x35);
console_init();
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
post_code(0x37);
val = agesawrapper_amdinitreset();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
}
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x38);
/*
* SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
* Disable all Pcie Bridges to work around It.
*/
sr56x0_rd890_disable_pcie_bridge();
post_code(0x39);
nb_Poweron_Init();
post_code(0x3A);
sb_Poweron_Init();
}
post_code(0x3B);
val = agesawrapper_amdinitearly();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
}
post_code(0x3C);
/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
* In order to access W83795G/ADG HWM using I2C protocol,
* we select function to SDA, SCL function (or GP33, GP32 function).
*/
w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI));
nb_Ht_Init();
post_code(0x3D);
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
distinguish_cpu_resets(0);
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
post_code(0x40);
val = agesawrapper_amdinitpost();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
}
post_code(0x41);
val = agesawrapper_amdinitenv();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
}
printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
post_code(0x42);
post_code(0x50);
print_debug("Disabling cache as ram ");
disable_cache_as_ram();
print_debug("done\n");
post_code(0x51);
setup_i8259 ();
setup_i8254 ();
copy_and_run();
/* We will not return, Should never see this message and post code. */
print_debug("should not be here -\n");
post_code(0x54);
}
static void vx900_print_sata_errors(u32 flags)
{
/* Status flags */
printk(BIOS_DEBUG, "\tPhyRdy %s\n",
(flags & (1 << 16)) ? "changed" : "not changed");
printk(BIOS_DEBUG, "\tCOMWAKE %s\n",
(flags & (1 << 16)) ? "detected" : "not detected");
printk(BIOS_DEBUG, "\tExchange as determined by COMINIT %s\n",
(flags & (1 << 26)) ? "occured" : "not occured");
printk(BIOS_DEBUG, "\tPort selector presence %s\n",
(flags & (1 << 27)) ? "detected" : "not detected");
/* Errors */
if (flags & (1 << 0))
print_debug("\tRecovered data integrity ERROR\n");
if (flags & (1 << 1))
print_debug("\tRecovered data communication ERROR\n");
if (flags & (1 << 8))
print_debug("\tNon-recovered Transient Data Integrity ERROR\n");
if (flags & (1 << 9))
print_debug("\tNon-recovered Persistent Communication or"
"\tData Integrity ERROR\n");
if (flags & (1 << 10))
print_debug("\tProtocol ERROR\n");
if (flags & (1 << 11))
print_debug("\tInternal ERROR\n");
if (flags & (1 << 17))
print_debug("\tPHY Internal ERROR\n");
if (flags & (1 << 19))
print_debug("\t10B to 8B Decode ERROR\n");
if (flags & (1 << 20))
print_debug("\tDisparity ERROR\n");
if (flags & (1 << 21))
print_debug("\tCRC ERROR\n");
if (flags & (1 << 22))
print_debug("\tHandshake ERROR\n");
if (flags & (1 << 23))
print_debug("\tLink Sequence ERROR\n");
if (flags & (1 << 24))
print_debug("\tTransport State Transition ERROR\n");
if (flags & (1 << 25))
print_debug("\tUNRECOGNIZED FIS type\n");
}
/*---------------------------------------------------------------------------*/
static void
handle_incoming_rreq(void)
{
struct uaodv_msg_rreq *rm = (struct uaodv_msg_rreq *)uip_appdata;
uip_ipaddr_t dest_addr, orig_addr;
struct uaodv_rt_entry *rt, *fw = NULL;
print_debug("RREQ %d.%d.%d.%d -> %d.%d.%d.%d ttl=%u"
" orig=%d.%d.%d.%d seq=%lu hops=%u dest=%d.%d.%d.%d seq=%lu\n",
uip_ipaddr_to_quad(&BUF->srcipaddr),
uip_ipaddr_to_quad(&BUF->destipaddr),
BUF->ttl,
uip_ipaddr_to_quad(&rm->orig_addr), ntohl(rm->orig_seqno),
rm->hop_count,
uip_ipaddr_to_quad(&rm->dest_addr), ntohl(rm->dest_seqno));
if(uip_ipaddr_cmp(&rm->orig_addr, &uip_hostaddr)) {
return; /* RREQ looped back! */
}
#ifdef CC2420_RADIO
{
int ret = cc2420_check_remote(uip_udp_sender()->u16[1]);
if(ret == REMOTE_YES) {
print_debug("RREQ drop is remote\n");
return;
} else if (ret == REMOTE_NO) {
/* Is neigbour, accept it. */
} else if(cc2420_last_rssi < RSSI_THRESHOLD) {
print_debug("RREQ drop %d %d\n", cc2420_last_rssi,
cc2420_last_correlation);
return;
}
}
#endif
#ifdef AODV_BAD_HOP_EXTENSION
if(uip_len > (sizeof(*rm) + 2)) {
struct uaodv_bad_hop_ext *ext = (void *)(uip_appdata + sizeof(*rm));
u8_t *end = uip_appdata + uip_len;
for(;
(u8_t *)ext < end;
ext = (void *)((u8_t *)ext + ext->length + 2)) {
u8_t *eend = (u8_t *)ext + ext->length;
if(eend > end)
eend = end;
if(ext->type == RREQ_BAD_HOP_EXT) {
uip_ipaddr_t *a;
for(a = ext->addrs; (u8_t *)a < eend; a++) {
if(uip_ipaddr_cmp(a, &uip_hostaddr)) {
print_debug("BAD_HOP drop\n");
return;
}
}
}
}
}
#endif /* AODV_BAD_HOP_EXTENSION */
/* New reverse route? */
rt = uaodv_rt_lookup(&rm->orig_addr);
if(rt == NULL
|| (SCMP32(ntohl(rm->orig_seqno), rt->hseqno) > 0) /* New route. */
|| (SCMP32(ntohl(rm->orig_seqno), rt->hseqno) == 0
&& rm->hop_count < rt->hop_count)) { /* Better route. */
print_debug("Inserting1\n");
rt = uaodv_rt_add(&rm->orig_addr, uip_udp_sender(),
rm->hop_count, &rm->orig_seqno);
}
/* Check if it is for our address or a fresh route. */
if(uip_ipaddr_cmp(&rm->dest_addr, &uip_hostaddr)
|| rm->flags & UAODV_RREQ_DESTONLY) {
fw = NULL;
} else {
fw = uaodv_rt_lookup(&rm->dest_addr);
if(!(rm->flags & UAODV_RREQ_UNKSEQNO)
&& fw != NULL
&& SCMP32(fw->hseqno, ntohl(rm->dest_seqno)) <= 0) {
fw = NULL;
}
}
if (fw != NULL) {
u32_t net_seqno;
print_debug("RREQ for known route\n");
uip_ipaddr_copy(&dest_addr, &rm->dest_addr);
uip_ipaddr_copy(&orig_addr, &rm->orig_addr);
net_seqno = htonl(fw->hseqno);
send_rrep(&dest_addr, &rt->nexthop, &orig_addr, &net_seqno,
fw->hop_count + 1);
} else if(uip_ipaddr_cmp(&rm->dest_addr, &uip_hostaddr)) {
u32_t net_seqno;
print_debug("RREQ for our address\n");
uip_ipaddr_copy(&dest_addr, &rm->dest_addr);
uip_ipaddr_copy(&orig_addr, &rm->orig_addr);
my_hseqno++;
if(!(rm->flags & UAODV_RREQ_UNKSEQNO)
&& SCMP32(my_hseqno, ntohl(rm->dest_seqno)) < 0) {
print_debug("New my_hseqno %lu\n", my_hseqno); /* We have rebooted. */
my_hseqno = ntohl(rm->dest_seqno) + 1;
}
net_seqno = htonl(my_hseqno);
send_rrep(&dest_addr, &rt->nexthop, &orig_addr, &net_seqno, 0);
} else if(BUF->ttl > 1) {
int len;
/* Have we seen this RREQ before? */
if(fwc_lookup(&rm->orig_addr, &rm->rreq_id)) {
print_debug("RREQ cached, not fwd\n");
return;
}
fwc_add(&rm->orig_addr, &rm->rreq_id);
print_debug("RREQ fwd\n");
rm->hop_count++;
bcastconn->ttl = BUF->ttl - 1;
len = sizeof(struct uaodv_msg_rreq);
len += add_rreq_extensions(rm + 1);
uip_udp_packet_send(bcastconn, rm, len);
}
}
static /*err*/int parse_expression(parser_t * parser)
{
int err;
// start of expression: a value or unary (prefix) operator is expected
// parser->state->expect != 0
for (;;) {
int c = nextchar(&parser->buffer);
switch (c) {
case 0:
/* reached end of input */
if (parser->state->prev) {
err = ENODATA;
} else {
unsigned prec;
err = propagatemax_parserstate(parser->state, &prec);
}
if (err) {
print_error(parser, "Unexpected end of input\n");
}
goto ONERR;
case '?':
err = parse_3ary(parser);
if (err) goto ONERR;
break;
case ':':
err = matchnext3ary_parser(parser);
if (err) goto ONERR;
break;
case '(':
err = parse_1ary(parser, PREC_1ARY_BRACKET, EXPR_1ARY_BRACKET, EXPR_VOID);
if (err) goto ONERR;
err = newstate_parser(parser);
if (err) goto ONERR;
break;
case ')':
err = prevstate_parser(parser, EXPR_1ARY_BRACKET, ')');
if (err) goto ONERR;
break;
case '[':
err = parse_2ary(parser, PREC_2ARY_ARRAYINDEX, EXPR_2ARY_ARRAYINDEX, EXPR_VOID);
if (err) goto ONERR;
err = newstate_parser(parser);
if (err) goto ONERR;
break;
case ']':
err = prevstate_parser(parser, EXPR_2ARY_ARRAYINDEX, ']');
if (err) goto ONERR;
break;
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
err = parse_integer(parser, c);
if (err) goto ONERR;
break;
case '~':
err = parse_1ary(parser, PREC_1ARY_BITWISE_NOT, EXPR_1ARY_BITWISE_NOT, EXPR_VOID);
if (err) goto ONERR;
break;
case '!':
err = parse_1ary(parser, PREC_1ARY_LOGICAL_NOT, EXPR_1ARY_LOGICAL_NOT, EXPR_VOID);
if (err) goto ONERR;
break;
case '+':
c = peekchar(&parser->buffer);
if ('+' == c) {
nextchar(&parser->buffer);
err = parse_1ary(parser, PREC_1ARY_PREINCR, EXPR_1ARY_PREINCR, EXPR_1ARY_POSTINCR);
} else if ('=' == c) {
nextchar(&parser->buffer);
err = parse_2ary(parser, PREC_2ARY_ASSIGN, EXPR_2ARY_ASSIGN, EXPR_2ARY_PLUS);
} else if (parser->state->current->expect) {
err = parse_1ary(parser, PREC_1ARY_PLUS, EXPR_1ARY_PLUS, EXPR_VOID);
} else {
err = parse_2ary(parser, PREC_2ARY_PLUS, EXPR_2ARY_PLUS, EXPR_VOID);
}
if (err) goto ONERR;
break;
case '*':
c = peekchar(&parser->buffer);
if ('=' == c) {
nextchar(&parser->buffer);
err = parse_2ary(parser, PREC_2ARY_ASSIGN, EXPR_2ARY_ASSIGN, EXPR_2ARY_MULT);
} else {
err = parse_2ary(parser, PREC_2ARY_MULT, EXPR_2ARY_MULT, EXPR_VOID);
}
if (err) goto ONERR;
break;
case '&':
c = peekchar(&parser->buffer);
if ('=' == c) {
nextchar(&parser->buffer);
err = parse_2ary(parser, PREC_2ARY_ASSIGN, EXPR_2ARY_ASSIGN, EXPR_2ARY_BITWISE_AND);
} else {
err = parse_2ary(parser, PREC_2ARY_BITWISE_AND, EXPR_2ARY_BITWISE_AND, EXPR_VOID);
}
if (err) goto ONERR;
break;
case '=':
c = peekchar(&parser->buffer);
// TODO: ...
err = parse_2ary(parser, PREC_2ARY_ASSIGN, EXPR_2ARY_ASSIGN, EXPR_VOID);
if (err) goto ONERR;
break;
case '-':
if ('-' == peekchar(&parser->buffer)) {
nextchar(&parser->buffer);
err = parse_1ary(parser, PREC_1ARY_PREINCR, EXPR_1ARY_PREDECR, EXPR_1ARY_POSTDECR);
} else if ('=' == c) {
nextchar(&parser->buffer);
err = parse_2ary(parser, PREC_2ARY_ASSIGN, EXPR_2ARY_ASSIGN, EXPR_2ARY_MINUS);
} else if (parser->state->current->expect) {
err = parse_1ary(parser, PREC_1ARY_PLUS, EXPR_1ARY_MINUS, EXPR_VOID);
} else {
err = parse_2ary(parser, PREC_2ARY_PLUS, EXPR_2ARY_MINUS, EXPR_VOID);
}
if (err) goto ONERR;
break;
case ',':
err = parse_2ary(parser, PREC_2ARY_COMMA, EXPR_2ARY_COMMA, EXPR_VOID);
if (err) goto ONERR;
break;
default:
print_error(parser, "Unexpected input '%c'; expected number\n", c);
break;
}
}
ONERR:
print_debug(parser, "parse_expression error %d\n", err);
return err;
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0. */
/* Allow the HT devices to be found. */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
/* FIXME: This should be part of the Super I/O code/config. */
pnp_enter_ext_func_mode(SERIAL_DEV);
/* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
pnp_write_config(SERIAL_DEV, 0x24, 0);
w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
setup_mb_resource_map();
console_init();
report_bist_failure(bist); /* Halt upon BIST failure. */
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid);
print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
/* In BSP so could hold all AP until sysinfo is in RAM. */
set_sysinfo_in_ram(0);
#endif
setup_coherent_ht_domain(); /* Routing table and start other core0. */
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched
* becase optimize_link_coherent_ht is moved out from
* setup_coherent_ht_domain, so here need to make sure last core0 is
* started, esp for two way system (there may be APIC ID conflicts in
* that case).
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* Set up chains and store link pair for optimization later. */
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
#if CONFIG_SET_FIDVID
{
msr_t msr = rdmsr(0xc0010042);
print_debug("begin msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
{
msr_t msr = rdmsr(0xc0010042);
print_debug("end msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
}
#endif
init_timer(); /* Need to use TMICT to synconize FID/VID. */
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl in sysinfo now. */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
/* All AP stopped? */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
/* bsp switch stack to RAM and copy sysinfo RAM now. */
post_cache_as_ram();
}
static void ddr_ram_setup(void)
{
uint8_t b, c, bank, ma;
uint16_t i;
unsigned long bank_address;
print_debug("CN400 RAM init starting\n");
pci_write_config8(ctrl.d0f7, 0x75, 0x08);
/* No Interleaving or Multi Page */
pci_write_config8(ctrl.d0f3, 0x69, 0x00);
pci_write_config8(ctrl.d0f3, 0x6b, 0x10);
/*
DRAM MA Map Type Device 0 Fn3 Offset 50-51
Determine memory addressing based on the module's memory technology and
arrangement. See Table 4-9 of Intel's 82443GX datasheet for details.
Bank 1/0 MA map type 50[7-5]
Bank 1/0 command rate 50[4]
Bank 3/2 MA map type 50[3-1]
Bank 3/2 command rate 50[0]
Read SPD byte 17, Number of banks on SDRAM device.
*/
c = 0;
b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
//print_val("Detecting Memory\nNumber of Banks ",b);
// Only supporting 4 bank chips just now
if( b == 4 ){
/* Read SPD byte 3, Number of row addresses. */
c = 0x01;
bank = 0x40;
b = smbus_read_byte(DIMM0, SPD_NUM_ROWS);
//print_val("\nNumber of Rows ", b);
if( b >= 0x0d ){ // 256/512Mb
if (b == 0x0e)
bank = 0x48;
else
bank = 0x44;
/* Read SPD byte 13, Primary DRAM width. */
b = smbus_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
//print_val("\nPrimary DRAM width", b);
if( b != 4 ) // not 64/128Mb (x4)
c = 0x81; // 256Mb
}
/* Read SPD byte 4, Number of column addresses. */
b = smbus_read_byte(DIMM0, SPD_NUM_COLUMNS);
//print_val("\nNo Columns ",b);
if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr
if( b == 9 ) c |= 0x40; // 9 bit col addr
if( b == 8 ) c |= 0x20; // 8 bit col addr
//print_val("\nMA type ", c);
pci_write_config8(ctrl.d0f3, 0x50, c);
}
/* Disable Upper Banks */
pci_write_config8(ctrl.d0f3, 0x51, 0x00);
/* else
{
die("DRAM module size is not supported by CN400\n");
}
*/
/*
DRAM bank size. See 4.3.1 pg 35
5a->5d set to end address for each bank. 1 bit == 32MB
5a = bank 0
5b = bank 0 + b1
5c = bank 0 + b1 + b2
5d = bank 0 + b1 + b2 + b3
*/
// Read SPD byte 31 Module bank density
//c = 0;
b = smbus_read_byte(DIMM0, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
if( b & 0x02 )
{
c = 0x40; // 2GB
bank |= 0x02;
}
else if( b & 0x01)
{
c = 0x20; // 1GB
if (bank == 0x48) bank |= 0x01;
else bank |= 0x03;
}
else if( b & 0x80)
{
c = 0x10; // 512MB
if (bank == 0x44) bank |= 0x02;
}
else if( b & 0x40)
{
c = 0x08; // 256MB
if (bank == 0x44) bank |= 0x01;
else bank |= 0x03;
}
else if( b & 0x20)
{
c = 0x04; // 128MB
if (bank == 0x40) bank |= 0x02;
}
else if( b & 0x10)
{
c = 0x02; // 64MB
bank |= 0x01;
}
else if( b & 0x08) c = 0x01; // 32MB
else c = 0x01; // Error, use default
// set bank zero size
pci_write_config8(ctrl.d0f3, 0x40, c);
// SPD byte 5 # of physical banks
b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS);
//print_val("\nNo Physical Banks ",b);
if( b == 2)
{
c <<=1;
bank |= 0x80;
}
/* else
{
die("Only a single DIMM is supported by EPIA-N(L)\n");
}
*/
// set banks 1,2,3...
pci_write_config8(ctrl.d0f3, 0x41,c);
pci_write_config8(ctrl.d0f3, 0x42,c);
pci_write_config8(ctrl.d0f3, 0x43,c);
pci_write_config8(ctrl.d0f3, 0x44,c);
pci_write_config8(ctrl.d0f3, 0x45,c);
pci_write_config8(ctrl.d0f3, 0x46,c);
pci_write_config8(ctrl.d0f3, 0x47,c);
/* Top Rank Address Mirrored to the South Bridge */
/* over the VLink */
pci_write_config8(ctrl.d0f7, 0x57, (c << 1));
ma = bank;
/* Read SPD byte 18 CAS Latency */
b = smbus_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
/* print_debug("\nCAS Supported ");
if(b & 0x04)
print_debug("2 ");
if(b & 0x08)
print_debug("2.5 ");
if(b & 0x10)
print_debug("3");
c = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
print_val("\nCycle time at CL X (nS)", c);
c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
print_val("\nCycle time at CL X-0.5 (nS)", c);
c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
print_val("\nCycle time at CL X-1 (nS)", c);
*/
/* Scaling of Cycle Time SPD data */
/* 7 4 3 0 */
/* ns x0.1ns */
bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if( b & 0x10 ){ // DDR offering optional CAS 3
//print_debug("\nStarting at CAS 3");
c = 0x30;
/* see if we can better it */
if( b & 0x08 ){ // DDR mandatory CAS 2.5
if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
//print_debug("\nWe can do CAS 2.5");
c = 0x20;
}
}
if( b & 0x04 ){ // DDR mandatory CAS 2
if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
//print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
}else{ // no optional CAS values just 2 & 2.5
//print_debug("\nStarting at CAS 2.5");
c = 0x20; // assume CAS 2.5
if( b & 0x04){ // Should always happen
if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
//print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
}
/* Scale DRAM Cycle Time to tRP/tRCD */
/* 7 2 1 0 */
/* ns x0.25ns */
if ( bank <= 0x50 ) bank = 0x14;
else if (bank <= 0x60) bank = 0x18;
else bank = 0x1E;
/*
DRAM Timing Device 0 Fn 3 Offset 56
RAS Pulse width 56[7,6]
CAS Latency 56[5,4]
Row pre-charge 56[1,0]
SDR DDR
00 1T -
01 2T 2T
10 3T 2.5T
11 - 3T
RAS/CAS delay 56[3,2]
Determine row pre-charge time (tRP)
Read SPD byte 27, min row pre-charge time.
*/
b = smbus_read_byte(DIMM0, SPD_MIN_ROW_PRECHARGE_TIME);
//print_val("\ntRP ",b);
if ( b >= (5 * bank)) {
c |= 0x03; // set tRP = 5T
}
else if ( b >= (4 * bank)) {
c |= 0x02; // set tRP = 4T
}
else if ( b >= (3 * bank)) {
c |= 0x01; // set tRP = 3T
}
/*
Determine RAS to CAS delay (tRCD)
Read SPD byte 29, min row pre-charge time.
*/
b = smbus_read_byte(DIMM0, SPD_MIN_RAS_TO_CAS_DELAY);
//print_val("\ntRCD ",b);
if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T
else if ( b >= (4 * bank)) c |= 0x08; // set tRCD = 4T
else if ( b >= (3 * bank)) c |= 0x04; // set tRCD = 3T
/*
Determine RAS pulse width (tRAS)
Read SPD byte 30, device min active to pre-charge time.
*/
/* tRAS is in whole ns */
bank = bank >> 2;
b = smbus_read_byte(DIMM0, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
//print_val("\ntRAS ",b);
//print_val("\nBank ", bank);
if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T
else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T
else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T
/* Write DRAM Timing All Banks I */
pci_write_config8(ctrl.d0f3, 0x56, c);
/* TWrite DRAM Timing All Banks II */
pci_write_config8(ctrl.d0f3, 0x57, 0x1a);
/* DRAM arbitration timer */
pci_write_config8(ctrl.d0f3, 0x65, 0x99);
/*
DRAM Clock Device 0 Fn 3 Offset 68
*/
bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
/* Setup DRAM Cycle Time */
if ( bank <= 0x50 )
{
/* DRAM DDR Control Alert! Alert! See also c3_cpu_setup */
/* This sets to 133MHz FSB / DDR400. */
pci_write_config8(ctrl.d0f3, 0x68, 0x85);
}
else if (bank <= 0x60)
{
/* DRAM DDR Control Alert! Alert! This hardwires to */
/* 133MHz FSB / DDR333. See also c3_cpu_setup */
pci_write_config8(ctrl.d0f3, 0x68, 0x81);
}
else
{
/* DRAM DDR Control Alert! Alert! This hardwires to */
/* 133MHz FSB / DDR266. See also c3_cpu_setup */
pci_write_config8(ctrl.d0f3, 0x68, 0x80);
}
/* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
udelay(200);
/*
Determine bank interleave
Read SPD byte 17, Number of banks on SDRAM device.
*/
c = 0x0F;
b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
if( b == 4) c |= 0x80;
else if (b == 2) c |= 0x40;
/* 4-Way Interleave With Multi-Paging (From Running System)*/
pci_write_config8(ctrl.d0f3, 0x69, c);
/*DRAM Controller Internal Options */
pci_write_config8(ctrl.d0f3, 0x54, 0x01);
/* DRAM Arbitration Control */
pci_write_config8(ctrl.d0f3, 0x66, 0x82);
/* DRAM Control */
pci_write_config8(ctrl.d0f3, 0x6e, 0x80);
/* Disable refresh for now */
pci_write_config8(ctrl.d0f3, 0x6a, 0x00);
/* DDR Clock Gen Duty Cycle Control */
pci_write_config8(ctrl.d0f3, 0xEE, 0x01);
/* DRAM Clock Control */
pci_write_config8(ctrl.d0f3, 0x6c, 0x00);
/* DRAM Bus Turn-Around Setting */
pci_write_config8(ctrl.d0f3, 0x60, 0x01);
/* Disable DRAM refresh */
pci_write_config8(ctrl.d0f3,0x6a,0x0);
/* Memory Pads Driving and Range Select */
pci_write_config8(ctrl.d0f3, 0xe2, 0xAA);
pci_write_config8(ctrl.d0f3, 0xe3, 0x00);
pci_write_config8(ctrl.d0f3, 0xe4, 0x99);
/* DRAM signal timing control */
pci_write_config8(ctrl.d0f3, 0x74, 0x99);
pci_write_config8(ctrl.d0f3, 0x76, 0x09);
pci_write_config8(ctrl.d0f3, 0x77, 0x12);
pci_write_config8(ctrl.d0f3, 0xe0, 0xAA);
pci_write_config8(ctrl.d0f3, 0xe1, 0x00);
pci_write_config8(ctrl.d0f3, 0xe6, 0x00);
pci_write_config8(ctrl.d0f3, 0xe8, 0xEE);
pci_write_config8(ctrl.d0f3, 0xea, 0xEE);
/* SPD byte 5 # of physical banks */
b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
c = b | 0x40;
pci_write_config8(ctrl.d0f3, 0xb0, c);
/* Set RAM Decode method */
pci_write_config8(ctrl.d0f3, 0x55, 0x0a);
/* Enable DIMM Ranks */
pci_write_config8(ctrl.d0f3, 0x48, ma);
udelay(200);
c = smbus_read_byte(DIMM0, SPD_SUPPORTED_BURST_LENGTHS);
c &= 0x08;
if ( c == 0x08 )
{
print_debug("Setting Burst Length 8\n");
/*
CPU Frequency Device 0 Function 2 Offset 54
CPU FSB Operating Frequency (bits 7:5)
000 : 100MHz 001 : 133MHz
010 : 200MHz
011->111 : Reserved
SDRAM BL8 (4)
Don't change Frequency from power up defaults
This seems to lockup the RAM interface
*/
c = pci_read_config8(ctrl.d0f2, 0x54);
c |= 0x10;
pci_write_config8(ctrl.d0f2, 0x54, c);
i = 0x008; // Used later to set SDRAM MSR
}
for( bank = 0 , bank_address=0; bank <= b ; bank++) {
/*
DDR init described in Via VT8623 BIOS Porting Guide. Pg 28 (4.2.3.1)
*/
/* NOP command enable */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_NOP;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
/* read a double word from any address of the dimm */
dimm_read(bank_address,0x1f000);
//udelay(200);
/* All bank precharge Command Enable */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_PRECHARGE;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
dimm_read(bank_address,0x1f000);
/* MSR Enable Low DIMM*/
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_MSR_LOW;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
/* TODO: Bank Addressing for Different Numbers of Row Addresses */
dimm_read(bank_address,0x2000);
udelay(1);
dimm_read(bank_address,0x800);
udelay(1);
/* All banks precharge Command Enable */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_PRECHARGE;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
dimm_read(bank_address,0x1f200);
/* CBR Cycle Enable */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_CBR;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
/* Read 8 times */
for (c=0;c<8;c++) {
dimm_read(bank_address,0x1f300);
udelay(100);
}
/* MSR Enable */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_MSR_LOW;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
/*
Mode Register Definition
with adjustement so that address calculation is correct - 64 bit technology, therefore
a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
to DIMM as a row or column address.
MR[9-7] CAS Latency
MR[6] Burst Type 0 = sequential, 1 = interleaved
MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved
MR[0-2] dont care
CAS Latency
000 reserved
001 reserved
010 2
011 3
100 reserved
101 1.5
110 2.5
111 reserved
CAS 2 0101011000 = 0x158
CAS 2.5 1101011000 = 0x358
CAS 3 0111011000 = 0x1d8
*/
c = pci_read_config8(ctrl.d0f3, 0x56);
if( (c & 0x30) == 0x10 )
dimm_read(bank_address,(0x150 + i));
else if((c & 0x30) == 0x20 )
dimm_read(bank_address,(0x350 + i));
else
dimm_read(bank_address,(0x1d0 + i));
/* Normal SDRAM Mode */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_NORMAL;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000;
} // end of for each bank
/* Set DRAM DQS Output Control */
pci_write_config8(ctrl.d0f3, 0x79, 0x11);
/* Set DQS A/B Input delay to defaults */
pci_write_config8(ctrl.d0f3, 0x7A, 0xA1);
pci_write_config8(ctrl.d0f3, 0x7B, 0x62);
/* DQS Duty Cycle Control */
pci_write_config8(ctrl.d0f3, 0xED, 0x11);
/* SPD byte 5 # of physical banks */
b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
/* determine low bond */
if( b == 2)
bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000;
else
bank_address = 0;
for(i = 0x30 ; i < 0x0ff; i++){
pci_write_config8(ctrl.d0f3,0x70,i);
// clear
*(volatile unsigned long*)(0x4000) = 0;
*(volatile unsigned long*)(0x4100+bank_address) = 0;
*(volatile unsigned long*)(0x4200) = 0;
*(volatile unsigned long*)(0x4300+bank_address) = 0;
*(volatile unsigned long*)(0x4400) = 0;
*(volatile unsigned long*)(0x4500+bank_address) = 0;
// fill
*(volatile unsigned long*)(0x4000) = 0x12345678;
*(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
*(volatile unsigned long*)(0x4200) = 0x78123456;
*(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
*(volatile unsigned long*)(0x4400) = 0x56781234;
*(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
// verify
if( *(volatile unsigned long*)(0x4000) != 0x12345678)
continue;
if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
continue;
if( *(volatile unsigned long*)(0x4200) != 0x78123456)
continue;
if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
continue;
if( *(volatile unsigned long*)(0x4400) != 0x56781234)
continue;
if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
continue;
// if everything verified then found low bond
break;
}
print_val("\nLow Bond ",i);
if( i < 0xff ){
c = i++;
for( ; i <0xff ; i++){
pci_write_config8(ctrl.d0f3,0x70, i);
// clear
*(volatile unsigned long*)(0x8000) = 0;
*(volatile unsigned long*)(0x8100+bank_address) = 0;
*(volatile unsigned long*)(0x8200) = 0x0;
*(volatile unsigned long*)(0x8300+bank_address) = 0;
*(volatile unsigned long*)(0x8400) = 0x0;
*(volatile unsigned long*)(0x8500+bank_address) = 0;
// fill
*(volatile unsigned long*)(0x8000) = 0x12345678;
*(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
*(volatile unsigned long*)(0x8200) = 0x78123456;
*(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
*(volatile unsigned long*)(0x8400) = 0x56781234;
*(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
// verify
if( *(volatile unsigned long*)(0x8000) != 0x12345678)
break;
if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
break;
if( *(volatile unsigned long*)(0x8200) != 0x78123456)
break;
if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
break;
if( *(volatile unsigned long*)(0x8400) != 0x56781234)
break;
if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
break;
}
print_val(" High Bond ",i);
c = ((i - c)<<1)/3 + c;
print_val(" Setting DQS delay",c);
print_debug("\n");
pci_write_config8(ctrl.d0f3,0x70,c);
}else{
pci_write_config8(ctrl.d0f3,0x70,0x67);
}
/* Set DQS ChA Data Output Delay to the default */
pci_write_config8(ctrl.d0f3, 0x71, 0x65);
/* Set Ch B DQS Output Delays */
pci_write_config8(ctrl.d0f3, 0x72, 0x2a);
pci_write_config8(ctrl.d0f3, 0x73, 0x29);
pci_write_config8(ctrl.d0f3, 0x78, 0x03);
/* Mystery Value */
pci_write_config8(ctrl.d0f3, 0x67, 0x50);
/* Enable Toggle Limiting */
pci_write_config8(ctrl.d0f4, 0xA3, 0x80);
/*
DRAM refresh rate Device 0 F3 Offset 6a
TODO :: Fix for different DRAM technologies
other than 512Mb and DRAM Freq
Units of 16 DRAM clock cycles - 1.
*/
//c = pci_read_config8(ctrl.d0f3, 0x68);
//c &= 0x07;
//b = smbus_read_byte(DIMM0, SPD_REFRESH);
//print_val("SPD_REFRESH = ", b);
pci_write_config8(ctrl.d0f3,0x6a,0x65);
/* SMM and APIC decoding, we do not use SMM */
b = 0x29;
pci_write_config8(ctrl.d0f3, 0x86, b);
/* SMM and APIC decoding mirror */
pci_write_config8(ctrl.d0f7, 0xe6, b);
/* Open Up the Rest of the Shadow RAM */
pci_write_config8(ctrl.d0f3,0x80,0xff);
pci_write_config8(ctrl.d0f3,0x81,0xff);
/* pci */
pci_write_config8(ctrl.d0f7,0x70,0x82);
pci_write_config8(ctrl.d0f7,0x73,0x01);
pci_write_config8(ctrl.d0f7,0x76,0x50);
pci_write_config8(ctrl.d0f7,0x71,0xc8);
/* VGA device. */
pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
print_debug("CN400 raminit.c done\n");
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
//first node
RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
//second node
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
};
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_ms9185_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid);
print_debug("\n");
setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
//bx_a010- wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
bcm5785_early_setup();
#if 0
//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid ");
print_debug_hex32( msr.hi );
print_debug_hex32(msr.lo);
print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid ");
print_debug_hex32( msr.hi );
print_debug_hex32(msr.lo);
print_debug("\n");
}
#endif
#if 1
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
#endif
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
#if 0
int i;
for(i=0; i<2; i++) {
activate_spd_rom(sysinfo->ctrl+i);
dump_smbus_registers();
}
#endif
#if 0
int i;
for(i=1; i<256; i<<=1) {
change_i2c_mux(i);
dump_smbus_registers();
}
#endif
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0
print_pci_devices();
#endif
#if 0
// dump_pci_devices();
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
post_cache_as_ram();
}
static void print_val(char *str, int val)
{
print_debug(str);
print_debug_hex8(val);
}
int mini_isp_debug_load_reg(char *reg_file,u32 *reg_key,u32 reg_max,u32 *reg_cnt)
{
struct kstat stat;
mm_segment_t fs;
struct file *fp = NULL;
int file_flag = O_RDONLY;
ssize_t ret = 0;
u32 addr = 0;
char addr_array[8] = {0};
char temp;
bool bRegStart = false;
if (NULL == reg_file) {
print_error("%s param error", __func__);
return -EINVAL;
}
print_debug("enter %s", __func__);
/* must have the following 2 statement */
fs = get_fs();
set_fs(KERNEL_DS);
fp = filp_open(reg_file, file_flag, 0666);
if (IS_ERR_OR_NULL(fp)) {
print_debug("no debug configuration file(%s) - do nothing, just skip it!\n",reg_file);
return -1;
}
if (0 != vfs_stat(reg_file, &stat)) {
print_error("failed to get file state!");
goto ERROR;
}
*reg_cnt = 0;
print_debug("file size : %d", (u32) stat.size);
while (0 < vfs_read(fp, &temp, 1, &fp->f_pos)) {
switch (temp) {
case '{':
bRegStart = true;
if (0 == vfs_read(fp, addr_array, 7, &fp->f_pos))
goto ERROR;
addr = mini_atoi16(addr_array);
if (*reg_cnt < reg_max){
reg_key[*reg_cnt]=addr;
*reg_cnt=*reg_cnt+1;
}
break;
case '}':
bRegStart = false;
break;
default:
break;
}
}
/* must have the following 1 statement */
set_fs(fs);
ERROR:
if (NULL != fp)
filp_close(fp, 0);
return ret;
}
/* ***************************************************************************/
void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
{
int msrnum;
msr_t msr;
/* Castle 2.0 BTM periodic sync period. */
/* [40:37] 1 sync record per 256 bytes */
print_debug("Castle 2.0 BTM periodic sync period.\n");
msrnum = CPU_PF_CONF;
msr = rdmsr(msrnum);
msr.hi |= (0x8 << 5);
wrmsr(msrnum, msr);
/*
* LX performance setting.
* Enable Quack for fewer re-RAS on the MC
*/
print_debug("Enable Quack for fewer re-RAS on the MC\n");
msrnum = GLIU0_ARB;
msr = rdmsr(msrnum);
msr.hi &= ~ARB_UPPER_DACK_EN_SET;
msr.hi |= ARB_UPPER_QUACK_EN_SET;
wrmsr(msrnum, msr);
msrnum = GLIU1_ARB;
msr = rdmsr(msrnum);
msr.hi &= ~ARB_UPPER_DACK_EN_SET;
msr.hi |= ARB_UPPER_QUACK_EN_SET;
wrmsr(msrnum, msr);
/* GLIU port active enable, limit south pole masters
* (AES and PCI) to one outstanding transaction.
*/
print_debug(" GLIU port active enable\n");
msrnum = GLIU1_PORT_ACTIVE;
msr = rdmsr(msrnum);
msr.lo &= ~0x880;
wrmsr(msrnum, msr);
/* Set the Delay Control in GLCP */
print_debug("Set the Delay Control in GLCP\n");
SetDelayControl(dimm0, dimm1, terminated);
/* Enable RSDC */
print_debug("Enable RSDC\n");
msrnum = CPU_AC_SMM_CTL;
msr = rdmsr(msrnum);
msr.lo |= SMM_INST_EN_SET;
wrmsr(msrnum, msr);
/* FPU imprecise exceptions bit */
print_debug("FPU imprecise exceptions bit\n");
msrnum = CPU_FPU_MSR_MODE;
msr = rdmsr(msrnum);
msr.lo |= FPU_IE_SET;
wrmsr(msrnum, msr);
/* Power Savers (Do after BIST) */
/* Enable Suspend on HLT & PAUSE instructions */
print_debug("Enable Suspend on HLT & PAUSE instructions\n");
msrnum = CPU_XC_CONFIG;
msr = rdmsr(msrnum);
msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
wrmsr(msrnum, msr);
/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
print_debug("Enable SUSP and allow TSC to run in Suspend\n");
msrnum = CPU_BC_CONF_0;
msr = rdmsr(msrnum);
msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
msr.lo &= 0x0F0FFFFFF;
msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */
wrmsr(msrnum, msr);
/* Disable the debug clock to save power. */
/* NOTE: leave it enabled for fs2 debug */
if (debug_clock_disable && 0) {
msrnum = GLCP_DBGCLKCTL;
msr.hi = 0;
msr.lo = 0;
wrmsr(msrnum, msr);
}
/* Setup throttling delays to proper mode if it is ever enabled. */
print_debug("Setup throttling delays to proper mode\n");
msrnum = GLCP_TH_OD;
msr.hi = 0;
msr.lo = 0x00000603C;
wrmsr(msrnum, msr);
print_debug("Done cpuRegInit\n");
}