static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
ata_index_t index;
ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];
ide_setup_pci_noise(dev, d);
/* We must not grab the entire device, it has 'ISA' space in its
BARS too and we will freak out other bits of the kernel */
if (pci_enable_device_bars(dev, 1<<2)) {
printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
return -ENODEV;
}
pci_set_master(dev);
if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
return -ENODEV;
}
index.all = 0xf0f0;
/*
* Now the chipset is configured we can let the core
* do all the device setup for us
*/
ide_pci_setup_ports(dev, d, 14, &index);
if((index.b.low & 0xf0) != 0xf0)
probe_hwif_init(&ide_hwifs[index.b.low]);
if((index.b.high & 0xf0) != 0xf0)
probe_hwif_init(&ide_hwifs[index.b.high]);
return 0;
}
static int __init ali14xx_probe(void)
{
ide_hwif_t *hwif, *mate;
printk(KERN_DEBUG "ali14xx: base=0x%03x, regOn=0x%02x.\n",
basePort, regOn);
/* initialize controller registers */
if (!initRegisters()) {
printk(KERN_ERR "ali14xx: Chip initialization failed.\n");
return 1;
}
hwif = &ide_hwifs[0];
mate = &ide_hwifs[1];
hwif->chipset = ide_ali14xx;
hwif->tuneproc = &ali14xx_tune_drive;
hwif->mate = mate;
mate->chipset = ide_ali14xx;
mate->tuneproc = &ali14xx_tune_drive;
mate->mate = hwif;
mate->channel = 1;
probe_hwif_init(hwif);
probe_hwif_init(mate);
return 0;
}
/* Can be called directly from ide.c. */
int __init ht6560b_init(void)
{
ide_hwif_t *hwif, *mate;
int t;
hwif = &ide_hwifs[0];
mate = &ide_hwifs[1];
if (!request_region(HT_CONFIG_PORT, 1, hwif->name)) {
printk(KERN_NOTICE "%s: HT_CONFIG_PORT not found\n",
__FUNCTION__);
return -ENODEV;
}
if (!try_to_init_ht6560b()) {
printk(KERN_NOTICE "%s: HBA not found\n", __FUNCTION__);
goto release_region;
}
hwif->chipset = ide_ht6560b;
hwif->selectproc = &ht6560b_selectproc;
hwif->tuneproc = &tune_ht6560b;
hwif->serialized = 1; /* is this needed? */
hwif->mate = mate;
mate->chipset = ide_ht6560b;
mate->selectproc = &ht6560b_selectproc;
mate->tuneproc = &tune_ht6560b;
mate->serialized = 1; /* is this needed? */
mate->mate = hwif;
mate->channel = 1;
/*
* Setting default configurations for drives
*/
t = (HT_CONFIG_DEFAULT << 8);
t |= HT_TIMING_DEFAULT;
hwif->drives[0].drive_data = t;
hwif->drives[1].drive_data = t;
t |= (HT_SECONDARY_IF << 8);
mate->drives[0].drive_data = t;
mate->drives[1].drive_data = t;
probe_hwif_init(hwif);
probe_hwif_init(mate);
create_proc_ide_interfaces();
return 0;
release_region:
release_region(HT_CONFIG_PORT, 1);
return -ENODEV;
}
static int __init dtc2278_probe(void)
{
unsigned long flags;
ide_hwif_t *hwif, *mate;
hwif = &ide_hwifs[0];
mate = &ide_hwifs[1];
if (hwif->chipset != ide_unknown || mate->chipset != ide_unknown)
return 1;
local_irq_save(flags);
/*
* This enables the second interface
*/
outb_p(4,0xb0);
inb(0x3f6);
outb_p(0x20,0xb4);
inb(0x3f6);
#ifdef ALWAYS_SET_DTC2278_PIO_MODE
/*
* This enables PIO mode4 (3?) on the first interface
* and may solve start-up problems for some people.
*/
sub22(1,0xc3);
sub22(0,0xa0);
#endif
local_irq_restore(flags);
hwif->serialized = 1;
hwif->chipset = ide_dtc2278;
hwif->tuneproc = &tune_dtc2278;
hwif->drives[0].no_unmask = 1;
hwif->drives[1].no_unmask = 1;
hwif->mate = mate;
mate->serialized = 1;
mate->chipset = ide_dtc2278;
mate->drives[0].no_unmask = 1;
mate->drives[1].no_unmask = 1;
mate->mate = hwif;
mate->channel = 1;
probe_hwif_init(hwif);
probe_hwif_init(mate);
create_proc_ide_interfaces();
return 0;
}
static int __devinit
rapide_probe(struct expansion_card *ec, const struct ecard_id *id)
{
ide_hwif_t *hwif;
void __iomem *base;
int ret;
ret = ecard_request_resources(ec);
if (ret)
goto out;
base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC),
ecard_resource_len(ec, ECARD_RES_MEMC));
if (!base) {
ret = -ENOMEM;
goto release;
}
hwif = rapide_locate_hwif(base, base + 0x818, 1 << 6, ec->irq);
if (hwif) {
hwif->hwif_data = base;
hwif->gendev.parent = &ec->dev;
hwif->noprobe = 0;
probe_hwif_init(hwif);
create_proc_ide_interfaces();
ecard_set_drvdata(ec, hwif);
goto out;
}
iounmap(base);
release:
ecard_release_resources(ec);
out:
return ret;
}
void __init probe_dtc2278 (void)
{
unsigned long flags;
local_irq_save(flags);
/*
* This enables the second interface
*/
outb_p(4,0xb0);
inb(0x3f6);
outb_p(0x20,0xb4);
inb(0x3f6);
#ifdef ALWAYS_SET_DTC2278_PIO_MODE
/*
* This enables PIO mode4 (3?) on the first interface
* and may solve start-up problems for some people.
*/
sub22(1,0xc3);
sub22(0,0xa0);
#endif
local_irq_restore(flags);
ide_hwifs[0].serialized = 1;
ide_hwifs[1].serialized = 1;
ide_hwifs[0].chipset = ide_dtc2278;
ide_hwifs[1].chipset = ide_dtc2278;
ide_hwifs[0].tuneproc = &tune_dtc2278;
ide_hwifs[0].drives[0].no_unmask = 1;
ide_hwifs[0].drives[1].no_unmask = 1;
ide_hwifs[1].drives[0].no_unmask = 1;
ide_hwifs[1].drives[1].no_unmask = 1;
ide_hwifs[0].mate = &ide_hwifs[1];
ide_hwifs[1].mate = &ide_hwifs[0];
ide_hwifs[1].channel = 1;
#ifndef HWIF_PROBE_CLASSIC_METHOD
probe_hwif_init(&ide_hwifs[0]);
probe_hwif_init(&ide_hwifs[1]);
#endif /* HWIF_PROBE_CLASSIC_METHOD */
}
static inline int csb536_cf_init(void)
{
ide_hwif_t *hwif;
ide_drive_t *drive;
hw_regs_t hw;
int cf_idx;
dbg("CSB536 CF Probe\n");
dbg("Using CF_REGISTER_BASE 0x%08lx\n",CF_REGISTER_BASE);
ide_setup_ports(&hw, CF_REGISTER_BASE, cfide_offsets, 0, 0, &csb536_ide_ack_intr, CF_RDYBSY_IRQ);
/* Reset the CF card */
csb536_cf_reset(NULL);
/* Dump the initial state of CF registers */
dbg("CF Config Option Reg(0x%08lx)=0x%02x\n",CF_CONFIG_OPTION_REG, inb(CF_CONFIG_OPTION_REG));
dbg("CF Config/Status Reg(0x%08lx)=0x%02x\n",CF_CONFIG_STATUS_REG, inb(CF_CONFIG_STATUS_REG));
dbg("CF Pin Replacement Reg(0x%08lx)=0x%02x\n",CF_PIN_REPLACEMENT_REG, inw(CF_PIN_REPLACEMENT_REG));
dbg("CF Socket and Copy Reg(0x%08lx)=0x%02x\n",CF_SOCKET_AND_COPY_REG, inb(CF_SOCKET_AND_COPY_REG));
/* Make sure that the CF card in is memory mapped mode by
* writing 0x0000 to the Configuration Option Register.
*/
dbg("Using Memory Mapped Mode\n");
outb(0x00, CF_CONFIG_OPTION_REG);
/* Dump the current state of CF registers */
dbg("CF Config Option Reg(0x%08lx)=0x%02x\n",
CF_CONFIG_OPTION_REG, inb(CF_CONFIG_OPTION_REG));
dbg("CF Config/Status Reg(0x%08lx)=0x%02x\n",
CF_CONFIG_STATUS_REG, inb(CF_CONFIG_STATUS_REG));
dbg("CF Pin Replacement Reg(0x%08lx)=0x%02x\n",
CF_PIN_REPLACEMENT_REG, inb(CF_PIN_REPLACEMENT_REG));
dbg("CF Socket and Copy Reg(0x%08lx)=0x%02x\n",
CF_SOCKET_AND_COPY_REG, inb(CF_SOCKET_AND_COPY_REG));
udelay(CF_MODE_DELAY);
/* Register the hardware interface. NOTE: The CF hardware
* must be completely initialized at this point because if
* ide_register_hw() is called AFTER initialization of the built-in,
* drivers it will also probe the CF interface.
*/
cf_idx = ide_register_hw(&hw, &hwif);
if (cf_idx < 0)
{
err("Could not register CSB536 CompactFlash driver\n");
return -ENODEV;
}
dbg("Using ide_hwifs[%d]\n", cf_idx);
/* Provide function pointers for special handling */
hwif->resetproc = csb536_cf_reset;
/* We assume only one "drive," the master driver.
* Probe only the master drive
*/
drive = &hwif->drives[0];
drive->noprobe = 0;
hwif->drives[1].noprobe = 1;
/* This is the signature for a CF card */
drive->removable = 1;
drive->is_flash = 1;
/* Dump all IDE registers */
dbg("CF DATA(0x%08lx) = 0x%04x\n",
hwif->hw.io_ports[IDE_DATA_OFFSET],
inw(hwif->hw.io_ports[IDE_DATA_OFFSET]));
dbg("CF ERROR(0x%08lx) = 0x%02x\n",
hwif->hw.io_ports[IDE_ERROR_OFFSET],
inb(hwif->hw.io_ports[IDE_ERROR_OFFSET]));
dbg("CF NSECTOR(0x%08lx) = 0x%02x\n",
hwif->hw.io_ports[IDE_NSECTOR_OFFSET],
inb(hwif->hw.io_ports[IDE_NSECTOR_OFFSET]));
dbg("CF SECTOR(0x%08lx) = 0x%02x\n",
hwif->hw.io_ports[IDE_SECTOR_OFFSET],
inb(hwif->hw.io_ports[IDE_SECTOR_OFFSET]));
dbg("CF LCYL(0x%08lx) = 0x%02x\n",
hwif->hw.io_ports[IDE_LCYL_OFFSET],
inb(hwif->hw.io_ports[IDE_LCYL_OFFSET]));
dbg("CF HCYL(0x%08lx) = 0x%02x\n",
hwif->hw.io_ports[IDE_HCYL_OFFSET],
inb(hwif->hw.io_ports[IDE_HCYL_OFFSET]));
dbg("CF SELECT(0x%08lx) = 0x%02x\n",
hwif->hw.io_ports[IDE_SELECT_OFFSET],
inb(hwif->hw.io_ports[IDE_SELECT_OFFSET]));
dbg("CF STATUS(0x%08lx) = 0x%02x\n",
hwif->hw.io_ports[IDE_STATUS_OFFSET],
inb(hwif->hw.io_ports[IDE_STATUS_OFFSET]));
dbg("CF CONTROL(0x%08lx) = 0x%02x\n",
hwif->hw.io_ports[IDE_CONTROL_OFFSET],
inb(hwif->hw.io_ports[IDE_CONTROL_OFFSET]));
dbg("CF IRQ(0x%08lx) = 0x%02x\n",
hwif->hw.io_ports[IDE_IRQ_OFFSET],
inb(hwif->hw.io_ports[IDE_IRQ_OFFSET]));
csb536_cf_memory();
/* Probe the hardware interface. NOTE: If ide_register_hw() is
* called AFTER initialization of IDE built-in drivers, it will do
* the following automatically.
*/
probe_hwif_init(hwif);
create_proc_ide_interfaces();
return cf_idx;
}
static int __devinit
sgiioc4_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t * d)
{
unsigned long base, ctl, dma_base, irqport;
ide_hwif_t *hwif;
int h;
/*
* Find an empty HWIF; if none available, return -ENOMEM.
*/
for (h = 0; h < MAX_HWIFS; ++h) {
hwif = &ide_hwifs[h];
if (hwif->chipset == ide_unknown)
break;
}
if (h == MAX_HWIFS) {
printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", d->name);
return -ENOMEM;
}
/* Get the CmdBlk and CtrlBlk Base Registers */
base = pci_resource_start(dev, 0) + IOC4_CMD_OFFSET;
ctl = pci_resource_start(dev, 0) + IOC4_CTRL_OFFSET;
irqport = pci_resource_start(dev, 0) + IOC4_INTR_OFFSET;
dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
if (!request_region(base, IOC4_CMD_CTL_BLK_SIZE, hwif->name)) {
printk(KERN_ERR
"%s : %s -- ERROR, Port Addresses "
"0x%p to 0x%p ALREADY in use\n",
__FUNCTION__, hwif->name, (void *) base,
(void *) base + IOC4_CMD_CTL_BLK_SIZE);
return -ENOMEM;
}
if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
/* Initialize the IO registers */
sgiioc4_init_hwif_ports(&hwif->hw, base, ctl, irqport);
memcpy(hwif->io_ports, hwif->hw.io_ports,
sizeof (hwif->io_ports));
hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
}
hwif->irq = dev->irq;
hwif->chipset = ide_pci;
hwif->pci_dev = dev;
hwif->channel = 0; /* Single Channel chip */
hwif->cds = (struct ide_pci_device_s *) d;
hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
/* Initializing chipset IRQ Registers */
hwif->OUTL(0x03, irqport + IOC4_INTR_SET * 4);
ide_init_sgiioc4(hwif);
if (dma_base)
ide_dma_sgiioc4(hwif, dma_base);
else
printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
hwif->name, d->name);
if (probe_hwif_init(hwif))
return -EIO;
/* Create /proc/ide entries */
create_proc_ide_interfaces();
return 0;
}
static int __devinit
sgiioc4_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t * d)
{
unsigned long cmd_base, dma_base, irqport;
unsigned long bar0, cmd_phys_base, ctl;
void __iomem *virt_base;
ide_hwif_t *hwif;
int h;
/*
* Find an empty HWIF; if none available, return -ENOMEM.
*/
for (h = 0; h < MAX_HWIFS; ++h) {
hwif = &ide_hwifs[h];
if (hwif->chipset == ide_unknown)
break;
}
if (h == MAX_HWIFS) {
printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", d->name);
return -ENOMEM;
}
/* Get the CmdBlk and CtrlBlk Base Registers */
bar0 = pci_resource_start(dev, 0);
virt_base = ioremap(bar0, pci_resource_len(dev, 0));
if (virt_base == NULL) {
printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
d->name, bar0);
return -ENOMEM;
}
cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
hwif->name)) {
printk(KERN_ERR
"%s : %s -- ERROR, Addresses "
"0x%p to 0x%p ALREADY in use\n",
__FUNCTION__, hwif->name, (void *) cmd_phys_base,
(void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
return -ENOMEM;
}
if (hwif->io_ports[IDE_DATA_OFFSET] != cmd_base) {
/* Initialize the IO registers */
sgiioc4_init_hwif_ports(&hwif->hw, cmd_base, ctl, irqport);
memcpy(hwif->io_ports, hwif->hw.io_ports,
sizeof (hwif->io_ports));
hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
}
hwif->irq = dev->irq;
hwif->chipset = ide_pci;
hwif->pci_dev = dev;
hwif->channel = 0; /* Single Channel chip */
hwif->cds = (struct ide_pci_device_s *) d;
hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
/* The IOC4 uses MMIO rather than Port IO. */
default_hwif_mmiops(hwif);
/* Initializing chipset IRQ Registers */
writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
ide_init_sgiioc4(hwif);
if (dma_base)
ide_dma_sgiioc4(hwif, dma_base);
else
printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
hwif->name, d->name);
if (probe_hwif_init(hwif))
return -EIO;
/* Create /proc/ide entries */
ide_proc_register_port(hwif);
return 0;
}
static int __init tcf_register(unsigned long dataport,int irq)
{
ide_hwif_t *hwif;
//int i,ret;
hwif = tscf_find_hwif(dataport);
if (hwif) {
//int i;
memset(&hwif->hw, 0, sizeof(hw_regs_t));
/*
* Ensure we're using MMIO
*/
default_hwif_mmiops(hwif);
hwif->mmio = 1;
hwif->io_ports[IDE_DATA_OFFSET] = (unsigned long)ioremap(TS7800_CF_DATA_PHYS_BASE,1);
hwif->io_ports[IDE_ERROR_OFFSET] = (unsigned long)ioremap(TS7800_CF_CMD_PHYS_BASE,1);
hwif->io_ports[IDE_NSECTOR_OFFSET] = (unsigned long)ioremap(TS7800_CF_CMD_PHYS_BASE + 0x1,1);
hwif->io_ports[IDE_SECTOR_OFFSET] = (unsigned long)ioremap(TS7800_CF_CMD_PHYS_BASE + 0x2,1);
hwif->io_ports[IDE_LCYL_OFFSET] = (unsigned long)ioremap(TS7800_CF_CMD_PHYS_BASE + 0x3,1);
hwif->io_ports[IDE_HCYL_OFFSET] = (unsigned long)ioremap(TS7800_CF_CMD_PHYS_BASE + 0x4,1);
hwif->io_ports[IDE_SELECT_OFFSET] = (unsigned long)ioremap(TS7800_CF_CMD_PHYS_BASE + 0x5,1);
hwif->io_ports[IDE_STATUS_OFFSET] = (unsigned long)ioremap(TS7800_CF_CMD_PHYS_BASE + 0x6,1);
hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)ioremap(TS7800_CF_AUX_PHYS_BASE,1);
/*
* This is the dma channel number assigned to this IDE interface. Until
* dma is enabled for this interface, we set it to NO_DMA.
*/
hwif->hw.dma = NO_DMA;
hwif->dma = NO_DMA;
hwif->hw.irq = irq;
hwif->irq = irq;
hwif->noprobe = 0;
hwif->chipset = ide_generic;
//hwif->chipset = ide_forced;
probe_hwif_init(hwif);
//ide_proc_register_port(hwif);
create_proc_ide_interfaces();
//ide_register_hw(hwif,NULL);
}
printk("Technologic Systems TS-7800 IDE initialization - driver version 1.0, 12/27/07. \n");
return 0;
}