/* Entry from cache-as-ram.inc. */
void * asmlinkage romstage_main(unsigned long bist,
uint32_t tsc_low, uint32_t tsc_hi)
{
struct romstage_params rp = {
.bist = bist,
.mrc_params = NULL,
};
/* Save initial timestamp from bootblock. */
timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
/* Save romstage begin */
timestamp_add_now(TS_START_ROMSTAGE);
program_base_addresses();
tco_disable();
byt_config_com1_and_enable();
console_init();
spi_init();
set_max_freq();
punit_init();
gfx_init();
#if CONFIG_EC_GOOGLE_CHROMEEC
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
/* Call into mainboard. */
mainboard_romstage_entry(&rp);
return setup_stack_and_mttrs();
}
/* Entry from cache-as-ram.inc. */
void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low,
uint32_t tsc_hi)
{
struct romstage_params rp = {
.bist = bist,
.mrc_params = NULL,
};
/* Save initial timestamp from bootblock. */
timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
/* Save romstage begin */
timestamp_add_now(TS_START_ROMSTAGE);
program_base_addresses();
tco_disable();
byt_config_com1_and_enable();
console_init();
spi_init();
set_max_freq();
punit_init();
gfx_init();
/* Call into mainboard. */
mainboard_romstage_entry(&rp);
platform_enter_postcar();
/* We don't return here */
return NULL;
}
/* Entry from cache-as-ram.inc. */
void main(FSP_INFO_HEADER *fsp_info_header)
{
uint32_t *func_dis = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS);
uint32_t *func_dis2 = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS2);
uint32_t fd_mask = 0;
uint32_t fd2_mask = 0;
post_code(0x40);
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
program_base_addresses();
post_code(0x41);
tco_disable();
post_code(0x42);
byt_config_com1_and_enable();
post_code(0x43);
console_init();
spi_init();
baytrail_rtc_init();
/* Call into mainboard. */
early_mainboard_romstage_entry();
set_max_freq();
post_code(0x44);
/* Program any required function disables */
get_func_disables(&fd_mask, &fd2_mask);
if (fd_mask != 0) {
write32(func_dis, read32(func_dis) | fd_mask);
/* Ensure posted write hits. */
read32(func_dis);
}
if (fd2_mask != 0) {
write32(func_dis2, read32(func_dis2) | fd2_mask);
/* Ensure posted write hits. */
read32(func_dis2);
}
post_code(0x47);
timestamp_add_now(TS_BEFORE_INITRAM);
/*
* Call early init to initialize memory and chipset. This function returns
* to the romstage_main_continue function with a pointer to the HOB
* structure.
*/
post_code(0x48);
printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
fsp_early_init(fsp_info_header);
die("Uh Oh! fsp_early_init should not return here.\n");
}