/**
* This function initializes the system using the psu_init()
*
* @param FsblInstancePtr is pointer to the XFsbl Instance
*
* @return returns the error codes described in xfsbl_error.h on any error
* returns XFSBL_SUCCESS on success
*
******************************************************************************/
static u32 XFsbl_SystemInit(XFsblPs * FsblInstancePtr)
{
u32 Status = XFSBL_SUCCESS;
/**
* psu initialization
*/
Status = (u32)psu_init();
if (XFSBL_SUCCESS != Status) {
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_PSU_INIT_FAILED\n\r");
/**
* Need to check a way to communicate both FSBL code
* and PSU init error code
*/
Status = XFSBL_PSU_INIT_FAILED + Status;
goto END;
}
/**
* DDR Check if present
*/
/**
* Poweroff the unused blocks as per PSU
*/
END:
return Status;
}
void ICACHE_FLASH_ATTR user_init(void) {
uart_div_modify(0, UART_CLK_FREQ / BAUD);
os_printf("Startup\r\n");
/*** Initialize subsystems ***/
psu_init();
ws2811dma_init();
wifi_init();
mxp_init(ws2811dma_put);
psu_server_init();
/*** Use LED strip as status indicator ***/
wifi_set_event_handler_cb(onWifiEvent);
status_indicate(STAT_NO_CONNECT);
}
void board_init_f(ulong dummy)
{
psu_init();
board_early_init_r();
#ifdef CONFIG_DEBUG_UART
/* Uart debug for sure */
debug_uart_init();
puts("Debug uart enabled\n"); /* or printch() */
#endif
/* Delay is required for clocks to be propagated */
udelay(1000000);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
/* No need to call timer init - it is empty for ZynqMP */
board_init_r(NULL, 0);
}
/**
* This function initializes the system using the psu_init()
*
* @param FsblInstancePtr is pointer to the XFsbl Instance
*
* @return returns the error codes described in xfsbl_error.h on any error
* returns XFSBL_SUCCESS on success
*
******************************************************************************/
static u32 XFsbl_SystemInit(XFsblPs * FsblInstancePtr)
{
u32 Status = XFSBL_SUCCESS;
#if defined (XPAR_PSU_DDR_0_S_AXI_BASEADDR) && !defined (ARMR5)
u32 BlockNum;
#endif
/**
* MIO33 can be used to control power to PL through PMU.
* For 1.0 and 2.0 Silicon, a workaround is needed to Powerup PL
* before MIO33 is configured. Hence, before MIO configuration,
* Powerup PL (but restore isolation).
*/
if (XGetPSVersion_Info() <= XPS_VERSION_2) {
Status = XFsbl_PowerUpIsland(PMU_GLOBAL_PWR_STATE_PL_MASK);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_PL_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_PL_POWER_UP\r\n");
goto END;
}
/* For PS only reset, make sure FSBL exits with isolation removed */
if (FsblInstancePtr->ResetReason != PS_ONLY_RESET) {
XFsbl_IsolationRestore(PMU_GLOBAL_REQ_ISO_INT_EN_PL_NONPCAP_MASK);
}
}
/**
* psu initialization
*/
Status = (u32)psu_init();
if (XFSBL_SUCCESS != Status) {
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_PSU_INIT_FAILED\n\r");
/**
* Need to check a way to communicate both FSBL code
* and PSU init error code
*/
Status = XFSBL_PSU_INIT_FAILED + Status;
goto END;
}
#ifdef XFSBL_PERF
XTime_GetTime(&(FsblInstancePtr->PerfTime.tFsblStart));
#endif
#if defined (XPAR_PSU_DDR_0_S_AXI_BASEADDR) && !defined (ARMR5)
/* For A53, mark DDR region as "Memory" as DDR initialization is done */
#ifdef ARMA53_64
/* For A53 64bit*/
for(BlockNum = 0; BlockNum < NUM_BLOCKS_A53_64; BlockNum++)
{
XFsbl_SetTlbAttributes(BlockNum * BLOCK_SIZE_A53_64, ATTRIB_MEMORY_A53_64);
}
Xil_DCacheFlush();
#else
/* For A53 32bit*/
for(BlockNum = 0; BlockNum < NUM_BLOCKS_A53_32; BlockNum++)
{
XFsbl_SetTlbAttributes(BlockNum * BLOCK_SIZE_A53_32, ATTRIB_MEMORY_A53_32);
}
Xil_DCacheFlush();
#endif
#endif
/**
* Forcing the SD card detection signal to bypass the debouncing logic.
* This will ensure that SD controller doesn't end up waiting for long,
* fixed durations for card to be stable.
*/
XFsbl_Out32(IOU_SLCR_SD_CDN_CTRL,
(IOU_SLCR_SD_CDN_CTRL_SD1_CDN_CTRL_MASK |
IOU_SLCR_SD_CDN_CTRL_SD0_CDN_CTRL_MASK));
/**
* DDR Check if present
*/
/**
* Poweroff the unused blocks as per PSU
*/
END:
return Status;
}
