void psxRcntWtarget( u32 index, u32 value )
{
verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
psxRcntUpdate();
rcnts[index].target = value;
_psxRcntWcount( index, _psxRcntRcount( index ) );
psxRcntSet();
}
void psxRcntWmode( u32 index, u32 value )
{
#ifdef DEBUG_BIOS
dbgf("[RCNT %i] wmode: %x\n", index, value );
#endif
psxRcntUpdate();
rcnts[index].mode = value;
rcnts[index].irqState = 0;
switch( index )
{
case 0:
if( value & Rc0PixelClock )
{
rcnts[index].rate = 5;
}
else
{
rcnts[index].rate = 1;
}
break;
case 1:
if( value & Rc1HSyncClock )
{
rcnts[index].rate = rcnt_target;
}
else
{
rcnts[index].rate = 1;
}
break;
case 2:
if( value & Rc2OneEighthClock )
{
rcnts[index].rate = 8;
}
else
{
rcnts[index].rate = 1;
}
// TODO: wcount must work.
if( value & Rc2Disable )
{
rcnts[index].rate = 0xffffffff;
}
break;
}
_psxRcntWcount( index, 0 );
psxRcntSet();
}
void psxBranchTest() {
if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
psxRcntUpdate();
if (psxHu32(0x1070) & psxHu32(0x1074)) {
if ((psxRegs.CP0.n.Status & 0x401) == 0x401) {
psxException(0x400, 0);
}
}
}
void psxRcntWcount( u32 index, u32 value )
{
#ifdef DEBUG_BIOS
dbgf("[RCNT %i] wcount: %x\n", index, value );
#endif
psxRcntUpdate();
_psxRcntWcount( index, value );
psxRcntSet();
}
void psxRcntWmode( u32 index, u32 value )
{
verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
psxRcntUpdate();
rcnts[index].mode = value;
rcnts[index].irqState = 0;
switch( index )
{
case 0:
if( value & Rc0PixelClock )
{
rcnts[index].rate = 5;
}
else
{
rcnts[index].rate = 1;
}
break;
case 1:
if( value & Rc1HSyncClock )
{
rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
}
else
{
rcnts[index].rate = 1;
}
break;
case 2:
if( value & Rc2OneEighthClock )
{
rcnts[index].rate = 8;
}
else
{
rcnts[index].rate = 1;
}
// TODO: wcount must work.
if( value & Rc2Disable )
{
rcnts[index].rate = 0xffffffff;
}
break;
}
_psxRcntWcount( index, 0 );
psxRcntSet();
}
u32 psxRcntRcount( u32 index )
{
#ifdef DEBUG_ANALYSIS
dbg_anacnt_psxRcntRcount++;
#endif
pcsx4all_prof_start_with_pause(PCSX4ALL_PROF_COUNTERS,PCSX4ALL_PROF_CPU);
u32 count;
#ifndef USE_NO_IDLE_LOOP
if (autobias) {
u32 cycle_next=rcnts[index].cycle+rcnts[index].cycleStart;
if (cycle_next>psxRegs.cycle) {
if (psxRegs.io_cycle_counter>(psxRegs.cycle+32) && psxRegs.io_cycle_counter<cycle_next) {
cycle_next = psxRegs.io_cycle_counter - psxRegs.cycle - 24;
} else {
cycle_next = 12+((cycle_next - psxRegs.cycle)&0x1FF);
}
if (rcnts[index].target) {
unsigned value=(((rcnts[index].target)*(rcnts[index].rate+1))/4)*BIAS;
if (value<cycle_next)
psxRegs.cycle+=value;
else
psxRegs.cycle+=cycle_next;
} else {
psxRegs.cycle+=cycle_next;
}
}
}
#endif
psxRcntUpdate();
count = _psxRcntRcount( index );
// Parasite Eve 2 fix.
if( Config.RCntFix )
{
if( index == 2 )
{
if( rcnts[index].counterState == CountToTarget )
{
count=UDIV(count,BIAS);
}
}
}
#ifdef DEBUG_BIOS
dbgf("[RCNT %i] rcount: %x\n", index, count );
#endif
pcsx4all_prof_end_with_resume(PCSX4ALL_PROF_COUNTERS,PCSX4ALL_PROF_CPU);
return count;
}
u32 psxRcntRmode( u32 index )
{
u16 mode;
psxRcntUpdate();
mode = rcnts[index].mode;
rcnts[index].mode &= 0xe7ff;
verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
return mode;
}
void psxRcntWtarget( u32 index, u32 value )
{
#ifdef DEBUG_BIOS
dbgf("[RCNT %i] wtarget: %x\n", index, value );
#endif
psxRcntUpdate();
rcnts[index].target = value;
_psxRcntWcount( index, _psxRcntRcount( index ) );
psxRcntSet();
}
u32 psxRcntRmode( u32 index )
{
#ifdef DEBUG_ANALYSIS
dbg_anacnt_psxRcntRmode++;
#endif
pcsx4all_prof_start_with_pause(PCSX4ALL_PROF_COUNTERS,PCSX4ALL_PROF_CPU);
u16 mode;
psxRcntUpdate();
mode = rcnts[index].mode;
rcnts[index].mode &= 0xe7ff;
#ifdef DEBUG_BIOS
dbgf("[RCNT %i] rmode: %x\n", index, mode );
#endif
pcsx4all_prof_end_with_resume(PCSX4ALL_PROF_COUNTERS,PCSX4ALL_PROF_CPU);
return mode;
}
u32 psxRcntRcount( u32 index )
{
u32 count;
psxRcntUpdate();
count = _psxRcntRcount( index );
// Parasite Eve 2 fix - artificial clock jitter based on BIAS
// TODO: any other games depend on getting excepted value from RCNT?
if( Config.HackFix && index == 2 && rcnts[index].counterState == CountToTarget && (Config.RCntFix || ((rcnts[index].mode & 0x2FF) == JITTER_FLAGS)) )
{
/*
*The problem is that...
*
*We generate too many cycles during PSX HW hardware operations.
*
*OR
*
*We simply count too many cycles here for RCNTs.
*
*OR
*
*RCNT implementation here is only 99% compatible. Assumed this since easities to fix (only PE2 known to be affected).
*/
static u32 clast = 0xffff;
static u32 cylast = 0;
u32 count1 = count;
count /= BIAS;
verboseLog( 4, "[RCNT %i] rcountpe2: %x %x %x (%u)\n", index, count, count1, clast, (psxRegs.cycle-cylast));
cylast=psxRegs.cycle;
clast=count;
}
verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
return count;
}
u32 psxRcntRcount( u32 index )
{
u32 count;
psxRcntUpdate();
count = _psxRcntRcount( index );
// Parasite Eve 2 fix.
if( Config.RCntFix )
{
if( index == 2 )
{
if( rcnts[index].counterState == CountToTarget )
{
count /= BIAS;
}
}
}
verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
return count;
}
void psxBranchTest() {
if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
psxRcntUpdate();
if (psxRegs.interrupt) {
if ((psxRegs.interrupt & (1 << PSXINT_SIO)) && !Config.Sio) { // sio
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_SIO);
sioInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDR);
cdrInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
cdrReadInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
gpuInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
mdec1Interrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
spuInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
mdec0Interrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
gpuotcInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
cdrDmaInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDRPLAY)) { // cdr play timing
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRPLAY].sCycle) >= psxRegs.intCycle[PSXINT_CDRPLAY].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDRPLAY);
cdrPlayInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDRDBUF)) { // cdr decoded buffer
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDBUF].sCycle) >= psxRegs.intCycle[PSXINT_CDRDBUF].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDRDBUF);
cdrDecodedBufferInterrupt();
}
}
if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
cdrLidSeekInterrupt();
}
}
}
if (psxHu32(0x1070) & psxHu32(0x1074)) {
if ((psxRegs.CP0.n.Status & 0x401) == 0x401) {
#ifdef PSXCPU_LOG
PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074));
#endif
psxException(0x400, 0);
}
}
}