static void push_irq_registers(struct MC6809 *cpu) { NVMA_CYCLE; push_word(cpu, ®_S, REG_PC); push_word(cpu, ®_S, REG_U); push_word(cpu, ®_S, REG_Y); push_word(cpu, ®_S, REG_X); push_byte(cpu, ®_S, REG_DP); push_byte(cpu, ®_S, RREG_B); push_byte(cpu, ®_S, RREG_A); push_byte(cpu, ®_S, REG_CC); }
static void psh(struct MC6809 *cpu, uint16_t *s, uint16_t as) { unsigned postbyte; postbyte = byte_immediate(cpu); NVMA_CYCLE; NVMA_CYCLE; peek_byte(cpu, *s); if (postbyte & 0x80) { push_word(cpu, s, REG_PC); } if (postbyte & 0x40) { push_word(cpu, s, as); } if (postbyte & 0x20) { push_word(cpu, s, REG_Y); } if (postbyte & 0x10) { push_word(cpu, s, REG_X); } if (postbyte & 0x08) { push_byte(cpu, s, REG_DP); } if (postbyte & 0x04) { push_byte(cpu, s, RREG_B); } if (postbyte & 0x02) { push_byte(cpu, s, RREG_A); } if (postbyte & 0x01) { push_byte(cpu, s, REG_CC); } }
void interrupts_step(t_gameboy *gb) { static struct { uint16_t address; void (*function)(t_gameboy *gb); } const interrupts [] = { {0x40, &vblank}, {0x48, &lcd_stat}, {0x50, &timer}, {0x58, &serial}, {0x60, &joypad}, }; uint8_t ints = *gb->hregisters._if & *gb->hregisters.ie; if (!(gb->interrupts.master && ints)) return ; for (unsigned i = 0; i < (sizeof(interrupts) / sizeof(interrupts[0])); ++i) { if (ints & (1 << i)) { *gb->hregisters._if &= (0xFF ^ (1 << i)); gb->interrupts.master = false; push_word(gb, gb->registers.pc); gb->registers.pc = interrupts[i].address; (*interrupts[i].function)(gb); break ; } } }
static int sax_window_get_word(lua_State* lua) { luaL_argcheck(lua, lua_gettop(lua) == 1, 0, "incorrect number of args"); sts_window window = check_sax_window(lua, 1); push_word(lua, sts_dup_word(&window->current_word)); return 1; }
//setup to run the code at the address, that the Interrupt Vector points to... static void setupInt(int intNum) { DEBUG_PRINTF_INTR("%s(%x): executing interrupt handler @%08x\n", __func__, intNum, my_rdl(intNum * 4)); // push current R_FLG... will be popped by IRET push_word((u16) M.x86.R_FLG); CLEAR_FLAG(F_IF); CLEAR_FLAG(F_TF); // push current CS:IP to the stack, will be popped by IRET push_word(M.x86.R_CS); push_word(M.x86.R_IP); // set CS:IP to the interrupt handler address... so the next executed instruction will // be the interrupt handler M.x86.R_CS = my_rdw(intNum * 4 + 2); M.x86.R_IP = my_rdw(intNum * 4); }
/*************************************************************** Return the current state of all parts of robot ***************************************************************/ void return_all() { //printf(" in return_all_sensors() "); start_checksum(); push_char(0x50); push_char(0xAF); push_char(0x81); push_word(get_sonar(1)); push_word(get_sonar(2)); push_word(get_sonar(3)); push_word(get_line_follower(1)); push_word(get_line_follower(2)); push_word(get_line_follower(3)); push_word(get_gyro()); push_byte(get_bumper(1)); # check new spec push_byte(get_bumper(2)); push_byte(get_motor(1)); push_byte(get_motor(2)); push_byte(get_motor(3)); send_checksum(); // Now 3 + 6 + 6 + 2 + 2 + 3 + 1 = 23 }
void do_return (byte numWords) { StackFrame *stackFrame; STACKWORD *fromStackPtr; stackFrame = current_stackframe(); #if DEBUG_BYTECODE printf ("\n------ return ----- %d ------------------\n\n", stackFrame->methodRecord->signatureId); #endif #if DEBUG_METHODS printf ("do_return: method: %d # num. words: %d\n", stackFrame->methodRecord->signatureId, numWords); #endif #ifdef VERIFY assert (stackFrame != null, LANGUAGE3); #endif if (stackFrame->monitor != null) exit_monitor (currentThread, stackFrame->monitor); #if DEBUG_THREADS || DEBUG_METHODS printf ("do_return: stack frame array size: %d\n", currentThread->stackFrameArraySize); #endif if (currentThread->stackFrameArraySize == 1) { #if DEBUG_METHODS printf ("do_return: thread is done: %d\n", (int) currentThread); #endif currentThread->state = DEAD; schedule_request (REQUEST_SWITCH_THREAD); return; } // Place source ptr below data to be copied up the stack fromStackPtr = get_stack_ptr_at (numWords); // Pop stack frame currentThread->stackFrameArraySize--; stackFrame--; // Assign registers update_registers (stackFrame); #if DEBUG_METHODS printf ("do_return: stack reset to:\n"); printf ("-- stack ptr = %d\n", (int) get_stack_ptr()); #endif while (numWords--) { push_word (*(++fromStackPtr)); } }
/**************************************************************************** REMARKS: Handles any pending asychronous interrupts. ****************************************************************************/ static void x86emu_intr_handle(void) { u8 intno; if (M.x86.intr & INTR_SYNCH) { intno = M.x86.intno; if (_X86EMU_intrTab[intno]) { (*_X86EMU_intrTab[intno])(intno); } else { push_word((u16)M.x86.R_FLG); CLEAR_FLAG(F_IF); CLEAR_FLAG(F_TF); push_word(M.x86.R_CS); M.x86.R_CS = mem_access_word(intno * 4 + 2); push_word(M.x86.R_IP); M.x86.R_IP = mem_access_word(intno * 4); M.x86.intr = 0; } } }
static int sax_from_string(lua_State* lua) { size_t len; const char* s = luaL_checklstring(lua, 1, &len); luaL_argcheck(lua, len > 1, 1, "length of SAX string should be > 1"); int c = luaL_checkint(lua, 2); sts_word a = sts_from_sax_string(s, c); if (!a) { return luaL_argerror(lua, 1, "illegal symbols for given cardinality " "or bad cardinality itself"); } push_word(lua, a); return 1; }
void m68k_push_dummy_frame () { register CORE_ADDR sp = read_register (SP_REGNUM); register int regnum; char raw_buffer[12]; sp = push_word (sp, read_register (PC_REGNUM)); sp = push_word (sp, read_register (FP_REGNUM)); write_register (FP_REGNUM, sp); #if defined (HAVE_68881) for (regnum = FP0_REGNUM + 7; regnum >= FP0_REGNUM; regnum--) { read_register_bytes (REGISTER_BYTE (regnum), raw_buffer, 12); sp = push_bytes (sp, raw_buffer, 12); } #endif for (regnum = FP_REGNUM - 1; regnum >= 0; regnum--) { sp = push_word (sp, read_register (regnum)); } sp = push_word (sp, read_register (PS_REGNUM)); write_register (SP_REGNUM, sp); }
static int sax_from_double_array(lua_State* lua) { int w = luaL_checkint(lua, 2); int c = luaL_checkint(lua, 3); if (!lua_istable(lua, 1)) { return luaL_argerror(lua, 1, "array-like table expected"); } size_t size = lua_objlen(lua, 1); check_nwc(lua, (int)size, w, c, 2); double* buf = check_array(lua, 1, size); sts_word a = sts_from_double_array(buf, size, w, c); free(buf); if (!a) { return luaL_error(lua, "memory allocation failed"); } push_word(lua, a); return 1; }
// prepare and execute Interrupt 13 (Disk Interrupt) void runInt13(void) { // Initialize stack and data segment M.x86.R_SS = STACK_SEGMENT; M.x86.R_DS = DATA_SEGMENT; M.x86.R_SP = STACK_START_OFFSET; // push a HLT instruction and a pointer to it onto the stack // any return will pop the pointer and jump to the HLT, thus // exiting (more or less) cleanly push_word(0xf4f4); //F4=HLT //push_word(M.x86.R_SS); //push_word(M.x86.R_SP + 2); // setupInt will push the current CS and IP to the stack to return to it, // but we want to halt, so set CS:IP to the HLT instruction we just pushed // to the stack M.x86.R_CS = M.x86.R_SS; M.x86.R_IP = M.x86.R_SP; CHECK_DBG(DEBUG_TRACE_X86EMU) { X86EMU_trace_on(); } CHECK_DBG(DEBUG_JMP) { M.x86.debug |= DEBUG_TRACEJMP_REGS_F; M.x86.debug |= DEBUG_TRACEJMP_REGS_F; M.x86.debug |= DEBUG_TRACECALL_F; M.x86.debug |= DEBUG_TRACECALL_REGS_F; } setupInt(0x13); DEBUG_PRINTF_INTR("%s(): starting execution of INT13...\n", __func__); X86EMU_exec(); DEBUG_PRINTF_INTR("%s(): execution finished\n", __func__); }
/** * NOTE: The technique is not the same as that used in TinyVM. * The return value indicates the impact of the call on the VM * system. EXEC_CONTINUE normal return the system should return to the return * address provided by the VM. EXEC_RUN The call has modified the value of * VM PC and this should be used to restart execution. EXEC_RETRY The call * needs to be re-tried (typically for a GC failure), all global state * should be left intact, the PC has been set appropriately. * */ int dispatch_native(TWOBYTES signature, STACKWORD * paramBase) { STACKWORD p0 = paramBase[0]; switch (signature) { case wait_4_5V: return monitor_wait((Object *) word2ptr(p0), 0); case wait_4J_5V: return monitor_wait((Object *) word2ptr(p0), ((int)paramBase[1] > 0 ? 0x7fffffff : paramBase[2])); case notify_4_5V: return monitor_notify((Object *) word2ptr(p0), false); case notifyAll_4_5V: return monitor_notify((Object *) word2ptr(p0), true); case start_4_5V: // Create thread, allow for instruction restart return init_thread((Thread *) word2ptr(p0)); case yield_4_5V: schedule_request(REQUEST_SWITCH_THREAD); break; case sleep_4J_5V: sleep_thread(((int)p0 > 0 ? 0x7fffffff : paramBase[1])); schedule_request(REQUEST_SWITCH_THREAD); break; case getPriority_4_5I: push_word(get_thread_priority((Thread *) word2ptr(p0))); break; case setPriority_4I_5V: { STACKWORD p = (STACKWORD) paramBase[1]; if (p > MAX_PRIORITY || p < MIN_PRIORITY) return throw_new_exception(JAVA_LANG_ILLEGALARGUMENTEXCEPTION); else set_thread_priority((Thread *) word2ptr(p0), p); } break; case currentThread_4_5Ljava_3lang_3Thread_2: push_ref(ptr2ref(currentThread)); break; case interrupt_4_5V: interrupt_thread((Thread *) word2ptr(p0)); break; case interrupted_4_5Z: { JBYTE i = currentThread->interruptState != INTERRUPT_CLEARED; currentThread->interruptState = INTERRUPT_CLEARED; push_word(i); } break; case isInterrupted_4_5Z: push_word(((Thread *) word2ptr(p0))->interruptState != INTERRUPT_CLEARED); break; case join_4_5V: join_thread((Thread *) word2ptr(p0), 0); break; case join_4J_5V: join_thread((Thread *) word2obj(p0), paramBase[2]); break; case halt_4I_5V: schedule_request(REQUEST_EXIT); break; case shutdown_4_5V: shutdown_program(false); break; case currentTimeMillis_4_5J: push_word(0); push_word(systick_get_ms()); break; case readSensorValue_4I_5I: push_word(sp_read(p0, SP_ANA)); break; case setPowerTypeById_4II_5V: sp_set_power(p0, paramBase[1]); break; case freeMemory_4_5J: push_word(0); push_word(getHeapFree()); break; case totalMemory_4_5J: push_word(0); push_word(getHeapSize()); break; case floatToRawIntBits_4F_5I: // Fall through case intBitsToFloat_4I_5F: push_word(p0); break; case doubleToRawLongBits_4D_5J: // Fall through case longBitsToDouble_4J_5D: push_word(p0); push_word(paramBase[1]); break; case drawString_4Ljava_3lang_3String_2II_5V: { String *p = (String *)word2obj(p0); Object *charArray; if (!p) return throw_new_exception(JAVA_LANG_NULLPOINTEREXCEPTION); charArray = (Object *) word2ptr(get_word_4_ns(fields_start(p))); if (!charArray) return throw_new_exception(JAVA_LANG_NULLPOINTEREXCEPTION); display_goto_xy(paramBase[1], paramBase[2]); display_jstring(p); } break; case drawInt_4III_5V: display_goto_xy(paramBase[1], paramBase[2]); display_int(p0, 0); break; case drawInt_4IIII_5V: display_goto_xy(paramBase[2], paramBase[3]); display_int(p0, paramBase[1]); break; case asyncRefresh_4_5V: display_update(); break; case clear_4_5V: display_clear(0); break; case getDisplay_4_5_1B: push_word(display_get_array()); break; case setAutoRefreshPeriod_4I_5I: push_word(display_set_auto_update_period(p0)); break; case getRefreshCompleteTime_4_5I: push_word(display_get_update_complete_time()); break; case bitBlt_4_1BIIII_1BIIIIIII_5V: { Object *src = word2ptr(p0); Object *dst = word2ptr(paramBase[5]); display_bitblt((byte *)(src != NULL ?jbyte_array(src):NULL), paramBase[1], paramBase[2], paramBase[3], paramBase[4], (byte *)(dst!=NULL?jbyte_array(dst):NULL), paramBase[6], paramBase[7], paramBase[8], paramBase[9], paramBase[10], paramBase[11], paramBase[12]); break; } case getSystemFont_4_5_1B: push_word(display_get_font()); break; case setContrast_4I_5V: nxt_lcd_set_pot(p0); break; case getBatteryStatus_4_5I: push_word(battery_voltage()); break; case getButtons_4_5I: push_word(buttons_get()); break; case getTachoCountById_4I_5I: push_word(nxt_motor_get_count(p0)); break; case controlMotorById_4III_5V: nxt_motor_set_speed(p0, paramBase[1], paramBase[2]); break; case resetTachoCountById_4I_5V: nxt_motor_set_count(p0, 0); break; case i2cEnableById_4II_5V: if (i2c_enable(p0, paramBase[1]) == 0) return EXEC_RETRY; else break; case i2cDisableById_4I_5V: i2c_disable(p0); break; case i2cStatusById_4I_5I: push_word(i2c_status(p0)); break; case i2cStartById_4II_1BIII_5I: { Object *p = word2obj(paramBase[2]); JBYTE *byteArray = p ? jbyte_array(p) + paramBase[3] : NULL; push_word(i2c_start(p0, paramBase[1], (U8 *)byteArray, paramBase[4], paramBase[5])); } break; case i2cCompleteById_4I_1BII_5I: { Object *p = word2ptr(paramBase[1]); JBYTE *byteArray = p ? jbyte_array(p) + paramBase[2] : NULL; push_word(i2c_complete(p0, (U8 *)byteArray, paramBase[3])); } break; case playFreq_4III_5V: sound_freq(p0,paramBase[1], paramBase[2]); break; case btGetBC4CmdMode_4_5I: push_word(bt_get_mode()); break; case btSetArmCmdMode_4I_5V: if (p0 == 0) bt_set_arm7_cmd(); else bt_clear_arm7_cmd(); break; case btSetResetLow_4_5V: bt_set_reset_low(); break; case btSetResetHigh_4_5V: bt_set_reset_high(); break; case btWrite_4_1BII_5I: { Object *p = word2ptr(p0); byte *byteArray = (byte *) jbyte_array(p); push_word(bt_write(byteArray, paramBase[1], paramBase[2])); } break; case btRead_4_1BII_5I: { Object *p = word2ptr(p0); byte *byteArray = (byte *) jbyte_array(p); push_word(bt_read(byteArray, paramBase[1], paramBase[2])); } break; case btPending_4_5I: { push_word(bt_event_check(0xffffffff)); } break; case btEnable_4_5V: if (bt_enable() == 0) return EXEC_RETRY; else break; case btDisable_4_5V: bt_disable(); break; case usbRead_4_1BII_5I: { Object *p = word2ptr(p0); byte *byteArray = (byte *) jbyte_array(p); push_word(udp_read(byteArray,paramBase[1], paramBase[2])); } break; case usbWrite_4_1BII_5I: { Object *p = word2ptr(p0); byte *byteArray = (byte *) jbyte_array(p); push_word(udp_write(byteArray,paramBase[1], paramBase[2])); } break; case usbStatus_4_5I: { push_word(udp_event_check(0xffffffff)); } break; case usbEnable_4I_5V: { udp_enable(p0); } break; case usbDisable_4_5V: { udp_disable(); } break; case usbReset_4_5V: udp_reset(); break; case usbSetSerialNo_4Ljava_3lang_3String_2_5V: { byte *p = word2ptr(p0); int len; Object *charArray = (Object *) word2ptr(get_word_4_ns(fields_start(p))); len = get_array_length(charArray); udp_set_serialno((U8 *)jchar_array(charArray), len); } break; case usbSetName_4Ljava_3lang_3String_2_5V: { byte *p = word2ptr(p0); int len; Object *charArray = (Object *) word2ptr(get_word_4_ns(fields_start(p))); len = get_array_length(charArray); udp_set_name((U8 *)jchar_array(charArray), len); } break; case flashWritePage_4_1BI_5I: { Object *p = word2ptr(p0); unsigned long *intArray = (unsigned long *) jint_array(p); push_word(flash_write_page(intArray,paramBase[1])); } break; case flashReadPage_4_1BI_5I: { Object *p = word2ptr(p0); unsigned long *intArray = (unsigned long *) jint_array(p); push_word(flash_read_page(intArray,paramBase[1])); } break; case flashExec_4II_5I: push_word(run_program((byte *)(&FLASH_BASE[(p0*FLASH_PAGE_SIZE)]), paramBase[1])); break; case playSample_4IIIII_5V: sound_play_sample(((unsigned char *) &FLASH_BASE[(p0*FLASH_PAGE_SIZE)]) + paramBase[1],paramBase[2],paramBase[3],paramBase[4]); break; case playQueuedSample_4_1BIIII_5I: push_word(sound_add_sample((U8 *)jbyte_array(word2obj(p0)) + paramBase[1],paramBase[2],paramBase[3],paramBase[4])); break; case getTime_4_5I: push_word(sound_get_time()); break; case getDataAddress_4Ljava_3lang_3Object_2_5I: if (is_array(word2obj(p0))) push_word (ptr2word ((byte *) array_start(word2ptr(p0)))); else push_word (ptr2word ((byte *) fields_start(word2ptr(p0)))); break; case getObjectAddress_4Ljava_3lang_3Object_2_5I: push_word(p0); break; case gc_4_5V: // Restartable garbage collection return garbage_collect(); case shutDown_4_5V: shutdown(); // does not return case boot_4_5V: display_clear(1); while (1) nxt_avr_firmware_update_mode(); // does not return case arraycopy_4Ljava_3lang_3Object_2ILjava_3lang_3Object_2II_5V: return arraycopy(word2ptr(p0), paramBase[1], word2ptr(paramBase[2]), paramBase[3], paramBase[4]); case executeProgram_4I_5V: // Exceute program, allow for instruction re-start return execute_program(p0); case setDebug_4_5V: set_debug(word2ptr(p0)); break; case eventOptions_4II_5I: { byte old = debugEventOptions[p0]; debugEventOptions[p0] = (byte)paramBase[1]; push_word(old); } break; case suspendThread_4Ljava_3lang_3Object_2_5V: suspend_thread(ref2ptr(p0)); break; case resumeThread_4Ljava_3lang_3Object_2_5V: resume_thread(ref2ptr(p0)); break; case getProgramExecutionsCount_4_5I: push_word(gProgramExecutions); break; case getFirmwareRevision_4_5I: push_word((STACKWORD) getRevision()); break; case getFirmwareRawVersion_4_5I: push_word((STACKWORD) VERSION_NUMBER); break; case hsEnable_4II_5V: { if (hs_enable((int)p0, (int)paramBase[1]) == 0) return EXEC_RETRY; } break; case hsDisable_4_5V: { hs_disable(); } break; case hsWrite_4_1BII_5I: { Object *p = word2ptr(p0); byte *byteArray = (byte *) jbyte_array(p); push_word(hs_write(byteArray, paramBase[1], paramBase[2])); } break; case hsRead_4_1BII_5I: { Object *p = word2ptr(p0); byte *byteArray = (byte *) jbyte_array(p); push_word(hs_read(byteArray, paramBase[1], paramBase[2])); } break; case hsPending_4_5I: { push_word(hs_pending()); } break; case hsSend_4BB_1BII_1C_5I: { Object *p = word2ptr(paramBase[2]); U8 *data = (U8 *)jbyte_array(p); p = word2ptr(paramBase[5]); U16 *crc = (U16 *)jchar_array(p); push_word(hs_send((U8) p0, (U8)paramBase[1], data, paramBase[3], paramBase[4], crc)); } break; case hsRecv_4_1BI_1CI_5I: { Object *p = word2ptr(p0); U8 *data = (U8 *)jbyte_array(p); p = word2ptr(paramBase[2]); U16 *crc = (U16 *)jchar_array(p); push_word(hs_recv(data, paramBase[1], crc, paramBase[3])); } break; case getUserPages_4_5I: push_word(FLASH_MAX_PAGES - flash_start_page); break; case setVMOptions_4I_5V: gVMOptions = p0; break; case getVMOptions_4_5I: push_word(gVMOptions); break; case isAssignable_4II_5Z: push_word(is_assignable(p0, paramBase[1])); break; case cloneObject_4Ljava_3lang_3Object_2_5Ljava_3lang_3Object_2: { Object *newObj = clone((Object *)ref2obj(p0)); if (newObj == NULL) return EXEC_RETRY; push_word(obj2ref(newObj)); } break; case memPeek_4III_5I: push_word(mem_peek(p0, paramBase[1], paramBase[2])); break; case memCopy_4Ljava_3lang_3Object_2IIII_5V: mem_copy(word2ptr(p0), paramBase[1], paramBase[2], paramBase[3], paramBase[4]); break; case memGetReference_4II_5Ljava_3lang_3Object_2: push_word(mem_get_reference(p0, paramBase[1])); break; case setSensorPin_4III_5V: sp_set(p0, paramBase[1], paramBase[2]); break; case getSensorPin_4II_5I: push_word(sp_get(p0, paramBase[1])); break; case setSensorPinMode_4III_5V: sp_set_mode(p0, paramBase[1], paramBase[2]); break; case readSensorPin_4II_5I: push_word(sp_read(p0, paramBase[1])); break; case nanoTime_4_5J: { U64 ns = systick_get_ns(); push_word(ns >> 32); push_word(ns); } break; case createStackTrace_4Ljava_3lang_3Thread_2Ljava_3lang_3Object_2_5_1I: { Object *trace = create_stack_trace((Thread *)ref2obj(p0), ref2obj(paramBase[1])); if (trace == NULL) return EXEC_RETRY; push_word(obj2ref(trace)); } break; case registerEvent_4_5I: push_word(register_event((NXTEvent *) ref2obj(p0))); break; case unregisterEvent_4_5I: push_word(unregister_event((NXTEvent *) ref2obj(p0))); break; case changeEvent_4II_5I: push_word(change_event((NXTEvent *) ref2obj(p0), paramBase[1], paramBase[2])); break; case isInitialized_4I_5Z: push_word(is_initialized_idx(p0)); break; case allocate_4II_5Ljava_3lang_3Object_2: { Object *allocated; if(paramBase[1]>0){ allocated=new_single_array(p0,paramBase[1]); }else{ allocated=new_object_for_class(p0); } if(allocated == NULL) return EXEC_RETRY; push_word(obj2ref(allocated)); } break; case memPut_4IIII_5V: store_word_ns((byte *)(memory_base[p0] + paramBase[1]), paramBase[2],paramBase[3]); break; case notifyEvent_4ILjava_3lang_3Thread_2_5Z: push_word(debug_event(paramBase[1], NULL, (Thread*) ref2obj(paramBase[2]), 0, 0, 0, 0)); break; case setThreadRequest_4Ljava_3lang_3Thread_2Llejos_3nxt_3debug_3SteppingRequest_2_5V: { Thread *th = (Thread*) ref2obj(p0); th->debugData = (REFERENCE) paramBase[1]; // currently we only get stepping requests if(paramBase[1]) th->flags |= THREAD_STEPPING; else th->flags &= ~THREAD_STEPPING; } break; case isStepping_4Ljava_3lang_3Thread_2_5Z: { Thread *th = (Thread*) ref2obj(p0); push_word(is_stepping(th)); } break; case setBreakpointList_4_1Llejos_3nxt_3debug_3Breakpoint_2I_5V: breakpoint_set_list((Breakpoint**) array_start(p0), paramBase[1]); break; case enableBreakpoint_4Llejos_3nxt_3debug_3Breakpoint_2Z_5V: breakpoint_enable((Breakpoint*) word2ptr(p0), (boolean) paramBase[1]); break; case firmwareExceptionHandler_4Ljava_3lang_3Throwable_2II_5V: firmware_exception_handler((Throwable *)p0, paramBase[1], paramBase[2]); break; case exitThread_4_5V: currentThread->state = DEAD; schedule_request(REQUEST_SWITCH_THREAD); break; case updateThreadFlags_4Ljava_3lang_3Thread_2II_5I: ((Thread *)p0)->flags |= paramBase[1]; ((Thread *)p0)->flags &= ~paramBase[2]; //printf("m %x %d\n", p0, ((Thread *)p0)->flags); push_word(((Thread *)p0)->flags); break; default: return throw_new_exception(JAVA_LANG_NOSUCHMETHODERROR); } return EXEC_CONTINUE; }
// handle int1a (PCI BIOS Interrupt) static void handleInt1a(void) { // function number in AX u8 bus, devfn, offs; struct device* dev; switch (M.x86.R_AX) { case 0xb101: // Installation check CLEAR_FLAG(F_CF); // clear CF M.x86.R_EDX = 0x20494350; // " ICP" endian swapped "PCI " M.x86.R_AL = 0x1; // Config Space Mechanism 1 supported M.x86.R_BX = 0x0210; // PCI Interface Level Version 2.10 M.x86.R_CL = 0xff; // number of last PCI Bus in system TODO: check! break; case 0xb102: // Find PCI Device // device_id in CX, vendor_id in DX // device index in SI (i.e. if multiple devices with same vendor/device id // are connected). We currently only support device index 0 // DEBUG_PRINTF_INTR("%s(): function: %x: PCI Find Device\n", __func__, M.x86.R_AX); /* FixME: support SI != 0 */ #if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); if (dev != 0) { DEBUG_PRINTF_INTR ("%s(): function %x: PCI Find Device --> 0x%04x\n", __func__, M.x86.R_AX, M.x86.R_BX); M.x86.R_BH = dev->bus->secondary; M.x86.R_BL = dev->path.pci.devfn; M.x86.R_AH = 0x00; // return code: success CLEAR_FLAG(F_CF); #else // only allow the device to find itself... if ((M.x86.R_CX == bios_device.pci_device_id) && (M.x86.R_DX == bios_device.pci_vendor_id) // device index must be 0 && (M.x86.R_SI == 0)) { CLEAR_FLAG(F_CF); M.x86.R_AH = 0x00; // return code: success M.x86.R_BH = bios_device.bus; M.x86.R_BL = bios_device.devfn; #endif } else { DEBUG_PRINTF_INTR ("%s(): function %x: invalid device/vendor/device index! (%04x/%04x/%02x expected: %04x/%04x/00) \n", __func__, M.x86.R_AX, M.x86.R_CX, M.x86.R_DX, M.x86.R_SI, bios_device.pci_device_id, bios_device.pci_vendor_id); SET_FLAG(F_CF); M.x86.R_AH = 0x86; // return code: device not found } break; case 0xb108: //read configuration byte case 0xb109: //read configuration word case 0xb10a: //read configuration dword bus = M.x86.R_BH; devfn = M.x86.R_BL; offs = M.x86.R_DI; DEBUG_PRINTF_INTR("%s(): function: %x: PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, M.x86.R_AX, bus, devfn, offs); #if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES dev = dev_find_slot(bus, devfn); DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", __func__, M.x86.R_AX, dev_path(dev)); if (dev == 0) { // fail accesses to non-existent devices... #else dev = bios_device.dev; if ((bus != bios_device.bus) || (devfn != bios_device.devfn)) { // fail accesses to any device but ours... #endif printf ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", __func__, bus, bios_device.bus, devfn, bios_device.devfn, offs); SET_FLAG(F_CF); M.x86.R_AH = 0x87; //return code: bad pci register HALT_SYS(); return; } else { switch (M.x86.R_AX) { case 0xb108: M.x86.R_CL = #if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config8(dev, offs); #else (u8) rtas_pci_config_read(bios_device. puid, 1, bus, devfn, offs); #endif DEBUG_PRINTF_INTR ("%s(): function %x: PCI Config Read @%02x --> 0x%02x\n", __func__, M.x86.R_AX, offs, M.x86.R_CL); break; case 0xb109: M.x86.R_CX = #if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config16(dev, offs); #else (u16) rtas_pci_config_read(bios_device. puid, 2, bus, devfn, offs); #endif DEBUG_PRINTF_INTR ("%s(): function %x: PCI Config Read @%02x --> 0x%04x\n", __func__, M.x86.R_AX, offs, M.x86.R_CX); break; case 0xb10a: M.x86.R_ECX = #if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config32(dev, offs); #else (u32) rtas_pci_config_read(bios_device. puid, 4, bus, devfn, offs); #endif DEBUG_PRINTF_INTR ("%s(): function %x: PCI Config Read @%02x --> 0x%08x\n", __func__, M.x86.R_AX, offs, M.x86.R_ECX); break; } CLEAR_FLAG(F_CF); M.x86.R_AH = 0x0; // return code: success } break; case 0xb10b: //write configuration byte case 0xb10c: //write configuration word case 0xb10d: //write configuration dword bus = M.x86.R_BH; devfn = M.x86.R_BL; offs = M.x86.R_DI; if ((bus != bios_device.bus) || (devfn != bios_device.devfn)) { // fail accesses to any device but ours... printf ("%s(): Config read access invalid! bus: %x (%x), devfn: %x (%x), offs: %x\n", __func__, bus, bios_device.bus, devfn, bios_device.devfn, offs); SET_FLAG(F_CF); M.x86.R_AH = 0x87; //return code: bad pci register HALT_SYS(); return; } else { switch (M.x86.R_AX) { case 0xb10b: #if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config8(bios_device.dev, offs, M.x86.R_CL); #else rtas_pci_config_write(bios_device.puid, 1, bus, devfn, offs, M.x86.R_CL); #endif DEBUG_PRINTF_INTR ("%s(): function %x: PCI Config Write @%02x <-- 0x%02x\n", __func__, M.x86.R_AX, offs, M.x86.R_CL); break; case 0xb10c: #if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config16(bios_device.dev, offs, M.x86.R_CX); #else rtas_pci_config_write(bios_device.puid, 2, bus, devfn, offs, M.x86.R_CX); #endif DEBUG_PRINTF_INTR ("%s(): function %x: PCI Config Write @%02x <-- 0x%04x\n", __func__, M.x86.R_AX, offs, M.x86.R_CX); break; case 0xb10d: #if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config32(bios_device.dev, offs, M.x86.R_ECX); #else rtas_pci_config_write(bios_device.puid, 4, bus, devfn, offs, M.x86.R_ECX); #endif DEBUG_PRINTF_INTR ("%s(): function %x: PCI Config Write @%02x <-- 0x%08x\n", __func__, M.x86.R_AX, offs, M.x86.R_ECX); break; } CLEAR_FLAG(F_CF); M.x86.R_AH = 0x0; // return code: success } break; default: printf("%s(): unknown function (%x) for int1a handler.\n", __func__, M.x86.R_AX); DEBUG_PRINTF_INTR("AX=%04x BX=%04x CX=%04x DX=%04x\n", M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); HALT_SYS(); break; } } // main Interrupt Handler routine, should be registered as x86emu interrupt handler void handleInterrupt(int intNum) { u8 int_handled = 0; #ifndef DEBUG_PRINT_INT10 // this printf makes output by int 10 unreadable... // so we only enable it, if int10 print is disabled DEBUG_PRINTF_INTR("%s(%x)\n", __func__, intNum); #endif /* check wether this interrupt has a function pointer set in yabel_intFuncArray and run that */ if (yabel_intFuncArray[intNum]) { DEBUG_PRINTF_INTR("%s(%x) intHandler overridden, calling it...\n", __func__, intNum); int_handled = (*yabel_intFuncArray[intNum])(); } else { switch (intNum) { case 0x10: //BIOS video interrupt case 0x42: // INT 10h relocated by EGA/VGA BIOS case 0x6d: // INT 10h relocated by VGA BIOS // get interrupt vector from IDT (4 bytes per Interrupt starting at address 0 if ((my_rdl(intNum * 4) == 0xF000F065) || //F000:F065 is default BIOS interrupt handler address (my_rdl(intNum * 4) == 0xF4F4F4F4)) //invalid { #if 0 // ignore interrupt... DEBUG_PRINTF_INTR ("%s(%x): invalid interrupt Vector (%08x) found, interrupt ignored...\n", __func__, intNum, my_rdl(intNum * 4)); DEBUG_PRINTF_INTR("AX=%04x BX=%04x CX=%04x DX=%04x\n", M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); //HALT_SYS(); #endif handleInt10(); int_handled = 1; } break; case 0x16: // Keyboard BIOS Interrupt handleInt16(); int_handled = 1; break; case 0x1a: // PCI BIOS Interrupt handleInt1a(); int_handled = 1; break; case PMM_INT_NUM: /* The self-defined PMM INT number, this is called by * the code in PMM struct, and it is handled by * pmm_handleInt() */ pmm_handleInt(); int_handled = 1; break; default: printf("Interrupt %#x (Vector: %x) not implemented\n", intNum, my_rdl(intNum * 4)); DEBUG_PRINTF_INTR("AX=%04x BX=%04x CX=%04x DX=%04x\n", M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); int_handled = 1; HALT_SYS(); break; } } // if we did not handle the interrupt, jump to the interrupt vector... if (!int_handled) { setupInt(intNum); } } // prepare and execute Interrupt 10 (VGA Interrupt) void runInt10(void) { // Initialize stack and data segment M.x86.R_SS = STACK_SEGMENT; M.x86.R_DS = DATA_SEGMENT; M.x86.R_SP = STACK_START_OFFSET; // push a HLT instruction and a pointer to it onto the stack // any return will pop the pointer and jump to the HLT, thus // exiting (more or less) cleanly push_word(0xf4f4); //F4=HLT //push_word(M.x86.R_SS); //push_word(M.x86.R_SP + 2); // setupInt will push the current CS and IP to the stack to return to it, // but we want to halt, so set CS:IP to the HLT instruction we just pushed // to the stack M.x86.R_CS = M.x86.R_SS; M.x86.R_IP = M.x86.R_SP; // + 4; CHECK_DBG(DEBUG_TRACE_X86EMU) { X86EMU_trace_on(); } CHECK_DBG(DEBUG_JMP) { M.x86.debug |= DEBUG_TRACEJMP_REGS_F; M.x86.debug |= DEBUG_TRACEJMP_REGS_F; M.x86.debug |= DEBUG_TRACECALL_F; M.x86.debug |= DEBUG_TRACECALL_REGS_F; } setupInt(0x10); DEBUG_PRINTF_INTR("%s(): starting execution of INT10...\n", __func__); X86EMU_exec(); DEBUG_PRINTF_INTR("%s(): execution finished\n", __func__); }
static void push_firq_registers(struct MC6809 *cpu) { NVMA_CYCLE; push_word(cpu, ®_S, REG_PC); push_byte(cpu, ®_S, REG_CC); }
/* main entry into YABEL biosemu, arguments are: * *biosmem = pointer to virtual memory * biosmem_size = size of the virtual memory * *dev = pointer to the device to be initialised * rom_addr = address of the OptionROM to be executed, if this is = 0, YABEL * will look for an ExpansionROM BAR and use the code from there. */ u32 biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_addr) { u8 *rom_image; int i = 0; #if CONFIG_X86EMU_DEBUG debug_flags = 0; #if defined(CONFIG_X86EMU_DEBUG_JMP) && CONFIG_X86EMU_DEBUG_JMP debug_flags |= DEBUG_JMP; #endif #if defined(CONFIG_X86EMU_DEBUG_TRACE) && CONFIG_X86EMU_DEBUG_TRACE debug_flags |= DEBUG_TRACE_X86EMU; #endif #if defined(CONFIG_X86EMU_DEBUG_PNP) && CONFIG_X86EMU_DEBUG_PNP debug_flags |= DEBUG_PNP; #endif #if defined(CONFIG_X86EMU_DEBUG_DISK) && CONFIG_X86EMU_DEBUG_DISK debug_flags |= DEBUG_DISK; #endif #if defined(CONFIG_X86EMU_DEBUG_PMM) && CONFIG_X86EMU_DEBUG_PMM debug_flags |= DEBUG_PMM; #endif #if defined(CONFIG_X86EMU_DEBUG_VBE) && CONFIG_X86EMU_DEBUG_VBE debug_flags |= DEBUG_VBE; #endif #if defined(CONFIG_X86EMU_DEBUG_INT10) && CONFIG_X86EMU_DEBUG_INT10 debug_flags |= DEBUG_PRINT_INT10; #endif #if defined(CONFIG_X86EMU_DEBUG_INTERRUPTS) && CONFIG_X86EMU_DEBUG_INTERRUPTS debug_flags |= DEBUG_INTR; #endif #if defined(CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS) && CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS debug_flags |= DEBUG_CHECK_VMEM_ACCESS; #endif #if defined(CONFIG_X86EMU_DEBUG_MEM) && CONFIG_X86EMU_DEBUG_MEM debug_flags |= DEBUG_MEM; #endif #if defined(CONFIG_X86EMU_DEBUG_IO) && CONFIG_X86EMU_DEBUG_IO debug_flags |= DEBUG_IO; #endif #endif if (biosmem_size < MIN_REQUIRED_VMEM_SIZE) { printf("Error: Not enough virtual memory: %x, required: %x!\n", biosmem_size, MIN_REQUIRED_VMEM_SIZE); return -1; } if (biosemu_dev_init(dev) != 0) { printf("Error initializing device!\n"); return -1; } if (biosemu_dev_check_exprom(rom_addr) != 0) { printf("Error: Device Expansion ROM invalid!\n"); return -1; } rom_image = (u8 *) bios_device.img_addr; DEBUG_PRINTF("executing rom_image from %p\n", rom_image); DEBUG_PRINTF("biosmem at %p\n", biosmem); DEBUG_PRINTF("Image Size: %d\n", bios_device.img_size); // in case we jump somewhere unexpected, or execution is finished, // fill the biosmem with hlt instructions (0xf4) // But we have to be careful: If biosmem is 0x00000000 we're running // in the lower 1MB and we must not wipe memory like that. if (biosmem) { DEBUG_PRINTF("Clearing biosmem\n"); memset(biosmem, 0xf4, biosmem_size); } X86EMU_setMemBase(biosmem, biosmem_size); DEBUG_PRINTF("membase set: %08x, size: %08x\n", (int) M.mem_base, (int) M.mem_size); // copy expansion ROM image to segment OPTION_ROM_CODE_SEGMENT // NOTE: this sometimes fails, some bytes are 0x00... so we compare // after copying and do some retries... u8 *mem_img = biosmem + (OPTION_ROM_CODE_SEGMENT << 4); u8 copy_count = 0; u8 cmp_result = 0; do { #if 0 set_ci(); memcpy(mem_img, rom_image, len); clr_ci(); #else // memcpy fails... try copy byte-by-byte with set/clr_ci u8 c; for (i = 0; i < bios_device.img_size; i++) { set_ci(); c = *(rom_image + i); if (c != *(rom_image + i)) { clr_ci(); printf("Copy failed at: %x/%x\n", i, bios_device.img_size); printf("rom_image(%x): %x, mem_img(%x): %x\n", i, *(rom_image + i), i, *(mem_img + i)); break; } clr_ci(); *(mem_img + i) = c; } #endif copy_count++; set_ci(); cmp_result = memcmp(mem_img, rom_image, bios_device.img_size); clr_ci(); } while ((copy_count < 5) && (cmp_result != 0)); if (cmp_result != 0) { printf ("\nCopying Expansion ROM Image to Memory failed after %d retries! (%x)\n", copy_count, cmp_result); dump(rom_image, 0x20); dump(mem_img, 0x20); return 0; } // setup default Interrupt Vectors // some expansion ROMs seem to check for these addresses.. // each handler is only an IRET (0xCF) instruction // ROM BIOS Int 10 Handler F000:F065 my_wrl(0x10 * 4, 0xf000f065); my_wrb(0x000ff065, 0xcf); // ROM BIOS Int 11 Handler F000:F84D my_wrl(0x11 * 4, 0xf000f84d); my_wrb(0x000ff84d, 0xcf); // ROM BIOS Int 12 Handler F000:F841 my_wrl(0x12 * 4, 0xf000f841); my_wrb(0x000ff841, 0xcf); // ROM BIOS Int 13 Handler F000:EC59 my_wrl(0x13 * 4, 0xf000ec59); my_wrb(0x000fec59, 0xcf); // ROM BIOS Int 14 Handler F000:E739 my_wrl(0x14 * 4, 0xf000e739); my_wrb(0x000fe739, 0xcf); // ROM BIOS Int 15 Handler F000:F859 my_wrl(0x15 * 4, 0xf000f859); my_wrb(0x000ff859, 0xcf); // ROM BIOS Int 16 Handler F000:E82E my_wrl(0x16 * 4, 0xf000e82e); my_wrb(0x000fe82e, 0xcf); // ROM BIOS Int 17 Handler F000:EFD2 my_wrl(0x17 * 4, 0xf000efd2); my_wrb(0x000fefd2, 0xcf); // ROM BIOS Int 1A Handler F000:FE6E my_wrl(0x1a * 4, 0xf000fe6e); my_wrb(0x000ffe6e, 0xcf); // setup BIOS Data Area (0000:04xx, or 0040:00xx) // we currently 0 this area, meaning "we dont have // any hardware" :-) no serial/parallel ports, floppys, ... memset(biosmem + 0x400, 0x0, 0x100); // at offset 13h in BDA is the memory size in kbytes my_wrw(0x413, biosmem_size / 1024); // at offset 0eh in BDA is the segment of the Extended BIOS Data Area // see setup further down my_wrw(0x40e, INITIAL_EBDA_SEGMENT); // TODO: setup BDA Video Data ( offset 49h-66h) // e.g. to store video mode, cursor position, ... // in int10 (done) handler and VBE Functions // TODO: setup BDA Fixed Disk Data // 74h: Fixed Disk Last Operation Status // 75h: Fixed Disk Number of Disk Drives // TODO: check BDA for further needed data... //setup Extended BIOS Data Area //we currently 0 this area memset(biosmem + (INITIAL_EBDA_SEGMENT << 4), 0, INITIAL_EBDA_SIZE); // at offset 0h in EBDA is the size of the EBDA in KB my_wrw((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024); //TODO: check for further needed EBDA data... // setup original ROM BIOS Area (F000:xxxx) const char *date = "06/11/99"; for (i = 0; date[i]; i++) my_wrb(0xffff5 + i, date[i]); // set up eisa ident string const char *ident = "PCI_ISA"; for (i = 0; ident[i]; i++) my_wrb(0xfffd9 + i, ident[i]); // write system model id for IBM-AT // according to "Ralf Browns Interrupt List" Int15 AH=C0 Table 515, // model FC is the original AT and also used in all DOSEMU Versions. my_wrb(0xFFFFE, 0xfc); //setup interrupt handler X86EMU_intrFuncs intrFuncs[256]; for (i = 0; i < 256; i++) intrFuncs[i] = handleInterrupt; X86EMU_setupIntrFuncs(intrFuncs); X86EMU_setupPioFuncs(&my_pio_funcs); X86EMU_setupMemFuncs(&my_mem_funcs); //setup PMM struct in BIOS_DATA_SEGMENT, offset 0x0 u8 pmm_length = pmm_setup(BIOS_DATA_SEGMENT, 0x0); if (pmm_length <= 0) { printf ("\nYABEL: Warning: PMM Area could not be setup. PMM not available (%x)\n", pmm_length); return 0; } else { CHECK_DBG(DEBUG_PMM) { /* test the PMM */ pmm_test(); /* and clean it again by calling pmm_setup... */ pmm_length = pmm_setup(BIOS_DATA_SEGMENT, 0x0); } } // setup the CPU M.x86.R_AH = bios_device.bus; M.x86.R_AL = bios_device.devfn; M.x86.R_DX = 0x80; M.x86.R_EIP = 3; M.x86.R_CS = OPTION_ROM_CODE_SEGMENT; // Initialize stack and data segment M.x86.R_SS = STACK_SEGMENT; M.x86.R_SP = STACK_START_OFFSET; M.x86.R_DS = DATA_SEGMENT; // push a HLT instruction and a pointer to it onto the stack // any return will pop the pointer and jump to the HLT, thus // exiting (more or less) cleanly push_word(0xf4f4); // F4=HLT push_word(M.x86.R_SS); push_word(M.x86.R_SP + 2); CHECK_DBG(DEBUG_TRACE_X86EMU) { X86EMU_trace_on(); #if 0 } else {
static void mc6809_run(struct MC6809 *cpu) { do { _Bool nmi_active = cpu->nmi && ((cpu->cycle - cpu->nmi_cycle) <= (UINT_MAX/2)); _Bool firq_active = cpu->firq && ((cpu->cycle - cpu->firq_cycle) <= (UINT_MAX/2)); _Bool irq_active = cpu->irq && ((cpu->cycle - cpu->irq_cycle) <= (UINT_MAX/2)); // Prevent overflow if (firq_active) cpu->firq_cycle = cpu->cycle; if (irq_active) cpu->irq_cycle = cpu->cycle; switch (cpu->state) { case mc6809_state_reset: REG_DP = 0; REG_CC |= (CC_F | CC_I); cpu->nmi = 0; cpu->nmi_armed = 0; cpu->state = mc6809_state_reset_check_halt; // fall through case mc6809_state_reset_check_halt: if (cpu->halt) { NVMA_CYCLE; continue; } REG_PC = fetch_byte(cpu, MC6809_INT_VEC_RESET) << 8; REG_PC |= fetch_byte(cpu, MC6809_INT_VEC_RESET + 1); NVMA_CYCLE; cpu->state = mc6809_state_label_a; continue; // done_instruction case for backwards-compatibility case mc6809_state_done_instruction: case mc6809_state_label_a: if (cpu->halt) { NVMA_CYCLE; continue; } cpu->state = mc6809_state_label_b; // fall through case mc6809_state_label_b: if (cpu->nmi_armed && nmi_active) { peek_byte(cpu, REG_PC); peek_byte(cpu, REG_PC); stack_irq_registers(cpu, 1); cpu->state = mc6809_state_dispatch_irq; continue; } if (!(REG_CC & CC_F) && firq_active) { peek_byte(cpu, REG_PC); peek_byte(cpu, REG_PC); stack_irq_registers(cpu, 0); cpu->state = mc6809_state_dispatch_irq; continue; } if (!(REG_CC & CC_I) && irq_active) { peek_byte(cpu, REG_PC); peek_byte(cpu, REG_PC); stack_irq_registers(cpu, 1); cpu->state = mc6809_state_dispatch_irq; continue; } cpu->state = mc6809_state_next_instruction; // Instruction fetch hook called here so that machine // can be stopped beforehand. DELEGATE_SAFE_CALL0(cpu->instruction_hook); continue; case mc6809_state_dispatch_irq: if (cpu->nmi_armed && nmi_active) { cpu->nmi = 0; REG_CC |= (CC_F | CC_I); take_interrupt(cpu, CC_F|CC_I, MC6809_INT_VEC_NMI); cpu->state = mc6809_state_label_a; continue; } if (!(REG_CC & CC_F) && firq_active) { REG_CC |= (CC_F | CC_I); take_interrupt(cpu, CC_F|CC_I, MC6809_INT_VEC_FIRQ); cpu->state = mc6809_state_label_a; continue; } if (!(REG_CC & CC_I) && irq_active) { REG_CC |= CC_I; take_interrupt(cpu, CC_I, MC6809_INT_VEC_IRQ); cpu->state = mc6809_state_label_a; continue; } cpu->state = mc6809_state_cwai_check_halt; continue; case mc6809_state_cwai_check_halt: NVMA_CYCLE; if (cpu->halt) { continue; } cpu->state = mc6809_state_dispatch_irq; continue; case mc6809_state_sync: if (nmi_active || firq_active || irq_active) { NVMA_CYCLE; NVMA_CYCLE; instruction_posthook(cpu); cpu->state = mc6809_state_label_b; continue; } NVMA_CYCLE; if (cpu->halt) cpu->state = mc6809_state_sync_check_halt; continue; case mc6809_state_sync_check_halt: NVMA_CYCLE; if (!cpu->halt) { cpu->state = mc6809_state_sync; } continue; case mc6809_state_next_instruction: { unsigned op; // Fetch op-code and process op = byte_immediate(cpu); switch (op) { // 0x00 - 0x0f direct mode ops // 0x40 - 0x4f inherent A register ops // 0x50 - 0x5f inherent B register ops // 0x60 - 0x6f indexed mode ops // 0x70 - 0x7f extended mode ops case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0f: case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47: case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4f: case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57: case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5f: case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67: case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6f: case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77: case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7f: { uint16_t ea; unsigned tmp1; switch ((op >> 4) & 0xf) { case 0x0: ea = ea_direct(cpu); tmp1 = fetch_byte(cpu, ea); break; case 0x4: ea = 0; tmp1 = RREG_A; break; case 0x5: ea = 0; tmp1 = RREG_B; break; case 0x6: ea = ea_indexed(cpu); tmp1 = fetch_byte(cpu, ea); break; case 0x7: ea = ea_extended(cpu); tmp1 = fetch_byte(cpu, ea); break; default: ea = tmp1 = 0; break; } switch (op & 0xf) { case 0x1: // NEG illegal case 0x0: tmp1 = op_neg(cpu, tmp1); break; // NEG, NEGA, NEGB case 0x2: tmp1 = op_negcom(cpu, tmp1); break; // NEGCOM illegal case 0x3: tmp1 = op_com(cpu, tmp1); break; // COM, COMA, COMB case 0x5: // LSR illegal case 0x4: tmp1 = op_lsr(cpu, tmp1); break; // LSR, LSRA, LSRB case 0x6: tmp1 = op_ror(cpu, tmp1); break; // ROR, RORA, RORB case 0x7: tmp1 = op_asr(cpu, tmp1); break; // ASR, ASRA, ASRB case 0x8: tmp1 = op_asl(cpu, tmp1); break; // ASL, ASLA, ASLB case 0x9: tmp1 = op_rol(cpu, tmp1); break; // ROL, ROLA, ROLB case 0xb: // DEC illegal case 0xa: tmp1 = op_dec(cpu, tmp1); break; // DEC, DECA, DECB case 0xc: tmp1 = op_inc(cpu, tmp1); break; // INC, INCA, INCB case 0xd: tmp1 = op_tst(cpu, tmp1); break; // TST, TSTA, TSTB case 0xf: tmp1 = op_clr(cpu, tmp1); break; // CLR, CLRA, CLRB default: break; } switch (op & 0xf) { case 0xd: // TST NVMA_CYCLE; NVMA_CYCLE; break; default: // the rest need storing switch ((op >> 4) & 0xf) { default: case 0x0: case 0x6: case 0x7: NVMA_CYCLE; store_byte(cpu, ea, tmp1); break; case 0x4: WREG_A = tmp1; peek_byte(cpu, REG_PC); break; case 0x5: WREG_B = tmp1; peek_byte(cpu, REG_PC); break; } } } break; // 0x0e JMP direct // 0x6e JMP indexed // 0x7e JMP extended case 0x0e: case 0x6e: case 0x7e: { unsigned ea; switch ((op >> 4) & 0xf) { case 0x0: ea = ea_direct(cpu); break; case 0x6: ea = ea_indexed(cpu); break; case 0x7: ea = ea_extended(cpu); break; default: ea = 0; break; } REG_PC = ea; } break; // 0x10 Page 2 case 0x10: cpu->state = mc6809_state_instruction_page_2; continue; // 0x11 Page 3 case 0x11: cpu->state = mc6809_state_instruction_page_3; continue; // 0x12 NOP inherent case 0x12: peek_byte(cpu, REG_PC); break; // 0x13 SYNC inherent case 0x13: peek_byte(cpu, REG_PC); cpu->state = mc6809_state_sync; continue; // 0x14, 0x15 HCF? (illegal) case 0x14: case 0x15: cpu->state = mc6809_state_hcf; goto done_instruction; // 0x16 LBRA relative case 0x16: { uint16_t ea; ea = long_relative(cpu); REG_PC += ea; NVMA_CYCLE; NVMA_CYCLE; } break; // 0x17 LBSR relative case 0x17: { uint16_t ea; ea = long_relative(cpu); ea += REG_PC; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; push_word(cpu, ®_S, REG_PC); REG_PC = ea; } break; // 0x18 Shift CC with mask inherent (illegal) case 0x18: REG_CC = (REG_CC << 1) & (CC_H | CC_Z); NVMA_CYCLE; peek_byte(cpu, REG_PC); break; // 0x19 DAA inherent case 0x19: { unsigned tmp = 0; if ((RREG_A&0x0f) >= 0x0a || REG_CC & CC_H) tmp |= 0x06; if (RREG_A >= 0x90 && (RREG_A&0x0f) >= 0x0a) tmp |= 0x60; if (RREG_A >= 0xa0 || REG_CC & CC_C) tmp |= 0x60; tmp += RREG_A; WREG_A = tmp; // CC.C NOT cleared, only set if appropriate CLR_NZV; SET_NZC8(tmp); peek_byte(cpu, REG_PC); } break; // 0x1a ORCC immediate case 0x1a: { unsigned data; data = byte_immediate(cpu); REG_CC |= data; peek_byte(cpu, REG_PC); } break; // 0x1b NOP inherent (illegal) case 0x1b: peek_byte(cpu, REG_PC); break; // 0x1c ANDCC immediate case 0x1c: { unsigned data; data = byte_immediate(cpu); REG_CC &= data; peek_byte(cpu, REG_PC); } break; // 0x1d SEX inherent case 0x1d: WREG_A = (RREG_B & 0x80) ? 0xff : 0; CLR_NZ; SET_NZ16(REG_D); peek_byte(cpu, REG_PC); break; // 0x1e EXG immediate case 0x1e: { unsigned postbyte; uint16_t tmp1, tmp2; postbyte = byte_immediate(cpu); switch (postbyte >> 4) { case 0x0: tmp1 = REG_D; break; case 0x1: tmp1 = REG_X; break; case 0x2: tmp1 = REG_Y; break; case 0x3: tmp1 = REG_U; break; case 0x4: tmp1 = REG_S; break; case 0x5: tmp1 = REG_PC; break; case 0x8: tmp1 = RREG_A | 0xff00; break; case 0x9: tmp1 = RREG_B | 0xff00; break; // TODO: verify this behaviour case 0xa: tmp1 = (REG_CC << 8) | REG_CC; break; case 0xb: tmp1 = (REG_DP << 8) | REG_DP; break; default: tmp1 = 0xffff; break; } switch (postbyte & 0xf) { case 0x0: tmp2 = REG_D; REG_D = tmp1; break; case 0x1: tmp2 = REG_X; REG_X = tmp1; break; case 0x2: tmp2 = REG_Y; REG_Y = tmp1; break; case 0x3: tmp2 = REG_U; REG_U = tmp1; break; case 0x4: tmp2 = REG_S; REG_S = tmp1; break; case 0x5: tmp2 = REG_PC; REG_PC = tmp1; break; case 0x8: tmp2 = RREG_A | 0xff00; WREG_A = tmp1; break; case 0x9: tmp2 = RREG_B | 0xff00; WREG_B = tmp1; break; // TODO: verify this behaviour case 0xa: tmp2 = (REG_CC << 8) | REG_CC; REG_CC = tmp1; break; case 0xb: tmp2 = (REG_DP << 8) | REG_DP; REG_DP = tmp1; break; default: tmp2 = 0xffff; break; } switch (postbyte >> 4) { case 0x0: REG_D = tmp2; break; case 0x1: REG_X = tmp2; break; case 0x2: REG_Y = tmp2; break; case 0x3: REG_U = tmp2; break; case 0x4: REG_S = tmp2; break; case 0x5: REG_PC = tmp2; break; case 0x8: WREG_A = tmp2; break; case 0x9: WREG_B = tmp2; break; case 0xa: REG_CC = tmp2; break; case 0xb: REG_DP = tmp2; break; default: break; } NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; } break; // 0x1f TFR immediate case 0x1f: { unsigned postbyte; uint16_t tmp1; postbyte = byte_immediate(cpu); switch (postbyte >> 4) { case 0x0: tmp1 = REG_D; break; case 0x1: tmp1 = REG_X; break; case 0x2: tmp1 = REG_Y; break; case 0x3: tmp1 = REG_U; break; case 0x4: tmp1 = REG_S; break; case 0x5: tmp1 = REG_PC; break; case 0x8: tmp1 = RREG_A | 0xff00; break; case 0x9: tmp1 = RREG_B | 0xff00; break; // TODO: verify this behaviour case 0xa: tmp1 = (REG_CC << 8) | REG_CC; break; case 0xb: tmp1 = (REG_DP << 8) | REG_DP; break; default: tmp1 = 0xffff; break; } switch (postbyte & 0xf) { case 0x0: REG_D = tmp1; break; case 0x1: REG_X = tmp1; break; case 0x2: REG_Y = tmp1; break; case 0x3: REG_U = tmp1; break; case 0x4: REG_S = tmp1; break; case 0x5: REG_PC = tmp1; break; case 0x8: WREG_A = tmp1; break; case 0x9: WREG_B = tmp1; break; case 0xa: REG_CC = tmp1; break; case 0xb: REG_DP = tmp1; break; default: break; } NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; } break; // 0x20 - 0x2f short branches case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: { unsigned tmp = sex8(byte_immediate(cpu)); NVMA_CYCLE; if (branch_condition(cpu, op)) REG_PC += tmp; } break; // 0x30 LEAX indexed case 0x30: REG_X = ea_indexed(cpu); CLR_Z; SET_Z(REG_X); NVMA_CYCLE; break; // 0x31 LEAY indexed case 0x31: REG_Y = ea_indexed(cpu); CLR_Z; SET_Z(REG_Y); NVMA_CYCLE; break; // 0x32 LEAS indexed case 0x32: REG_S = ea_indexed(cpu); NVMA_CYCLE; cpu->nmi_armed = 1; // XXX: Really? break; // 0x33 LEAU indexed case 0x33: REG_U = ea_indexed(cpu); NVMA_CYCLE; break; // 0x34 PSHS immediate case 0x34: psh(cpu, ®_S, REG_U); break; // 0x35 PULS immediate case 0x35: pul(cpu, ®_S, ®_U); break; // 0x36 PSHU immediate case 0x36: psh(cpu, ®_U, REG_S); break; // 0x37 PULU immediate case 0x37: pul(cpu, ®_U, ®_S); break; // 0x38 ANDCC immediate (illegal) case 0x38: { unsigned data; data = byte_immediate(cpu); REG_CC &= data; peek_byte(cpu, REG_PC); /* Differs from legal 0x1c version by * taking one more cycle: */ NVMA_CYCLE; } break; // 0x39 RTS inherent case 0x39: peek_byte(cpu, REG_PC); REG_PC = pull_word(cpu, ®_S); NVMA_CYCLE; break; // 0x3a ABX inherent case 0x3a: REG_X += RREG_B; peek_byte(cpu, REG_PC); NVMA_CYCLE; break; // 0x3b RTI inherent case 0x3b: peek_byte(cpu, REG_PC); REG_CC = pull_byte(cpu, ®_S); if (REG_CC & CC_E) { WREG_A = pull_byte(cpu, ®_S); WREG_B = pull_byte(cpu, ®_S); REG_DP = pull_byte(cpu, ®_S); REG_X = pull_word(cpu, ®_S); REG_Y = pull_word(cpu, ®_S); REG_U = pull_word(cpu, ®_S); REG_PC = pull_word(cpu, ®_S); } else { REG_PC = pull_word(cpu, ®_S); } cpu->nmi_armed = 1; peek_byte(cpu, REG_S); break; // 0x3c CWAI immediate case 0x3c: { unsigned data; data = byte_immediate(cpu); REG_CC &= data; peek_byte(cpu, REG_PC); NVMA_CYCLE; stack_irq_registers(cpu, 1); NVMA_CYCLE; cpu->state = mc6809_state_dispatch_irq; goto done_instruction; } break; // 0x3d MUL inherent case 0x3d: { unsigned tmp = RREG_A * RREG_B; REG_D = tmp; CLR_ZC; SET_Z(tmp); if (tmp & 0x80) REG_CC |= CC_C; peek_byte(cpu, REG_PC); NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; } break; // 0x3e RESET (illegal) case 0x3e: peek_byte(cpu, REG_PC); push_irq_registers(cpu); instruction_posthook(cpu); take_interrupt(cpu, CC_F|CC_I, MC6809_INT_VEC_RESET); cpu->state = mc6809_state_label_a; continue; // 0x3f SWI inherent case 0x3f: peek_byte(cpu, REG_PC); stack_irq_registers(cpu, 1); instruction_posthook(cpu); take_interrupt(cpu, CC_F|CC_I, MC6809_INT_VEC_SWI); cpu->state = mc6809_state_label_a; continue; // 0x80 - 0xbf A register arithmetic ops // 0xc0 - 0xff B register arithmetic ops case 0x80: case 0x81: case 0x82: case 0x84: case 0x85: case 0x86: case 0x87: case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x90: case 0x91: case 0x92: case 0x94: case 0x95: case 0x96: case 0x98: case 0x99: case 0x9a: case 0x9b: case 0xa0: case 0xa1: case 0xa2: case 0xa4: case 0xa5: case 0xa6: case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xb0: case 0xb1: case 0xb2: case 0xb4: case 0xb5: case 0xb6: case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xc0: case 0xc1: case 0xc2: case 0xc4: case 0xc5: case 0xc6: case 0xc7: case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xd0: case 0xd1: case 0xd2: case 0xd4: case 0xd5: case 0xd6: case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xe0: case 0xe1: case 0xe2: case 0xe4: case 0xe5: case 0xe6: case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xf0: case 0xf1: case 0xf2: case 0xf4: case 0xf5: case 0xf6: case 0xf8: case 0xf9: case 0xfa: case 0xfb: { unsigned tmp1, tmp2; tmp1 = !(op & 0x40) ? RREG_A : RREG_B; switch ((op >> 4) & 3) { case 0: tmp2 = byte_immediate(cpu); break; case 1: tmp2 = byte_direct(cpu); break; case 2: tmp2 = byte_indexed(cpu); break; case 3: tmp2 = byte_extended(cpu); break; default: tmp2 = 0; break; } switch (op & 0xf) { case 0x0: tmp1 = op_sub(cpu, tmp1, tmp2); break; // SUBA, SUBB case 0x1: (void)op_sub(cpu, tmp1, tmp2); break; // CMPA, CMPB case 0x2: tmp1 = op_sbc(cpu, tmp1, tmp2); break; // SBCA, SBCB case 0x4: tmp1 = op_and(cpu, tmp1, tmp2); break; // ANDA, ANDB case 0x5: (void)op_and(cpu, tmp1, tmp2); break; // BITA, BITB case 0x6: tmp1 = op_ld(cpu, 0, tmp2); break; // LDA, LDB case 0x7: tmp1 = op_discard(cpu, tmp1, tmp2); break; // illegal case 0x8: tmp1 = op_eor(cpu, tmp1, tmp2); break; // EORA, EORB case 0x9: tmp1 = op_adc(cpu, tmp1, tmp2); break; // ADCA, ADCB case 0xa: tmp1 = op_or(cpu, tmp1, tmp2); break; // ORA, ORB case 0xb: tmp1 = op_add(cpu, tmp1, tmp2); break; // ADDA, ADDB default: break; } if (!(op & 0x40)) { WREG_A = tmp1; } else { WREG_B = tmp1; } } break; // 0x83, 0x93, 0xa3, 0xb3 SUBD // 0x8c, 0x9c, 0xac, 0xbc CMPX // 0xc3, 0xd3, 0xe3, 0xf3 ADDD case 0x83: case 0x93: case 0xa3: case 0xb3: case 0x8c: case 0x9c: case 0xac: case 0xbc: case 0xc3: case 0xd3: case 0xe3: case 0xf3: { unsigned tmp1, tmp2; tmp1 = !(op & 0x08) ? REG_D : REG_X; switch ((op >> 4) & 3) { case 0: tmp2 = word_immediate(cpu); break; case 1: tmp2 = word_direct(cpu); break; case 2: tmp2 = word_indexed(cpu); break; case 3: tmp2 = word_extended(cpu); break; default: tmp2 = 0; break; } switch (op & 0x4f) { case 0x03: tmp1 = op_sub16(cpu, tmp1, tmp2); break; // SUBD case 0x0c: (void)op_sub16(cpu, tmp1, tmp2); break; // CMPX case 0x43: tmp1 = op_add16(cpu, tmp1, tmp2); break; // ADDD default: break; } NVMA_CYCLE; if (!(op & 0x08)) { REG_D = tmp1; } } break; // 0x8d BSR // 0x9d, 0xad, 0xbd JSR case 0x8d: case 0x9d: case 0xad: case 0xbd: { unsigned ea; switch ((op >> 4) & 3) { case 0: ea = short_relative(cpu); ea += REG_PC; NVMA_CYCLE; NVMA_CYCLE; NVMA_CYCLE; break; case 1: ea = ea_direct(cpu); peek_byte(cpu, ea); NVMA_CYCLE; break; case 2: ea = ea_indexed(cpu); peek_byte(cpu, ea); NVMA_CYCLE; break; case 3: ea = ea_extended(cpu); peek_byte(cpu, ea); NVMA_CYCLE; break; default: ea = 0; break; } push_word(cpu, ®_S, REG_PC); REG_PC = ea; } break; // 0x8e, 0x9e, 0xae, 0xbe LDX // 0xcc, 0xdc, 0xec, 0xfc LDD // 0xce, 0xde, 0xee, 0xfe LDU case 0x8e: case 0x9e: case 0xae: case 0xbe: case 0xcc: case 0xdc: case 0xec: case 0xfc: case 0xce: case 0xde: case 0xee: case 0xfe: { unsigned tmp1, tmp2; switch ((op >> 4) & 3) { case 0: tmp2 = word_immediate(cpu); break; case 1: tmp2 = word_direct(cpu); break; case 2: tmp2 = word_indexed(cpu); break; case 3: tmp2 = word_extended(cpu); break; default: tmp2 = 0; break; } tmp1 = op_ld16(cpu, 0, tmp2); switch (op & 0x42) { case 0x02: REG_X = tmp1; break; case 0x40: REG_D = tmp1; break; case 0x42: REG_U = tmp1; break; default: break; } } break; // 0x97, 0xa7, 0xb7 STA // 0xd7, 0xe7, 0xf7 STB case 0x97: case 0xa7: case 0xb7: case 0xd7: case 0xe7: case 0xf7: { uint16_t ea; uint8_t tmp1; tmp1 = !(op & 0x40) ? RREG_A : RREG_B; switch ((op >> 4) & 3) { case 1: ea = ea_direct(cpu); break; case 2: ea = ea_indexed(cpu); break; case 3: ea = ea_extended(cpu); break; default: ea = 0; break; } store_byte(cpu, ea, tmp1); CLR_NZV; SET_NZ8(tmp1); } break; // 0x9f, 0xaf, 0xbf STX // 0xdd, 0xed, 0xfd STD // 0xdf, 0xef, 0xff STU case 0x9f: case 0xaf: case 0xbf: case 0xdd: case 0xed: case 0xfd: case 0xdf: case 0xef: case 0xff: { uint16_t ea, tmp1; switch (op & 0x42) { case 0x02: tmp1 = REG_X; break; case 0x40: tmp1 = REG_D; break; case 0x42: tmp1 = REG_U; break; default: tmp1 = 0; break; } switch ((op >> 4) & 3) { case 1: ea = ea_direct(cpu); break; case 2: ea = ea_indexed(cpu); break; case 3: ea = ea_extended(cpu); break; default: ea = 0; break; } CLR_NZV; SET_NZ16(tmp1); store_byte(cpu, ea, tmp1 >> 8); store_byte(cpu, ea+1, tmp1); } break; // 0x8f STX immediate (illegal) // 0xcf STU immediate (illegal) // Illegal instruction only part working case 0x8f: case 0xcf: { unsigned tmp1; tmp1 = !(op & 0x40) ? REG_X : REG_U; (void)fetch_byte(cpu, REG_PC); REG_PC++; store_byte(cpu, REG_PC, tmp1); REG_PC++; CLR_NZV; REG_CC |= CC_N; } break; // 0xcd HCF? (illegal) case 0xcd: cpu->state = mc6809_state_hcf; goto done_instruction; // Illegal instruction default: NVMA_CYCLE; break; } cpu->state = mc6809_state_label_a; goto done_instruction; } case mc6809_state_instruction_page_2: { unsigned op; op = byte_immediate(cpu); switch (op) { // 0x10, 0x11 Page 2 case 0x10: case 0x11: cpu->state = mc6809_state_instruction_page_2; continue; // 0x1020 - 0x102f long branches case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: { unsigned tmp = word_immediate(cpu); if (branch_condition(cpu, op)) { REG_PC += tmp; NVMA_CYCLE; } NVMA_CYCLE; } break; // 0x103f SWI2 inherent case 0x3f: peek_byte(cpu, REG_PC); stack_irq_registers(cpu, 1); instruction_posthook(cpu); take_interrupt(cpu, 0, MC6809_INT_VEC_SWI2); cpu->state = mc6809_state_label_a; continue; // 0x1083, 0x1093, 0x10a3, 0x10b3 CMPD // 0x108c, 0x109c, 0x10ac, 0x10bc CMPY case 0x83: case 0x93: case 0xa3: case 0xb3: case 0x8c: case 0x9c: case 0xac: case 0xbc: { unsigned tmp1, tmp2; tmp1 = !(op & 0x08) ? REG_D : REG_Y; switch ((op >> 4) & 3) { case 0: tmp2 = word_immediate(cpu); break; case 1: tmp2 = word_direct(cpu); break; case 2: tmp2 = word_indexed(cpu); break; case 3: tmp2 = word_extended(cpu); break; default: tmp2 = 0; break; } (void)op_sub16(cpu, tmp1, tmp2); NVMA_CYCLE; } break; // 0x108e, 0x109e, 0x10ae, 0x10be LDY // 0x10ce, 0x10de, 0x10ee, 0x10fe LDS case 0x8e: case 0x9e: case 0xae: case 0xbe: case 0xce: case 0xde: case 0xee: case 0xfe: { unsigned tmp1, tmp2; switch ((op >> 4) & 3) { case 0: tmp2 = word_immediate(cpu); break; case 1: tmp2 = word_direct(cpu); break; case 2: tmp2 = word_indexed(cpu); break; case 3: tmp2 = word_extended(cpu); break; default: tmp2 = 0; break; } tmp1 = op_ld16(cpu, 0, tmp2); if (!(op & 0x40)) { REG_Y = tmp1; } else { REG_S = tmp1; cpu->nmi_armed = 1; } } break; // 0x109f, 0x10af, 0x10bf STY // 0x10df, 0x10ef, 0x10ff STS case 0x9f: case 0xaf: case 0xbf: case 0xdf: case 0xef: case 0xff: { unsigned ea, tmp1; tmp1 = !(op & 0x40) ? REG_Y : REG_S; switch ((op >> 4) & 3) { case 1: ea = ea_direct(cpu); break; case 2: ea = ea_indexed(cpu); break; case 3: ea = ea_extended(cpu); break; default: ea = 0; break; } CLR_NZV; SET_NZ16(tmp1); store_byte(cpu, ea, tmp1 >> 8); store_byte(cpu, ea+1, tmp1); } break; // Illegal instruction default: NVMA_CYCLE; break; } cpu->state = mc6809_state_label_a; goto done_instruction; } case mc6809_state_instruction_page_3: { unsigned op; op = byte_immediate(cpu); switch (op) { // 0x10, 0x11 Page 3 case 0x10: case 0x11: cpu->state = mc6809_state_instruction_page_3; continue; // 0x113F SWI3 inherent case 0x3f: peek_byte(cpu, REG_PC); stack_irq_registers(cpu, 1); instruction_posthook(cpu); take_interrupt(cpu, 0, MC6809_INT_VEC_SWI3); cpu->state = mc6809_state_label_a; continue; // 0x1183, 0x1193, 0x11a3, 0x11b3 CMPU // 0x118c, 0x119c, 0x11ac, 0x11bc CMPS case 0x83: case 0x93: case 0xa3: case 0xb3: case 0x8c: case 0x9c: case 0xac: case 0xbc: { unsigned tmp1, tmp2; tmp1 = !(op & 0x08) ? REG_U : REG_S; switch ((op >> 4) & 3) { case 0: tmp2 = word_immediate(cpu); break; case 1: tmp2 = word_direct(cpu); break; case 2: tmp2 = word_indexed(cpu); break; case 3: tmp2 = word_extended(cpu); break; default: tmp2 = 0; break; } (void)op_sub16(cpu, tmp1, tmp2); NVMA_CYCLE; } break; // Illegal instruction default: NVMA_CYCLE; break; } cpu->state = mc6809_state_label_a; goto done_instruction; } // Certain illegal instructions cause the CPU to lock up: case mc6809_state_hcf: NVMA_CYCLE; continue; } done_instruction: instruction_posthook(cpu); continue; } while (cpu->running); }