static pwmOutputPort_t *pwmOutConfig(const timerHardware_t *timerHardware, uint8_t mhz, uint16_t period, uint16_t value) { pwmOutputPort_t *p = &pwmOutputPorts[allocatedOutputPortCount++]; configTimeBase(timerHardware->tim, period, mhz); pwmGPIOConfig(timerHardware->gpio, timerHardware->pin, Mode_AF_PP); pwmOCConfig(timerHardware->tim, timerHardware->channel, value); if (timerHardware->outputEnable) TIM_CtrlPWMOutputs(timerHardware->tim, ENABLE); TIM_Cmd(timerHardware->tim, ENABLE); switch (timerHardware->channel) { case TIM_Channel_1: p->ccr = &timerHardware->tim->CCR1; break; case TIM_Channel_2: p->ccr = &timerHardware->tim->CCR2; break; case TIM_Channel_3: p->ccr = &timerHardware->tim->CCR3; break; case TIM_Channel_4: p->ccr = &timerHardware->tim->CCR4; break; } p->period = period; p->tim = timerHardware->tim; return p; }
static pwmPortData_t *pwmOutConfig(uint8_t port, uint16_t period, uint16_t value) { pwmPortData_t *p = &pwmPorts[port]; pwmTimeBase(timerHardware[port].tim, period); pwmGPIOConfig(timerHardware[port].gpio, timerHardware[port].pin, 0); pwmOCConfig(timerHardware[port].tim, timerHardware[port].channel, value); // Needed only on TIM1 if (timerHardware[port].outputEnable) TIM_CtrlPWMOutputs(timerHardware[port].tim, ENABLE); TIM_Cmd(timerHardware[port].tim, ENABLE); switch (timerHardware[port].channel) { case TIM_Channel_1: p->ccr = &timerHardware[port].tim->CCR1; break; case TIM_Channel_2: p->ccr = &timerHardware[port].tim->CCR2; break; case TIM_Channel_3: p->ccr = &timerHardware[port].tim->CCR3; break; case TIM_Channel_4: p->ccr = &timerHardware[port].tim->CCR4; break; } return p; }
static void pwmOutConfig(pwmOutputPort_t *port, const timerHardware_t *timerHardware, uint8_t mhz, uint16_t period, uint16_t value) { configTimeBase(timerHardware->tim, period, mhz); pwmOCConfig(timerHardware->tim, timerHardware->channel, value, timerHardware->output); TIM_CtrlPWMOutputs(timerHardware->tim, ENABLE); TIM_Cmd(timerHardware->tim, ENABLE); port->ccr = timerChCCR(timerHardware); port->period = period; port->tim = timerHardware->tim; *port->ccr = 0; }
static pwmOutputPort_t *pwmOutConfig(const timerHardware_t *timerHardware, uint8_t mhz, uint16_t period, uint16_t value, bool enableOutput) { pwmOutputPort_t *p = &pwmOutputPorts[allocatedOutputPortCount++]; configTimeBase(timerHardware->tim, period, mhz); const IO_t io = IOGetByTag(timerHardware->tag); IOInit(io, OWNER_MOTOR, RESOURCE_OUTPUT, allocatedOutputPortCount); if (enableOutput) { // If PWM outputs are enabled - configure as AF_PP - map to timer // AF itself was configured by timerInit(); IOConfigGPIO(io, IOCFG_AF_PP); } else { // If PWM outputs are disabled - configure as GPIO and drive low IOConfigGPIO(io, IOCFG_OUT_OD); IOLo(io); } pwmOCConfig(timerHardware->tim, timerHardware->channel, value, timerHardware->output & TIMER_OUTPUT_INVERTED); if (timerHardware->output & TIMER_OUTPUT_ENABLED) { TIM_CtrlPWMOutputs(timerHardware->tim, ENABLE); } TIM_Cmd(timerHardware->tim, ENABLE); switch (timerHardware->channel) { case TIM_Channel_1: p->ccr = &timerHardware->tim->CCR1; break; case TIM_Channel_2: p->ccr = &timerHardware->tim->CCR2; break; case TIM_Channel_3: p->ccr = &timerHardware->tim->CCR3; break; case TIM_Channel_4: p->ccr = &timerHardware->tim->CCR4; break; } p->period = period; p->tim = timerHardware->tim; *p->ccr = 0; return p; }
static pwmOutputPort_t *pwmOutConfig(const timerHardware_t *timerHardware, uint8_t mhz, uint16_t period, uint16_t value) { pwmOutputPort_t *p = &pwmOutputPorts[allocatedOutputPortCount++]; configTimeBase(timerHardware->tim, period, mhz); IO_t io = IOGetByTag(timerHardware->tag); IOInit(io, OWNER_MOTOR, RESOURCE_OUTPUT, allocatedOutputPortCount); IOConfigGPIO(io, IOCFG_AF_PP); pwmOCConfig(timerHardware->tim, timerHardware->channel, value, timerHardware->output & TIMER_OUTPUT_INVERTED); if (timerHardware->output & TIMER_OUTPUT_ENABLED) { TIM_CtrlPWMOutputs(timerHardware->tim, ENABLE); } TIM_Cmd(timerHardware->tim, ENABLE); switch (timerHardware->channel) { case TIM_Channel_1: p->ccr = &timerHardware->tim->CCR1; break; case TIM_Channel_2: p->ccr = &timerHardware->tim->CCR2; break; case TIM_Channel_3: p->ccr = &timerHardware->tim->CCR3; break; case TIM_Channel_4: p->ccr = &timerHardware->tim->CCR4; break; } p->period = period; p->tim = timerHardware->tim; *p->ccr = 0; return p; }