/* ------------------------------------------------------------------------*//** * @FUNCTION dsp44xx_config_show * @BRIEF analyze DSP power configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in] stream: output file stream * @DESCRIPTION analyze DSP power configuration *//*------------------------------------------------------------------------ */ int dsp44xx_config_show(FILE *stream) { unsigned int pm_pwstctrl; unsigned int pm_pwstst; unsigned int cm_clkstctrl; unsigned int rm_context; unsigned int cm_clkctrl; int ret; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) dsp44xx_regtable_init(); if (mem_read(OMAP4430_CM_DSP_DSP_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_DSP_DSP_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; /* Power Domain Configuration */ if (mem_read(OMAP4430_PM_DSP_PWRSTCTRL, &pm_pwstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_DSP_PWRSTST, &pm_pwstst) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = pwrdm44xx_config_show(stream, "DSP", OMAP4430_PM_DSP_PWRSTCTRL, pm_pwstctrl, OMAP4430_PM_DSP_PWRSTST, pm_pwstst); if (ret != 0) return ret; /* Clock Domain Configuration */ if (mem_read(OMAP4430_CM_DSP_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "DSP", OMAP4430_CM_DSP_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* Module Power Configuration */ ret = mod44xx_config_show(stream, "DSP", OMAP4430_CM_DSP_DSP_CLKCTRL, cm_clkctrl, OMAP4430_RM_DSP_DSP_CONTEXT, rm_context); if (ret != 0) return ret; return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION emu44xx_config_show * @BRIEF analyze power configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in] stream: output file stream * @DESCRIPTION analyze power configuration *//*------------------------------------------------------------------------ */ int emu44xx_config_show(FILE *stream) { unsigned int pm_pwstctrl; unsigned int pm_pwstst; unsigned int cm_clkstctrl; unsigned int rm_context; unsigned int cm_clkctrl; int ret; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) emu44xx_regtable_init(); if (mem_read(OMAP4430_PM_EMU_PWRSTCTRL, &pm_pwstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_EMU_PWRSTST, &pm_pwstst) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_EMU_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = pwrdm44xx_config_show(stream, "EMU", OMAP4430_PM_EMU_PWRSTCTRL, pm_pwstctrl, OMAP4430_PM_EMU_PWRSTST, pm_pwstst); if (ret != 0) return ret; ret = clkdm44xx_config_show(stream, "EMU", OMAP4430_CM_EMU_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_EMU_DEBUGSS_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "DEBUGSS", OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, cm_clkctrl, OMAP4430_RM_EMU_DEBUGSS_CONTEXT, rm_context); return ret; }
/* ------------------------------------------------------------------------*//** * @FUNCTION core44xx_config_show * @BRIEF analyze CORE power configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in,out] stream: output file stream * @DESCRIPTION analyze CORE power configuration *//*------------------------------------------------------------------------ */ int core44xx_config_show(FILE *stream) { unsigned int pm_pwstctrl; unsigned int pm_pwstst; unsigned int cm_clkstctrl; unsigned int cm_clkctrl; unsigned int rm_context; int ret = 0; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) core44xx_regtable_init(); /* CORE Domain Power Configuration */ if (mem_read(OMAP4430_PM_CORE_PWRSTCTRL, &pm_pwstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_CORE_PWRSTST, &pm_pwstst) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = pwrdm44xx_config_show(stream, "CORE", OMAP4430_PM_CORE_PWRSTCTRL, pm_pwstctrl, OMAP4430_PM_CORE_PWRSTST, pm_pwstst); if (ret != 0) return ret; /* L3_1 Clock Domain Configuration */ if (mem_read(OMAP4430_CM_L3_1_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "L3_1", OMAP4430_CM_L3_1_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* L3_1 Module Power Configuration */ if (mem_read(OMAP4430_CM_L3_1_L3_1_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L3_1_L3_1_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "L3_1", OMAP4430_CM_L3_1_L3_1_CLKCTRL, cm_clkctrl, OMAP4430_RM_L3_1_L3_1_CONTEXT, rm_context); if (ret != 0) return ret; /* L3_2 Clock Domain Configuration */ if (mem_read(OMAP4430_CM_L3_2_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "L3_2", OMAP4430_CM_L3_2_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* L3_2 Modules Power Configuration */ if (mem_read(OMAP4430_CM_L3_2_L3_2_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L3_2_L3_2_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "L3_2", OMAP4430_CM_L3_2_L3_2_CLKCTRL, cm_clkctrl, OMAP4430_RM_L3_2_L3_2_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L3_2_GPMC_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L3_2_GPMC_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPMC", OMAP4430_CM_L3_2_GPMC_CLKCTRL, cm_clkctrl, OMAP4430_RM_L3_2_GPMC_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "OCMC_RAM", OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL, cm_clkctrl, OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT, rm_context); if (ret != 0) return ret; /* MPU_M3 Clock Domain Configuration */ if (mem_read(OMAP4430_CM_MPU_M3_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "MPU_M3", OMAP4430_CM_MPU_M3_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* MPU_M3 Module Power Configuration */ if (mem_read(OMAP4430_CM_MPU_M3_MPU_M3_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_MPU_M3_MPU_M3_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MPU_M3", OMAP4430_CM_MPU_M3_MPU_M3_CLKCTRL, cm_clkctrl, OMAP4430_RM_MPU_M3_MPU_M3_CONTEXT, rm_context); if (ret != 0) return ret; /* SDMA Clock Domain Configuration */ if (mem_read(OMAP4430_CM_SDMA_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "SDMA", OMAP4430_CM_SDMA_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* SDMA Module Power Configuration */ if (mem_read(OMAP4430_CM_SDMA_SDMA_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_SDMA_SDMA_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "SDMA", OMAP4430_CM_SDMA_SDMA_CLKCTRL, cm_clkctrl, OMAP4430_RM_SDMA_SDMA_CONTEXT, rm_context); if (ret != 0) return ret; /* MEMIF Clock Domain Configuration */ if (mem_read(OMAP4430_CM_MEMIF_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "MEMIF", OMAP4430_CM_MEMIF_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* MEMIF Modules Power Configuration */ if (mem_read(OMAP4430_CM_MEMIF_DMM_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_MEMIF_DMM_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "DMM", OMAP4430_CM_MEMIF_DMM_CLKCTRL, cm_clkctrl, OMAP4430_RM_MEMIF_DMM_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "EMIF_FW", OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL, cm_clkctrl, OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_MEMIF_EMIF_1_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "EMIF_1", OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, cm_clkctrl, OMAP4430_RM_MEMIF_EMIF_1_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_MEMIF_EMIF_2_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "EMIF_2", OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, cm_clkctrl, OMAP4430_RM_MEMIF_EMIF_2_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_MEMIF_DLL_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_MEMIF_DLL_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "DLL", OMAP4430_CM_MEMIF_DLL_CLKCTRL, cm_clkctrl, OMAP4430_RM_MEMIF_DLL_CONTEXT, rm_context); if (ret != 0) return ret; /* C2C Clock Domain Configuration */ if (mem_read(OMAP4430_CM_C2C_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "C2C", OMAP4430_CM_C2C_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* C2C Modules Power Configuration */ if (mem_read(OMAP4430_CM_C2C_C2C_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_C2C_C2C_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "C2C", OMAP4430_CM_C2C_C2C_CLKCTRL, cm_clkctrl, OMAP4430_RM_C2C_C2C_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_C2C_MODEM_ICR_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_C2C_MODEM_ICR_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MODEM_ICR", OMAP4430_CM_C2C_MODEM_ICR_CLKCTRL, cm_clkctrl, OMAP4430_RM_C2C_MODEM_ICR_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_C2C_C2C_FW_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_C2C_C2C_FW_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "C2C_FW", OMAP4430_CM_C2C_C2C_FW_CLKCTRL, cm_clkctrl, OMAP4430_RM_C2C_C2C_FW_CONTEXT, rm_context); if (ret != 0) return ret; /* L4CFG Clock Domain Configuration */ if (mem_read(OMAP4430_CM_L4CFG_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "L4CFG", OMAP4430_CM_L4CFG_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* L4CFG Modules Power Configuration */ if (mem_read(OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4CFG_L4_CFG_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "L4_CFG", OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4CFG_L4_CFG_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4CFG_HW_SEM_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "HW_SEM", OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4CFG_HW_SEM_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4CFG_MAILBOX_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MAILBOX", OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4CFG_MAILBOX_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "SAR_ROM", OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT, rm_context); if (ret != 0) return ret; /* L3INSTR Clock Domain Configuration */ if (mem_read(OMAP4430_CM_L3INSTR_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "L3INSTR", OMAP4430_CM_L3INSTR_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* L3INSTR Modules Power Configuration */ if (mem_read(OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L3INSTR_L3_3_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "L3_3", OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, cm_clkctrl, OMAP4430_RM_L3INSTR_L3_3_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "L3_INSTR", OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, cm_clkctrl, OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "OCP_WP1", OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, cm_clkctrl, OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT, rm_context); if (ret != 0) return ret; return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mpu44xx_config_show * @BRIEF analyze MPU power configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in] stream: output file stream * @DESCRIPTION analyze MPU power configuration *//*------------------------------------------------------------------------ */ int mpu44xx_config_show(FILE *stream) { unsigned int pm_pda_cpu0_pwrstctrl; unsigned int pm_pda_cpu0_pwrstst; unsigned int rm_pda_cpu0_context; unsigned int cm_pda_cpu0_clkctrl; unsigned int cm_pda_cpu0_clkstctrl; unsigned int pm_pda_cpu1_pwrstctrl; unsigned int pm_pda_cpu1_pwrstst; unsigned int rm_pda_cpu1_context; unsigned int cm_pda_cpu1_clkctrl; unsigned int cm_pda_cpu1_clkstctrl; unsigned int scu_cpu_power_status; char s0[32], s1[32]; unsigned int cm_clkmode_dpll_mpu; unsigned int cm_idlest_dpll_mpu; unsigned int cm_autoidle_dpll_mpu; omap4_dpll_params dpll_mpu_params; unsigned int pm_pwstctrl; unsigned int pm_pwstst; unsigned int cm_clkstctrl; unsigned int rm_context; unsigned int cm_clkctrl; int ret; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) mpu44xx_regtable_init(); if (mem_read(OMAP4430_PM_PDA_CPU0_PWRSTCTRL, &pm_pda_cpu0_pwrstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU0_PWRSTST, &pm_pda_cpu0_pwrstst) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT, &rm_pda_cpu0_context) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL, &cm_pda_cpu0_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU0_CLKSTCTRL, &cm_pda_cpu0_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU1_PWRSTCTRL, &pm_pda_cpu1_pwrstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU1_PWRSTST, &pm_pda_cpu1_pwrstst) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT, &rm_pda_cpu1_context) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL, &cm_pda_cpu1_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU1_CLKSTCTRL, &cm_pda_cpu1_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_SCU_CPU_POWER_STATUS, &scu_cpu_power_status) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_CLKMODE_DPLL_MPU, &cm_clkmode_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_IDLEST_DPLL_MPU, &cm_idlest_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_AUTOIDLE_DPLL_MPU, &cm_autoidle_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = dpll44xx_dpll_params_get(DPLL44XX_MPU, &dpll_mpu_params, 0); if (ret < 0) return ret; /* MPU LPRM config */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "MPU LPRM Configuration", "CPU0", "CPU1"); fprintf(stream, "|--------------------------------|-----------|-------" "----|\n"); pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 0, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 0, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current Power State", s0, s1); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current Logic State", ((extract_bit(pm_pda_cpu0_pwrstst, 2) == 1) ? "ON" : "OFF"), ((extract_bit(pm_pda_cpu1_pwrstst, 2) == 1) ? "ON" : "OFF")); pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 4, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 4, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current L1$ State", s0, s1); pwrdm_state2string(s0, (pwrdm_state)extract_bitfield(pm_pda_cpu0_pwrstctrl, 0, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstctrl, 0, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Standby Status", ((extract_bit(cm_pda_cpu0_clkctrl, 0) == 1) ? "STANDBY" : "RUNNING"), ((extract_bit(cm_pda_cpu1_clkctrl, 0) == 1) ? "STANDBY" : "RUNNING")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "", "", ""); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Target Power State", s0, s1); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Logic State When Domain is RET", ((extract_bit(pm_pda_cpu0_pwrstctrl, 2) == 1) ? "RET" : "OFF"), ((extract_bit(pm_pda_cpu1_pwrstctrl, 2) == 1) ? "RET" : "OFF")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Clock Control", clkdm_ctrl_mode_name_get((clkdm_ctrl_mode) extract_bitfield(cm_pda_cpu0_clkstctrl, 0, 2)), clkdm_ctrl_mode_name_get((clkdm_ctrl_mode) extract_bitfield(cm_pda_cpu1_clkstctrl, 0, 2))); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "", "", ""); if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0)) || cpu_is_omap4460() || cpu_is_omap4470()) { pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 24, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 24, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last Power State", s0, s1); } fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last L1$ Context", ((extract_bit(rm_pda_cpu0_context, 8) == 1) ? "LOST" : "RETAINED"), ((extract_bit(rm_pda_cpu1_context, 8) == 1) ? "LOST" : "RETAINED")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last CPU Context", ((extract_bit(rm_pda_cpu0_context, 0) == 1) ? "LOST" : "RETAINED"), ((extract_bit(rm_pda_cpu1_context, 0) == 1) ? "LOST" : "RETAINED")); fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "\n"); /* SCU Configuration */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "SCU Configuration", "CPU0", "CPU1"); fprintf(stream, "|--------------------------------|-----------|-------" "----|\n"); OMAPCONF_SCU_CPU_POWER_STATUS_2_STRING(s0, extract_bitfield(scu_cpu_power_status, 0, 2)); OMAPCONF_SCU_CPU_POWER_STATUS_2_STRING(s1, extract_bitfield(scu_cpu_power_status, 8, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "CPU Power Status", s0, s1); fprintf(stream, "|---------------------------------------------------" "-----|\n"); fprintf(stream, "\n"); /* MPU Power Domain Configuration */ if (mem_read(OMAP4430_PM_MPU_PWRSTCTRL, &pm_pwstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_MPU_PWRSTST, &pm_pwstst) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = pwrdm44xx_config_show(stream, "MPU", OMAP4430_PM_MPU_PWRSTCTRL, pm_pwstctrl, OMAP4430_PM_MPU_PWRSTST, pm_pwstst); if (ret != 0) return ret; /* MPU Clock Domain Configuration */ if (mem_read(OMAP4430_CM_MPU_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "MPU", OMAP4430_CM_MPU_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* MPU Module Power Configuration */ if (mem_read(OMAP4430_CM_MPU_MPU_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_MPU_MPU_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MPU", OMAP4430_CM_MPU_MPU_CLKCTRL, cm_clkctrl, OMAP4430_RM_MPU_MPU_CONTEXT, rm_context); if (ret != 0) return ret; /* MPU DPLL Configuration */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| MPU DPLL Configuration " " |\n"); fprintf(stream, "|--------------------------------|-------------------" "----|\n"); fprintf(stream, "| %-30s | %-21s |\n", "Status", dpll_status_name_get((dpll_status) dpll_mpu_params.status)); sprintf(s0, "%d", (unsigned int) dpll_mpu_params.M2_speed); fprintf(stream, "| %-30s | %-21s |\n", "Clock Speed (MHz)", s0); fprintf(stream, "| %-30s | %-21s |\n", "Mode", dpll_mode_name_get((dpll_mode) dpll_mpu_params.mode)); fprintf(stream, "| %-30s | %-21s |\n", "Low-Power Mode", (dpll_mpu_params.lpmode == 1) ? "Enabled" : "Disabled"); fprintf(stream, "| %-30s | %-21s |\n", "Autoidle Mode", dpll_autoidle_mode_name_get((dpll_autoidle_mode) dpll_mpu_params.autoidle_mode)); fprintf(stream, "| %-30s | %-21s |\n", "M2 Output Autogating", (dpll_mpu_params.M2_autogating == 1) ? "Enabled" : "Disabled"); fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "\nNB: type \"omapconf dplls cfg\" " "for detailed DPLL configuration.\n\n"); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION powerdm_config_show * @BRIEF decode and display power domain configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_ARG * OMAPCONF_ERR_NOT_AVAILABLE * @param[in,out] stream: output file * @param[in] powerdm: power domain name * @DESCRIPTION decode and display power domain configuration *//*------------------------------------------------------------------------ */ int powerdm_config_show(FILE *stream, const char *powerdm) { int ret; powerdm_info data; pwrdm_state st_last, st_curr, st_tgt; reg *pm_pwrstctrl; reg *pm_pwrstst; char s[64]; char s1[32], s2[32]; CHECK_NULL_ARG(stream, OMAPCONF_ERR_ARG); CHECK_NULL_ARG(powerdm, OMAPCONF_ERR_ARG); ret = _powerdm_info_get(powerdm, &data); if (ret != 0) { dprintf("%s(%s): could not retrieve powerdm_info struct!\n", __func__, powerdm); return OMAPCONF_ERR_NOT_AVAILABLE; } fprintf(stream, "|----------------------------------------------------------------|\n"); strcpy(s, powerdm); strcat(s, " Power Domain Configuration"); fprintf(stream, "| %-62s |\n", s); fprintf(stream, "|----------------------------------------------------------------|\n"); fprintf(stream, "| %-32s | %-7s | %-7s | %-7s |\n", "Power State", "Current", "Target", "Last"); fprintf(stream, "|----------------------------------|---------|---------|---------|\n"); st_last = powerdm_state_get(powerdm, PWRDM_STATE_PREVIOUS); st_curr = powerdm_state_get(powerdm, PWRDM_STATE_CURRENT); st_tgt = powerdm_state_get(powerdm, PWRDM_STATE_TARGET); fprintf(stream, "| %-32s | %-7s | %-7s | %-7s |\n", "Domain", pwrdm_state_name_get(st_curr), pwrdm_state_name_get(st_tgt), pwrdm_state_name_get(st_last)); if ((!powerdm_has_logic_ret_state_ctrl_bit(powerdm)) && (data.pwrstst == NULL)) goto powerdm_config_show_mem; st_tgt = powerdm_target_logic_ret_state_get(powerdm); if (st_tgt != PWRDM_STATE_MAX) strcpy(s1, pwrdm_state_name_get(st_tgt)); else strcpy(s1, ""); st_curr = powerdm_logic_state_get(powerdm); if (st_curr != PWRDM_STATE_MAX) strcpy(s2, pwrdm_state_name_get(st_curr)); else strcpy(s2, ""); fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Logic", s2, s1); powerdm_config_show_mem: if (cpu_is_omap44xx()) { pm_pwrstctrl = powerdm_pwrstctrl_reg_get(powerdm); pm_pwrstst = powerdm_pwrstst_reg_get(powerdm); ret = pwrdm44xx_config_show(stream, powerdm, reg_addr_get(pm_pwrstctrl), reg_read(pm_pwrstctrl), reg_addr_get(pm_pwrstst), reg_read(pm_pwrstst)); } else if (cpu_is_omap54xx()) { ret = pwrdm54xx_config_show(stream, data); } else { fprintf(stderr, "omapconf: %s(): cpu not supported!!!\n", __func__); ret = OMAPCONF_ERR_CPU; } if (data.pwrstst != NULL) { fprintf(stream, "|----------------------------------------------------------------|\n"); fprintf(stream, "| %-32s | %-27s |\n", "Ongoing Power Transition?", ((powerdm_in_transition(powerdm) == 1) ? "YES" : "NO")); } fprintf(stream, "|----------------------------------------------------------------|\n\n"); return ret; }
/* ------------------------------------------------------------------------*//** * @FUNCTION per44xx_config_show * @BRIEF analyze power configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in,out] stream: output file stream * @DESCRIPTION analyze power configuration *//*------------------------------------------------------------------------ */ int per44xx_config_show(FILE *stream) { unsigned int pm_pwstctrl; unsigned int pm_pwstst; unsigned int cm_clkstctrl; unsigned int rm_context; unsigned int cm_clkctrl; int ret; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) per44xx_regtable_init(); if (mem_read(OMAP4430_PM_L4PER_PWRSTCTRL, &pm_pwstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_L4PER_PWRSTST, &pm_pwstst) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_L4PER_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = pwrdm44xx_config_show(stream, "L4_PER", OMAP4430_PM_L4PER_PWRSTCTRL, pm_pwstctrl, OMAP4430_PM_L4PER_PWRSTST, pm_pwstst); if (ret != 0) return ret; ret = clkdm44xx_config_show(stream, "L4_PER", OMAP4430_CM_L4PER_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_L4PER_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_L4_PER_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "L4_PER", OMAP4430_CM_L4PER_L4PER_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_L4_PER_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_DMTIMER2_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPTIMER2", OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_DMTIMER2_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_DMTIMER3_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPTIMER3", OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_DMTIMER3_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_DMTIMER4_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPTIMER4", OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_DMTIMER4_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_DMTIMER9_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPTIMER9", OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_DMTIMER9_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_DMTIMER10_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPTIMER10", OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_DMTIMER10_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_DMTIMER11_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPTIMER11", OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_DMTIMER11_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_ELM_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_ELM_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "ELM", OMAP4430_CM_L4PER_ELM_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_ELM_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_GPIO2_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_GPIO2_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPIO2", OMAP4430_CM_L4PER_GPIO2_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_GPIO2_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_GPIO3_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_GPIO3_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPIO3", OMAP4430_CM_L4PER_GPIO3_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_GPIO3_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_GPIO4_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_GPIO4_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPIO4", OMAP4430_CM_L4PER_GPIO4_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_GPIO4_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_GPIO5_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_GPIO5_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPIO5", OMAP4430_CM_L4PER_GPIO5_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_GPIO5_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_GPIO6_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_GPIO6_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "GPIO6", OMAP4430_CM_L4PER_GPIO6_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_GPIO6_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_HDQ1W_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "HDQ1W", OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_HDQ1W_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_I2C1_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_I2C1_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "I2C1", OMAP4430_CM_L4PER_I2C1_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_I2C1_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_I2C2_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_I2C2_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "I2C2", OMAP4430_CM_L4PER_I2C2_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_I2C2_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_I2C3_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_I2C3_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "I2C3", OMAP4430_CM_L4PER_I2C3_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_I2C3_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_I2C4_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_I2C4_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "I2C4", OMAP4430_CM_L4PER_I2C4_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_I2C4_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_MCBSP4_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MCBSP4", OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_MCBSP4_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_MCSPI1_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MCSPI1", OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_MCSPI1_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_MCSPI2_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MCSPI2", OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_MCSPI2_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_MCSPI3_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MCSPI3", OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_MCSPI3_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_MCSPI4_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MCSPI4", OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_MCSPI4_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_MMCSD3_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MMCSD3", OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_MMCSD3_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_MMCSD4_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MMCSD4", OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_MMCSD4_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_MMCSD5_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MMCSD5", OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_MMCSD5_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "SLIMBUS2", OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_UART1_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_UART1_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "UART1", OMAP4430_CM_L4PER_UART1_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_UART1_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_UART2_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_UART2_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "UART2", OMAP4430_CM_L4PER_UART2_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_UART2_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_UART3_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_UART3_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "UART3", OMAP4430_CM_L4PER_UART3_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_UART3_CONTEXT, rm_context); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_L4PER_UART4_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_L4PER_UART4_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "UART4", OMAP4430_CM_L4PER_UART4_CLKCTRL, cm_clkctrl, OMAP4430_RM_L4PER_UART4_CONTEXT, rm_context); if (ret != 0) return ret; return 0; }