int serial_tstc(void) { u32 uart_data = qca_soc_reg_read(QCA_HSUART_DATA_REG); return ((uart_data & QCA_HSUART_DATA_RX_CSR_MASK) >> QCA_HSUART_DATA_RX_CSR_SHIFT); }
/* * Returns last reset reason: * 1 -> reset by watchdog * 0 -> normal reset */ int last_reset_wdt() { u32 reg; reg = qca_soc_reg_read(QCA_RST_WATCHDOG_TIMER_CTRL_REG); if (reg & QCA_RST_WATCHDOG_TIMER_CTRL_LAST_MASK) return 1; return 0; }
int serial_getc(void) { u32 uart_data; while (!serial_tstc()) ; uart_data = qca_soc_reg_read(QCA_HSUART_DATA_REG); qca_soc_reg_write(QCA_HSUART_DATA_REG, (1 << QCA_HSUART_DATA_RX_CSR_SHIFT)); return (uart_data & QCA_HSUART_DATA_TX_RX_DATA_MASK); }
/* * Put QCA SOC name, version and revision in buffer */ void qca_soc_name_rev(char *buf) { u32 id; u32 major; u32 rev = 0; if (buf == NULL) return; /* Get revision ID value */ id = qca_soc_reg_read(QCA_RST_REVISION_ID_REG); major = id & QCA_RST_REVISION_ID_MAJOR_MASK; rev = id & QCA_RST_REVISION_ID_REV_MASK; switch (major) { #if (SOC_TYPE & QCA_AR933X_SOC) case QCA_RST_REVISION_ID_MAJOR_AR9330_VAL: sprintf(buf, "AR9330 rev. %d", rev); break; case QCA_RST_REVISION_ID_MAJOR_AR9331_VAL: sprintf(buf, "AR9331 rev. %d", rev); break; #endif #if (SOC_TYPE & QCA_AR934X_SOC) case QCA_RST_REVISION_ID_MAJOR_AR9341_VAL: sprintf(buf, "AR9341 rev. %d", rev); break; case QCA_RST_REVISION_ID_MAJOR_AR9344_VAL: sprintf(buf, "AR9344 rev. %d", rev); break; #endif #if (SOC_TYPE & QCA_QCA953X_SOC) case QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL: sprintf(buf, "QCA953x ver. 1 rev. %d", rev); break; case QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL: sprintf(buf, "QCA953x ver. 2 rev. %d", rev); break; #endif #if (SOC_TYPE & QCA_QCA955X_SOC) case QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL: sprintf(buf, "QCA9558 rev. %d", rev); break; #endif default: sprintf(buf, "Unknown"); break; } }
void serial_putc(const char c) { u32 uart_data; if (c == '\n') serial_putc('\r'); /* Wait for FIFO */ do { uart_data = qca_soc_reg_read(QCA_HSUART_DATA_REG); } while (((uart_data & QCA_HSUART_DATA_TX_CSR_MASK) >> QCA_HSUART_DATA_TX_CSR_SHIFT) == 0); /* Put data in buffer and set CSR bit */ uart_data = (u32)c | (1 << QCA_HSUART_DATA_TX_CSR_SHIFT); qca_soc_reg_write(QCA_HSUART_DATA_REG, uart_data); }
/* * Returns "reset button" status: * 1 -> button is pressed * 0 -> button is not pressed */ int reset_button_status(void) { #ifdef CONFIG_GPIO_RESET_BTN u32 gpio; gpio = qca_soc_reg_read(QCA_GPIO_IN_REG); if (gpio & (1 << CONFIG_GPIO_RESET_BTN)) { #if defined(CONFIG_GPIO_RESET_BTN_ACTIVE_LOW) return 0; #else return 1; #endif } else { #if defined(CONFIG_GPIO_RESET_BTN_ACTIVE_LOW) return 1; #else return 0; #endif } #else return 0; #endif }
/* * Returns 1 if reference clock is 40 MHz */ inline u32 qca_xtal_is_40mhz(void) { return ((qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG) & QCA_RST_BOOTSTRAP_REF_CLK_MASK) >> QCA_RST_BOOTSTRAP_REF_CLK_SHIFT); }