/* Legacy helper function. Should go away when machine config files are implemented. */ void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq) { DeviceState *dev; SysBusDevice *s; qemu_check_nic_model(nd, "smc91c111"); dev = qdev_create(NULL, "smc91c111"); qdev_set_netdev(dev, nd); qdev_init(dev); s = sysbus_from_qdev(dev); sysbus_mmio_map(s, 0, base); sysbus_connect_irq(s, 0, irq); }
static DeviceState *goldfish_device_bus_create(GoldfishBus *gbus, uint32_t base, uint32_t irq) { DeviceState *dev; char *name = (char *)"goldfish_device_bus"; dev = qdev_create(&gbus->bus, name); qdev_prop_set_string(dev, "name", name); qdev_prop_set_uint32(dev, "base", base); qdev_prop_set_uint32(dev, "irq", irq); qdev_init_nofail(dev); return dev; }
static void ioapic_init(GSIState *gsi_state) { DeviceState *dev; SysBusDevice *d; unsigned int i; if (kvm_irqchip_in_kernel()) { dev = qdev_create(NULL, "kvm-ioapic"); } else { dev = qdev_create(NULL, "ioapic"); } /* FIXME: this should be under the piix3. */ object_property_add_child(object_resolve_path("i440fx", NULL), "ioapic", OBJECT(dev), NULL); qdev_init_nofail(dev); d = sysbus_from_qdev(dev); sysbus_mmio_map(d, 0, 0xfec00000); for (i = 0; i < IOAPIC_NUM_PINS; i++) { gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); } }
/* Legacy helper function. Should go away when machine config files are implemented. */ void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq) { DeviceState *dev; SysBusDevice *s; qemu_check_nic_model(nd, "smc91c111"); dev = qdev_create(NULL, "smc91c111"); qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_mmio_map(s, 0, base); sysbus_connect_irq(s, 0, irq); }
static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) { DeviceState *dev; SysBusDevice *s; qemu_check_nic_model(nd, "cadence_gem"); dev = qdev_create(NULL, "cadence_gem"); qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); s = sysbus_from_qdev(dev); sysbus_mmio_map(s, 0, base); sysbus_connect_irq(s, 0, irq); }
static void idreg_init(hwaddr addr) { DeviceState *dev; SysBusDevice *s; dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_mmio_map(s, 0, addr); cpu_physical_memory_write_rom(&address_space_memory, addr, idreg_data, sizeof(idreg_data)); }
/* FIXME callers should check for failure, but don't */ SCSIDevice *scsi_bus_legacy_add_drive(SCSIBus *bus, DriveInfo *dinfo, int unit) { const char *driver; DeviceState *dev; driver = bdrv_is_sg(dinfo->bdrv) ? "scsi-generic" : "scsi-disk"; dev = qdev_create(&bus->qbus, driver); qdev_prop_set_uint32(dev, "scsi-id", unit); qdev_prop_set_drive(dev, "drive", dinfo); if (qdev_init(dev) < 0) return NULL; return DO_UPCAST(SCSIDevice, qdev, dev); }
static void init_cpus(const char *cpu_type, const char *privdev, hwaddr periphbase, qemu_irq *pic, bool secure) { DeviceState *dev; SysBusDevice *busdev; int n; /* Create the actual CPUs */ for (n = 0; n < smp_cpus; n++) { Object *cpuobj = object_new(cpu_type); if (!secure) { object_property_set_bool(cpuobj, false, "has_el3", NULL); } if (object_property_find(cpuobj, "reset-cbar", NULL)) { object_property_set_int(cpuobj, periphbase, "reset-cbar", &error_abort); } object_property_set_bool(cpuobj, true, "realized", &error_fatal); } /* Create the private peripheral devices (including the GIC); * this must happen after the CPUs are created because a15mpcore_priv * wires itself up to the CPU's generic_timer gpio out lines. */ dev = qdev_create(NULL, privdev); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, periphbase); /* Interrupts [42:0] are from the motherboard; * [47:43] are reserved; [63:48] are daughterboard * peripherals. Note that some documentation numbers * external interrupts starting from 32 (because there * are internal interrupts 0..31). */ for (n = 0; n < 64; n++) { pic[n] = qdev_get_gpio_in(dev, n); } /* Connect the CPUs to the GIC */ for (n = 0; n < smp_cpus; n++) { DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); sysbus_connect_irq(busdev, n + smp_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); } }
void *mcf_uart_init(qemu_irq irq, Chardev *chrdrv) { DeviceState *dev; dev = qdev_create(NULL, TYPE_MCF_UART); if (chrdrv) { qdev_prop_set_chr(dev, "chardev", chrdrv); } qdev_init_nofail(dev); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); return dev; }
static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) { DeviceState *dev; SysBusDevice *s; dev = qdev_create(NULL, "iommu"); qdev_prop_set_uint32(dev, "version", version); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_connect_irq(s, 0, irq); sysbus_mmio_map(s, 0, addr); return s; }
ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io) { if (isabus) { fprintf(stderr, "Can't create a second ISA bus\n"); return NULL; } if (NULL == dev) { dev = qdev_create(NULL, "isabus-bridge"); qdev_init_nofail(dev); } isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL)); isabus->address_space_io = address_space_io; return isabus; }
static void ioapic_init(IsaIrqState *isa_irq_state) { DeviceState *dev; SysBusDevice *d; unsigned int i; dev = qdev_create(NULL, "ioapic"); qdev_init_nofail(dev); d = sysbus_from_qdev(dev); sysbus_mmio_map(d, 0, 0xfec00000); for (i = 0; i < IOAPIC_NUM_PINS; i++) { isa_irq_state->ioapic[i] = qdev_get_gpio_in(dev, i); } }
static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd) { DeviceState *dev; SysBusDevice *s; dev = qdev_create(NULL, "mipsnet"); qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_connect_irq(s, 0, irq); memory_region_add_subregion(get_system_io(), base, sysbus_mmio_get_region(s, 0)); }
static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) { DeviceState *dev; SysBusDevice *s; dev = qdev_create(NULL, "eccmemctl"); qdev_prop_set_uint32(dev, "version", version); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_connect_irq(s, 0, irq); sysbus_mmio_map(s, 0, base); if (version == 0) { // SS-600MP only sysbus_mmio_map(s, 1, base + 0x1000); } }
static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) { DeviceState *dev; SysBusDevice *s; RamDevice *d; /* allocate RAM */ dev = qdev_create(NULL, "memory"); s = sysbus_from_qdev(dev); d = FROM_SYSBUS(RamDevice, s); d->size = RAM_size; qdev_init_nofail(dev); sysbus_mmio_map(s, 0, addr); }
static void ram_init(hwaddr addr, ram_addr_t RAM_size) { DeviceState *dev; SysBusDevice *s; RamDevice *d; /* allocate RAM */ dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); s = SYS_BUS_DEVICE(dev); d = SUN4U_RAM(dev); d->size = RAM_size; qdev_init_nofail(dev); sysbus_mmio_map(s, 0, addr); }
static void ram_init(hwaddr addr, ram_addr_t RAM_size) { DeviceState *dev; SysBusDevice *s; RamDevice *d; /* allocate RAM */ dev = qdev_create(NULL, "memory"); s = SYS_BUS_DEVICE(dev); d = FROM_SYSBUS(RamDevice, s); d->size = RAM_size; qdev_init_nofail(dev); sysbus_mmio_map(s, 0, addr); }
void s390_flic_init(void) { DeviceState *dev; int r; dev = s390_flic_kvm_create(); if (!dev) { dev = qdev_create(NULL, TYPE_QEMU_S390_FLIC); object_property_add_child(qdev_get_machine(), TYPE_QEMU_S390_FLIC, OBJECT(dev), NULL); } r = qdev_init(dev); if (r) { error_report("flic: couldn't create qdev"); } }
static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, void *iommu, qemu_irq *dev_irq, int is_ledma) { DeviceState *dev; SysBusDevice *s; dev = qdev_create(NULL, "sparc32_dma"); qdev_prop_set_ptr(dev, "iommu_opaque", iommu); qdev_prop_set_uint32(dev, "is_ledma", is_ledma); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_connect_irq(s, 0, parent_irq); *dev_irq = qdev_get_gpio_in(dev, 0); sysbus_mmio_map(s, 0, daddr); return s; }
void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, const uint8_t *eeprom_spd, int eeprom_spd_size) { int i; uint8_t *eeprom_buf = g_malloc0(8 * 256); /* XXX: make this persistent */ if (eeprom_spd_size > 0) { memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size); } for (i = 0; i < nb_eeprom; i++) { DeviceState *eeprom; eeprom = qdev_create((BusState *)smbus, "smbus-eeprom"); qdev_prop_set_uint8(eeprom, "address", 0x50 + i); qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); qdev_init_nofail(eeprom); } }
FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, hwaddr data_addr, uint32_t data_width) { DeviceState *dev; SysBusDevice *sbd; dev = qdev_create(NULL, TYPE_FW_CFG_MEM); qdev_prop_set_uint32(dev, "data_width", data_width); fw_cfg_init1(dev); sbd = SYS_BUS_DEVICE(dev); sysbus_mmio_map(sbd, 0, ctl_addr); sysbus_mmio_map(sbd, 1, data_addr); return FW_CFG(dev); }
static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, qemu_irq **cpu_irqs, int irq_pin) { DeviceState *dev; SysBusDevice *s; int i; dev = qdev_create(NULL, "or1k-ompic"); qdev_prop_set_uint32(dev, "num-cpus", num_cpus); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); for (i = 0; i < num_cpus; i++) { sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]); } sysbus_mmio_map(s, 0, base); }
static void lan9215_init(uint32_t base, qemu_irq irq) { DeviceState *dev; SysBusDevice *s; /* This should be a 9215 but the 9118 is close enough */ if (nd_table[0].used) { qemu_check_nic_model(&nd_table[0], "lan9118"); dev = qdev_create(NULL, "lan9118"); qdev_set_nic_properties(dev, &nd_table[0]); qdev_prop_set_uint32(dev, "mode_16bit", 1); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_mmio_map(s, 0, base); sysbus_connect_irq(s, 0, irq); } }
ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space, MemoryRegion *address_space_io, Error **errp) { if (isabus) { error_setg(errp, "Can't create a second ISA bus"); return NULL; } if (!dev) { dev = qdev_create(NULL, "isabus-bridge"); qdev_init_nofail(dev); } isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL)); isabus->address_space = address_space; isabus->address_space_io = address_space_io; return isabus; }
void empty_slot_init(hwaddr addr, uint64_t slot_size) { if (slot_size > 0) { /* Only empty slots larger than 0 byte need handling. */ DeviceState *dev; SysBusDevice *s; EmptySlot *e; dev = qdev_create(NULL, "empty_slot"); s = SYS_BUS_DEVICE(dev); e = FROM_SYSBUS(EmptySlot, s); e->size = slot_size; qdev_init_nofail(dev); sysbus_mmio_map(s, 0, addr); } }
DeviceState *goldfish_int_create(GoldfishBus *gbus, uint32_t base, qemu_irq parent_irq, qemu_irq parent_fiq) { DeviceState *dev; GoldfishDevice *gdev; GoldfishInterruptDevice *idev; char *name = (char *)"goldfish_int"; dev = qdev_create(&gbus->bus, name); qdev_prop_set_string(dev, "name", name); qdev_prop_set_uint32(dev, "base", base); qdev_init_nofail(dev); gdev = (GoldfishDevice *)dev; idev = DO_UPCAST(GoldfishInterruptDevice, dev, gdev); idev->parent_irq = parent_irq; idev->parent_fiq = parent_fiq; return dev; }
static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { SysBusDevice *s; NICInfo *nd = &nd_table[0]; /* In hardware this is a LAN9220; the LAN9118 is software compatible * except that it doesn't support the checksum-offload feature. */ qemu_check_nic_model(nd, "lan9118"); mms->lan9118 = qdev_create(NULL, "lan9118"); qdev_set_nic_properties(mms->lan9118, nd); qdev_init_nofail(mms->lan9118); s = SYS_BUS_DEVICE(mms->lan9118); sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); return sysbus_mmio_get_region(s, 0); }
void s390_init_ipl_dev(const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *firmware) { DeviceState *dev; dev = qdev_create(NULL, "s390-ipl"); if (kernel_filename) { qdev_prop_set_string(dev, "kernel", kernel_filename); } if (initrd_filename) { qdev_prop_set_string(dev, "initrd", initrd_filename); } qdev_prop_set_string(dev, "cmdline", kernel_cmdline); qdev_prop_set_string(dev, "firmware", firmware); qdev_init_nofail(dev); }
DeviceState *s5pc1xx_onedram_init(const char *name, target_phys_addr_t base, qemu_irq irq_ap) { DeviceState *dev = qdev_create(NULL, name); ram_addr_t onedram_shared, onedram_ap; qdev_init_nofail(dev); onedram_ap = qemu_ram_alloc(ONEDRAM_AP_SIZE); cpu_register_physical_memory(base, ONEDRAM_AP_SIZE, onedram_ap | IO_MEM_RAM); onedram_shared = qemu_ram_alloc(ONEDRAM_SHARED_SIZE); cpu_register_physical_memory(base + ONEDRAM_AP_SIZE, ONEDRAM_SHARED_SIZE, onedram_shared | IO_MEM_RAM); sysbus_mmio_map(sysbus_from_qdev(dev), 0, base + ONEDRAM_AP_SIZE + ONEDRAM_SFR); sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq_ap); return dev; }
f2xx_flash_t *f2xx_flash_register(BlockDriverState *bdrv, hwaddr base, hwaddr size) { DeviceState *dev = qdev_create(NULL, "f2xx.flash"); //SysBusDevice *busdev = SYS_BUS_DEVICE(dev); f2xx_flash_t *flash = (f2xx_flash_t *)object_dynamic_cast(OBJECT(dev), "f2xx.flash"); qdev_prop_set_uint32(dev, "size", size); qdev_prop_set_uint64(dev, "base_address", base); if (bdrv) { if (qdev_prop_set_drive(dev, "drive", bdrv)) { printf("%s, have no drive???\n", __func__); return NULL; } } qdev_init_nofail(dev); //sysbus_mmio_map(busdev, 0, base); return flash; }