static int sm_lcd_init(SSISlave *dev)
{
lcd_state *s = FROM_SSI_SLAVE(lcd_state, dev);
s->brightness = 0.0;
s->con = graphic_console_init(DEVICE(dev), 0, &sm_lcd_ops, s);
qemu_console_resize(s->con, NUM_COLS, NUM_ROWS);
/* This callback informs us that brightness control is enabled */
qdev_init_gpio_in_named(DEVICE(dev), sm_lcd_backlight_enable_cb,
"backlight_enable", 1);
/* This callback informs us of the brightness level (from 0 to 255) */
qdev_init_gpio_in_named(DEVICE(dev), sm_lcd_set_backlight_level_cb,
"backlight_level", 1);
/* This callback informs us that the vibrate is on/orr */
qdev_init_gpio_in_named(DEVICE(dev), sm_lcd_vibe_ctl,
"vibe_ctl", 1);
/* This callback informs us that power is on/off */
qdev_init_gpio_in_named(DEVICE(dev), sm_lcd_power_ctl,
"power_ctl", 1);
return 0;
}
static void tz_ppc_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
TZPPC *s = TZ_PPC(obj);
qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS);
qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS);
qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1);
qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1);
qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1);
qdev_init_gpio_out_named(dev, &s->irq, "irq", 1);
}
SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr)
{
SPARCCPU *cpu;
CPUSPARCState *env;
ResetData *reset_info;
uint32_t tick_frequency = 100 * 1000000;
uint32_t stick_frequency = 100 * 1000000;
uint32_t hstick_frequency = 100 * 1000000;
cpu = SPARC_CPU(cpu_create(cpu_type));
qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq,
"ivec-irq", IVEC_MAX);
env = &cpu->env;
env->tick = cpu_timer_create("tick", cpu, tick_irq,
tick_frequency, TICK_INT_DIS,
TICK_NPT_MASK);
env->stick = cpu_timer_create("stick", cpu, stick_irq,
stick_frequency, TICK_INT_DIS,
TICK_NPT_MASK);
env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
hstick_frequency, TICK_INT_DIS,
TICK_NPT_MASK);
reset_info = g_malloc0(sizeof(ResetData));
reset_info->cpu = cpu;
reset_info->prom_addr = prom_addr;
qemu_register_reset(main_cpu_reset, reset_info);
return cpu;
}
static void bcm2835_ic_init(Object *obj)
{
BCM2835ICState *s = BCM2835_IC(obj);
memory_region_init_io(&s->iomem, obj, &bcm2835_ic_ops, s, TYPE_BCM2835_IC,
0x200);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_gpu_irq,
BCM2835_IC_GPU_IRQ, GPU_IRQS);
qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_arm_irq,
BCM2835_IC_ARM_IRQ, ARM_IRQS);
sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
sysbus_init_irq(SYS_BUS_DEVICE(s), &s->fiq);
}
static void xlx_iom_realize(DeviceState *dev, Error **errp)
{
XilinxPIT *s = XILINX_IO_MODULE_PIT(dev);
unsigned int i;
s->prefix = object_get_canonical_path(OBJECT(dev));
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
RegisterInfo *r = &s->regs_info[i];
*r = (RegisterInfo) {
.data = (uint8_t *)&s->regs[i],
.data_size = sizeof(uint32_t),
.access = &pit_regs_info[i],
.debug = XILINX_IO_MODULE_PIT_ERR_DEBUG,
.prefix = s->prefix,
.opaque = s,
};
memory_region_init_io(&r->mem, OBJECT(dev), &iom_pit_ops, r,
r->access->name, 4);
memory_region_add_subregion(&s->iomem, i * 4, &r->mem);
}
if (s->cfg.use) {
s->bh = qemu_bh_new(pit_timer_hit, s);
s->ptimer = ptimer_init(s->bh);
ptimer_set_freq(s->ptimer, s->frequency);
/* IRQ out to pulse when present timer expires/reloads */
qdev_init_gpio_out(dev, &s->hit_out, 1);
/* IRQ in to enable pre-scalar mode. Routed from gpo1 */
qdev_init_gpio_in_named(dev, iom_pit_ps_config, "ps_config", 1);
/* hit_out of neighbouring PIT is received as hit_in */
qdev_init_gpio_in_named(dev, iom_pit_ps_hit_in, "ps_hit_in", 1);
}
}
static void xlx_iom_pit_init(Object *obj)
{
XilinxPIT *s = XILINX_IO_MODULE_PIT(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &iom_pit_ops, s,
TYPE_XILINX_IO_MODULE_PIT,
R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
}
static void ipi_realize(DeviceState *dev, Error **errp)
{
IPI *s = XILINX_IPI(dev);
const char *prefix = object_get_canonical_path(OBJECT(dev));
unsigned int i;
for (i = 0; i < ARRAY_SIZE(ipi_regs_info); ++i) {
DepRegisterInfo *r = &s->regs_info[ipi_regs_info[i].decode.addr/4];
*r = (DepRegisterInfo) {
.data = (uint8_t *)&s->regs[
ipi_regs_info[i].decode.addr/4],
.data_size = sizeof(uint32_t),
.access = &ipi_regs_info[i],
.debug = XILINX_IPI_ERR_DEBUG,
.prefix = prefix,
.opaque = s,
};
dep_register_init(r);
qdev_pass_all_gpios(DEVICE(r), dev);
}
qdev_init_gpio_in_named(dev, ipi_handler, "IPI_INPUTS", 32);
qdev_init_gpio_in_named(dev, obs_handler, "OBS_INPUTS", 32);
}
static void ipi_init(Object *obj)
{
IPI *s = XILINX_IPI(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &ipi_ops, s,
TYPE_XILINX_IPI, R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
}
static void ronaldo_sdhci_realize(DeviceState *dev, Error **errp)
{
DeviceClass *dc_parent = DEVICE_CLASS(RONALDO_SDHCI_PARENT_CLASS);
RonaldoSDHCIState *s = RONALDO_SDHCI(dev);
DriveInfo *di_sd;
DriveInfo *di_mmc;
di_sd = drive_get_by_index(IF_SD , s->drive_index);
di_mmc = drive_get_by_index(IF_SD, (s->drive_index + 2));
s->sd_card = sd_init(di_sd ? blk_by_legacy_dinfo(di_sd) : NULL, false);
s->mmc_card = mmc_init(di_mmc ? blk_by_legacy_dinfo(di_mmc) : NULL);
dc_parent->realize(dev, errp);
qdev_init_gpio_in_named(dev, ronaldo_sdhci_slottype_handler, "SLOTTYPE", 1);
}
static void ss_realize(DeviceState *dev, Error **errp)
{
SlaveBootInt *s = SBI(dev);
const char *prefix = object_get_canonical_path(OBJECT(dev));
unsigned int i;
const char *port_name;
Chardev *chr;
for (i = 0; i < ARRAY_SIZE(slave_boot_regs_info); ++i) {
DepRegisterInfo *r = &s->regs_info[
slave_boot_regs_info[i].decode.addr / 4];
*r = (DepRegisterInfo) {
.data = (uint8_t *)&s->regs[
slave_boot_regs_info[i].decode.addr / 4],
.data_size = sizeof(uint32_t),
.access = &slave_boot_regs_info[i],
.debug = SBI_ERR_DEBUG,
.prefix = prefix,
.opaque = s,
};
}
port_name = g_strdup("smap_busy_b");
qdev_init_gpio_out_named(dev, &s->smap_busy, port_name, 1);
g_free((gpointer) port_name);
port_name = g_strdup("smap_in_b");
qdev_init_gpio_in_named(dev, smap_update, port_name, 2);
g_free((gpointer) port_name);
chr = qemu_chr_find("sbi");
qdev_prop_set_chr(dev, "chardev", chr);
if (!qemu_chr_fe_get_driver(&s->chr)) {
DPRINT("SBI interface not connected\n");
} else {
qemu_chr_fe_set_handlers(&s->chr, ss_sbi_can_receive, ss_sbi_receive,
NULL, NULL, s, NULL, true);
}
fifo_create8(&s->fifo, 1024 * 4);
}
static void ss_reset(DeviceState *dev)
{
SlaveBootInt *s = SBI(dev);
uint32_t i;
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
dep_register_reset(&s->regs_info[i]);
}
fifo_reset(&s->fifo);
s->busy_line = 1;
qemu_set_irq(s->smap_busy, s->busy_line);
ss_update_busy_line(s);
sbi_update_irq(s);
/* Note : cs always 0 when rp is not connected
* i.e slave always respond to master data irrespective of
* master state
*
* as rdwr is also 0, initial state of sbi is data load. Hack this bit
* to become 1, when sbi changes to write mode. So, its assumed in
* non remote-port model master should expect data when slave wishes
* to send.
*/
}
static void rpu_realize(DeviceState *dev, Error **errp)
{
RPU *s = XILINX_RPU(dev);
const char *prefix = object_get_canonical_path(OBJECT(dev));
unsigned int i;
for (i = 0; i < ARRAY_SIZE(rpu_regs_info); ++i) {
RegisterInfo *r = &s->regs_info[rpu_regs_info[i].decode.addr/4];
*r = (RegisterInfo) {
.data = (uint8_t *)&s->regs[
rpu_regs_info[i].decode.addr/4],
.data_size = sizeof(uint32_t),
.access = &rpu_regs_info[i],
.debug = XILINX_RPU_ERR_DEBUG,
.prefix = prefix,
.opaque = s,
};
register_init(r);
qdev_pass_all_gpios(DEVICE(r), dev);
}
if (!s->atcm1_for_rpu0) {
error_set(errp, QERR_MISSING_PARAMETER, "atcm1-for-rpu0");
return;
}
if (!s->btcm1_for_rpu0) {
error_set(errp, QERR_MISSING_PARAMETER, "btcm1-for-rpu0");
return;
}
if (!s->icache_for_rpu1) {
error_set(errp, QERR_MISSING_PARAMETER, "icache-for-rpu1");
return;
}
if (!s->dcache_for_rpu1) {
error_set(errp, QERR_MISSING_PARAMETER, "dcache-for-rpu1");
return;
}
if (!s->ddr) {
error_set(errp, QERR_MISSING_PARAMETER, "ddr-mem-for-rpu");
return;
}
/* RPUs starts in lockstep mode, so the rpu1 caches are not accessible. */
memory_region_set_enabled(s->icache_for_rpu1, false);
memory_region_set_enabled(s->dcache_for_rpu1, false);
memory_region_set_enabled(s->ddr, false);
}
static void rpu_init(Object *obj)
{
RPU *s = XILINX_RPU(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &rpu_ops, s,
TYPE_XILINX_RPU, R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq_rpu_1);
sysbus_init_irq(sbd, &s->irq_rpu_0);
/* xtcm1-for-rpu0 are the aliases for the tcm in lockstep mode.
* This link allows to enable/disable those aliases when we are in
* lock-step/normal mode.
*/
object_property_add_link(obj, "atcm1-for-rpu0", TYPE_MEMORY_REGION,
(Object **)&s->atcm1_for_rpu0,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
object_property_add_link(obj, "btcm1-for-rpu0", TYPE_MEMORY_REGION,
(Object **)&s->btcm1_for_rpu0,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
object_property_add_link(obj, "rpu1-for-main-bus", TYPE_MEMORY_REGION,
(Object **)&s->atcm1_for_rpu0,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
/* This link allows to enable/disable those memory region when we are in
* lock-step/normal mode.
*/
object_property_add_link(obj, "icache-for-rpu1", TYPE_MEMORY_REGION,
(Object **)&s->icache_for_rpu1,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
object_property_add_link(obj, "dcache-for-rpu1", TYPE_MEMORY_REGION,
(Object **)&s->dcache_for_rpu1,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
/* Link to the second part of the DDR which is enabled in split mode and
* disabled in lockstep mode.
*/
object_property_add_link(obj, "ddr-mem-for-rpu", TYPE_MEMORY_REGION,
(Object **)&s->ddr,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
/* wfi_out is used to connect to PMU GPIs. */
qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 2);
/* wfi_in is used as input from CPUs as wfi request. */
qdev_init_gpio_in_named(DEVICE(obj), zynqmp_rpu_0_handle_wfi, "wfi_in_0", 1);
qdev_init_gpio_in_named(DEVICE(obj), zynqmp_rpu_1_handle_wfi, "wfi_in_1", 1);
}
static void xlnx_zynqmp_ipi_realize(DeviceState *dev, Error **errp)
{
qdev_init_gpio_in_named(dev, xlnx_zynqmp_ipi_handler, "IPI_INPUTS", 32);
qdev_init_gpio_in_named(dev, xlnx_zynqmp_obs_handler, "OBS_INPUTS", 32);
}
