static int eth_can_rx(NetClientState *nc)
{
struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
unsigned int rxbase = s->rxbuf * (0x800 / 4);
return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
}
static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
{
struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
unsigned int rxbase = s->rxbuf * (0x800 / 4);
/* DA filter. */
if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
return size;
if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
return -1;
}
D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase));
memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
if (s->regs[R_RX_CTRL0] & CTRL_I) {
eth_pulse_irq(s);
}
/* If c_rx_pingpong was set flip buffers. */
s->rxbuf ^= s->c_rx_pingpong;
return size;
}
static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
ETRAXFSEthState *eth = qemu_get_nic_opaque(nc);
int use_ma0 = eth->regs[RW_REC_CTRL] & 1;
int use_ma1 = eth->regs[RW_REC_CTRL] & 2;
int r_bcast = eth->regs[RW_REC_CTRL] & 8;
if (size < 12) {
return -1;
}
D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
use_ma0, use_ma1, r_bcast));
/* Does the frame get through the address filters? */
if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6))
&& (!use_ma1 || memcmp(buf, eth->macaddr[1], 6))
&& (!r_bcast || memcmp(buf, sa_bcast, 6))
&& !eth_match_groupaddr(eth, buf)) {
return size;
}
/* FIXME: Find another way to pass on the fake csum. */
etraxfs_dmac_input(eth->dma_in, (void *)buf, size + 4, 1);
return size;
}
static int mipsnet_can_receive(NetClientState *nc)
{
MIPSnetState *s = qemu_get_nic_opaque(nc);
if (s->busy)
return 0;
return !mipsnet_buffer_full(s);
}
static void nic_cleanup(NetClientState *ncs)
{
#if 0
tnetw1130_t *s = qemu_get_nic_opaque(ncs);
timer_del(d->poll_timer);
timer_free(d->poll_timer);
#endif
}
static int stellaris_enet_can_receive(NetClientState *nc)
{
stellaris_enet_state *s = qemu_get_nic_opaque(nc);
if ((s->rctl & SE_RCTL_RXEN) == 0)
return 1;
return (s->np < 31);
}
static int smc91c111_can_receive(NetClientState *nc)
{
smc91c111_state *s = qemu_get_nic_opaque(nc);
if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST))
return 1;
if (s->allocated == (1 << NUM_PACKETS) - 1)
return 0;
return 1;
}
static int dp8393x_can_receive(NetClientState *nc)
{
dp8393xState *s = qemu_get_nic_opaque(nc);
if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN))
return 0;
if (s->regs[SONIC_ISR] & SONIC_ISR_RBE)
return 0;
return 1;
}
static ssize_t etsec_receive(NetClientState *nc,
const uint8_t *buf,
size_t size)
{
eTSEC *etsec = qemu_get_nic_opaque(nc);
#if defined(HEX_DUMP)
fprintf(stderr, "%s receive size:%d\n", etsec->nic->nc.name, size);
qemu_hexdump(buf, stderr, "", size);
#endif
etsec_rx_ring_write(etsec, buf, size);
return size;
}
/* TODO: Implement MAC address filtering. */
static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
stellaris_enet_state *s = qemu_get_nic_opaque(nc);
int n;
uint8_t *p;
uint32_t crc;
if ((s->rctl & SE_RCTL_RXEN) == 0)
return -1;
if (s->np >= 31) {
return 0;
}
DPRINTF("Received packet len=%zu\n", size);
n = s->next_packet + s->np;
if (n >= 31)
n -= 31;
if (size >= sizeof(s->rx[n].data) - 6) {
/* If the packet won't fit into the
* emulated 2K RAM, this is reported
* as a FIFO overrun error.
*/
s->ris |= SE_INT_FOV;
stellaris_enet_update(s);
return -1;
}
s->np++;
s->rx[n].len = size + 6;
p = s->rx[n].data;
*(p++) = (size + 6);
*(p++) = (size + 6) >> 8;
memcpy (p, buf, size);
p += size;
crc = crc32(~0, buf, size);
*(p++) = crc;
*(p++) = crc >> 8;
*(p++) = crc >> 16;
*(p++) = crc >> 24;
/* Clear the remaining bytes in the last word. */
if ((size & 3) != 2) {
memset(p, 0, (6 - size) & 3);
}
s->ris |= SE_INT_RX;
stellaris_enet_update(s);
return size;
}
static ssize_t fp_port_receive_iov(NetClientState *nc, const struct iovec *iov,
int iovcnt)
{
FpPort *port = qemu_get_nic_opaque(nc);
/* If the port is disabled, we want to drop this pkt
* now rather than queing it for later. We don't want
* any stale pkts getting into the device when the port
* transitions to enabled.
*/
if (!port->enabled) {
return -1;
}
return world_ingress(port->world, port->pport, iov, iovcnt);
}
static ssize_t net_rx_packet(NetClientState *nc, const uint8_t *buf, size_t size)
{
struct XenNetDev *netdev = qemu_get_nic_opaque(nc);
netif_rx_request_t rxreq;
RING_IDX rc, rp;
void *page;
if (netdev->xendev.be_state != XenbusStateConnected) {
return -1;
}
rc = netdev->rx_ring.req_cons;
rp = netdev->rx_ring.sring->req_prod;
xen_rmb(); /* Ensure we see queued requests up to 'rp'. */
if (rc == rp || RING_REQUEST_CONS_OVERFLOW(&netdev->rx_ring, rc)) {
return 0;
}
if (size > XC_PAGE_SIZE - NET_IP_ALIGN) {
xen_be_printf(&netdev->xendev, 0, "packet too big (%lu > %ld)",
(unsigned long)size, XC_PAGE_SIZE - NET_IP_ALIGN);
return -1;
}
memcpy(&rxreq, RING_GET_REQUEST(&netdev->rx_ring, rc), sizeof(rxreq));
netdev->rx_ring.req_cons = ++rc;
page = xc_gnttab_map_grant_ref(netdev->xendev.gnttabdev,
netdev->xendev.dom,
rxreq.gref, PROT_WRITE);
if (page == NULL) {
xen_be_printf(&netdev->xendev, 0, "error: rx gref dereference failed (%d)\n",
rxreq.gref);
net_rx_response(netdev, &rxreq, NETIF_RSP_ERROR, 0, 0, 0);
return -1;
}
memcpy(page + NET_IP_ALIGN, buf, size);
xc_gnttab_munmap(netdev->xendev.gnttabdev, page, 1);
net_rx_response(netdev, &rxreq, NETIF_RSP_OKAY, NET_IP_ALIGN, size, 0);
return size;
}
/* TODO: Implement MAC address filtering. */
static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
stellaris_enet_state *s = qemu_get_nic_opaque(nc);
int n;
uint8_t *p;
uint32_t crc;
if ((s->rctl & SE_RCTL_RXEN) == 0)
return -1;
if (s->np >= 31) {
DPRINTF("Packet dropped\n");
return -1;
}
DPRINTF("Received packet len=%zu\n", size);
n = s->next_packet + s->np;
if (n >= 31)
n -= 31;
s->np++;
s->rx[n].len = size + 6;
p = s->rx[n].data;
*(p++) = (size + 6);
*(p++) = (size + 6) >> 8;
memcpy (p, buf, size);
p += size;
crc = crc32(~0, buf, size);
*(p++) = crc;
*(p++) = crc >> 8;
*(p++) = crc >> 16;
*(p++) = crc >> 24;
/* Clear the remaining bytes in the last word. */
if ((size & 3) != 2) {
memset(p, 0, (6 - size) & 3);
}
s->ris |= SE_INT_RX;
stellaris_enet_update(s);
return size;
}
static ssize_t etsec_receive(NetClientState *nc,
const uint8_t *buf,
size_t size)
{
ssize_t ret;
eTSEC *etsec = qemu_get_nic_opaque(nc);
#if defined(HEX_DUMP)
fprintf(stderr, "%s receive size:%d\n", etsec->nic->nc.name, size);
qemu_hexdump(buf, stderr, "", size);
#endif
/* Flush is unnecessary as are already in receiving path */
etsec->need_flush = false;
ret = etsec_rx_ring_write(etsec, buf, size);
if (ret == 0) {
/* The packet will be queued, let's flush it when buffer is available
* again. */
etsec->need_flush = true;
}
return ret;
}
static ssize_t fp_port_receive(NetClientState *nc, const uint8_t *buf,
size_t size)
{
const struct iovec iov = {
.iov_base = (uint8_t *)buf,
.iov_len = size
};
return fp_port_receive_iov(nc, &iov, 1);
}
static void fp_port_cleanup(NetClientState *nc)
{
}
static void fp_port_set_link_status(NetClientState *nc)
{
FpPort *port = qemu_get_nic_opaque(nc);
rocker_event_link_changed(port->r, port->pport, !nc->link_down);
}
static ssize_t mipsnet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
MIPSnetState *s = qemu_get_nic_opaque(nc);
trace_mipsnet_receive(size);
if (!mipsnet_can_receive(nc))
return -1;
s->busy = 1;
/* Just accept everything. */
/* Write packet data. */
memcpy(s->rx_buffer, buf, size);
s->rx_count = size;
s->rx_read = 0;
/* Now we can signal we have received something. */
s->intctl |= MIPSNET_INTCTL_RXDONE;
mipsnet_update_irq(s);
return size;
}
static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
size_t size)
{
dp8393xState *s = qemu_get_nic_opaque(nc);
uint16_t data[10];
int packet_type;
uint32_t available, address;
int width, rx_len = size;
uint32_t checksum;
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
packet_type = dp8393x_receive_filter(s, buf, size);
if (packet_type < 0) {
DPRINTF("packet not for netcard\n");
return -1;
}
/* XXX: Check byte ordering */
/* Check for EOL */
if (s->regs[SONIC_LLFA] & 0x1) {
/* Are we still in resource exhaustion? */
size = sizeof(uint16_t) * 1 * width;
address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)data, size, 0);
if (data[0 * width] & 0x1) {
/* Still EOL ; stop reception */
return -1;
} else {
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
}
}
/* Save current position */
s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
/* Calculate the ethernet checksum */
checksum = cpu_to_le32(crc32(0, buf, rx_len));
/* Put packet into RBA */
DPRINTF("Receive packet at %08x\n", dp8393x_crba(s));
address = dp8393x_crba(s);
address_space_rw(&s->as, address,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1);
address += rx_len;
address_space_rw(&s->as, address,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1);
rx_len += 4;
s->regs[SONIC_CRBA1] = address >> 16;
s->regs[SONIC_CRBA0] = address & 0xffff;
available = dp8393x_rbwc(s);
available -= rx_len / 2;
s->regs[SONIC_RBWC1] = available >> 16;
s->regs[SONIC_RBWC0] = available & 0xffff;
/* Update status */
if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) {
s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
}
s->regs[SONIC_RCR] |= packet_type;
s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
if (s->loopback_packet) {
s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
s->loopback_packet = 0;
}
/* Write status to memory */
DPRINTF("Write status at %08x\n", dp8393x_crda(s));
data[0 * width] = s->regs[SONIC_RCR]; /* status */
data[1 * width] = rx_len; /* byte count */
data[2 * width] = s->regs[SONIC_TRBA0]; /* pkt_ptr0 */
data[3 * width] = s->regs[SONIC_TRBA1]; /* pkt_ptr1 */
data[4 * width] = s->regs[SONIC_RSC]; /* seq_no */
size = sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, dp8393x_crda(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
/* Move to next descriptor */
size = sizeof(uint16_t) * width;
address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
s->regs[SONIC_LLFA] = data[0 * width];
if (s->regs[SONIC_LLFA] & 0x1) {
/* EOL detected */
s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
} else {
data[0 * width] = 0; /* in_use */
address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1);
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);
if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
/* Read next RRA */
dp8393x_do_read_rra(s);
}
}
/* Done */
dp8393x_update_irq(s);
return size;
}
static ssize_t spapr_vlan_receive(NetClientState *nc, const uint8_t *buf,
size_t size)
{
VIOsPAPRVLANDevice *dev = qemu_get_nic_opaque(nc);
VIOsPAPRDevice *sdev = VIO_SPAPR_DEVICE(dev);
vlan_bd_t rxq_bd = vio_ldq(sdev, dev->buf_list + VLAN_RXQ_BD_OFF);
vlan_bd_t bd;
int buf_ptr = dev->use_buf_ptr;
uint64_t handle;
uint8_t control;
dprintf("spapr_vlan_receive() [%s] rx_bufs=%d\n", sdev->qdev.id,
dev->rx_bufs);
if (!dev->isopen) {
return -1;
}
if (!dev->rx_bufs) {
return -1;
}
do {
buf_ptr += 8;
if (buf_ptr >= SPAPR_TCE_PAGE_SIZE) {
buf_ptr = VLAN_RX_BDS_OFF;
}
bd = vio_ldq(sdev, dev->buf_list + buf_ptr);
dprintf("use_buf_ptr=%d bd=0x%016llx\n",
buf_ptr, (unsigned long long)bd);
} while ((!(bd & VLAN_BD_VALID) || (VLAN_BD_LEN(bd) < (size + 8)))
&& (buf_ptr != dev->use_buf_ptr));
if (!(bd & VLAN_BD_VALID) || (VLAN_BD_LEN(bd) < (size + 8))) {
/* Failed to find a suitable buffer */
return -1;
}
/* Remove the buffer from the pool */
dev->rx_bufs--;
dev->use_buf_ptr = buf_ptr;
vio_stq(sdev, dev->buf_list + dev->use_buf_ptr, 0);
dprintf("Found buffer: ptr=%d num=%d\n", dev->use_buf_ptr, dev->rx_bufs);
/* Transfer the packet data */
if (spapr_vio_dma_write(sdev, VLAN_BD_ADDR(bd) + 8, buf, size) < 0) {
return -1;
}
dprintf("spapr_vlan_receive: DMA write completed\n");
/* Update the receive queue */
control = VLAN_RXQC_TOGGLE | VLAN_RXQC_VALID;
if (rxq_bd & VLAN_BD_TOGGLE) {
control ^= VLAN_RXQC_TOGGLE;
}
handle = vio_ldq(sdev, VLAN_BD_ADDR(bd));
vio_stq(sdev, VLAN_BD_ADDR(rxq_bd) + dev->rxq_ptr + 8, handle);
vio_stl(sdev, VLAN_BD_ADDR(rxq_bd) + dev->rxq_ptr + 4, size);
vio_sth(sdev, VLAN_BD_ADDR(rxq_bd) + dev->rxq_ptr + 2, 8);
vio_stb(sdev, VLAN_BD_ADDR(rxq_bd) + dev->rxq_ptr, control);
dprintf("wrote rxq entry (ptr=0x%llx): 0x%016llx 0x%016llx\n",
(unsigned long long)dev->rxq_ptr,
(unsigned long long)vio_ldq(sdev, VLAN_BD_ADDR(rxq_bd) +
dev->rxq_ptr),
(unsigned long long)vio_ldq(sdev, VLAN_BD_ADDR(rxq_bd) +
dev->rxq_ptr + 8));
dev->rxq_ptr += 16;
if (dev->rxq_ptr >= VLAN_BD_LEN(rxq_bd)) {
dev->rxq_ptr = 0;
vio_stq(sdev, dev->buf_list + VLAN_RXQ_BD_OFF, rxq_bd ^ VLAN_BD_TOGGLE);
}
if (sdev->signal_state & 1) {
qemu_irq_pulse(spapr_vio_qirq(sdev));
}
return size;
}
static int spapr_vlan_can_receive(NetClientState *nc)
{
VIOsPAPRVLANDevice *dev = qemu_get_nic_opaque(nc);
return (dev->isopen && dev->rx_bufs > 0);
}
static void spapr_vlan_cleanup(NetClientState *nc)
{
VIOsPAPRVLANDevice *dev = qemu_get_nic_opaque(nc);
dev->nic = NULL;
}
static void etsec_set_link_status(NetClientState *nc)
{
eTSEC *etsec = qemu_get_nic_opaque(nc);
etsec_miim_link_status(etsec, nc);
}
static void eth_set_link(NetClientState *nc)
{
ETRAXFSEthState *eth = qemu_get_nic_opaque(nc);
D(printf("%s %d\n", __func__, nc->link_down));
eth->phy.link = !nc->link_down;
}
static void
e1000e_set_link_status(NetClientState *nc)
{
E1000EState *s = qemu_get_nic_opaque(nc);
e1000e_core_set_link_status(&s->core);
}
static ssize_t
e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
E1000EState *s = qemu_get_nic_opaque(nc);
return e1000e_receive(&s->core, buf, size);
}
static ssize_t
e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
{
E1000EState *s = qemu_get_nic_opaque(nc);
return e1000e_receive_iov(&s->core, iov, iovcnt);
}
static ssize_t smc91c111_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
smc91c111_state *s = qemu_get_nic_opaque(nc);
int status;
int packetsize;
uint32_t crc;
int packetnum;
uint8_t *p;
if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST))
return -1;
/* Short packets are padded with zeros. Receiving a packet
< 64 bytes long is considered an error condition. */
if (size < 64)
packetsize = 64;
else
packetsize = (size & ~1);
packetsize += 6;
crc = (s->rcr & RCR_STRIP_CRC) == 0;
if (crc)
packetsize += 4;
/* TODO: Flag overrun and receive errors. */
if (packetsize > 2048)
return -1;
packetnum = smc91c111_allocate_packet(s);
if (packetnum == 0x80)
return -1;
s->rx_fifo[s->rx_fifo_len++] = packetnum;
p = &s->data[packetnum][0];
/* ??? Multicast packets? */
status = 0;
if (size > 1518)
status |= RS_TOOLONG;
if (size & 1)
status |= RS_ODDFRAME;
*(p++) = status & 0xff;
*(p++) = status >> 8;
*(p++) = packetsize & 0xff;
*(p++) = packetsize >> 8;
memcpy(p, buf, size & ~1);
p += (size & ~1);
/* Pad short packets. */
if (size < 64) {
int pad;
if (size & 1)
*(p++) = buf[size - 1];
pad = 64 - size;
memset(p, 0, pad);
p += pad;
size = 64;
}
/* It's not clear if the CRC should go before or after the last byte in
odd sized packets. Linux disables the CRC, so that's no help.
The pictures in the documentation show the CRC aligned on a 16-bit
boundary before the last odd byte, so that's what we do. */
if (crc) {
crc = crc32(~0, buf, size);
*(p++) = crc & 0xff; crc >>= 8;
*(p++) = crc & 0xff; crc >>= 8;
*(p++) = crc & 0xff; crc >>= 8;
*(p++) = crc & 0xff;
}
if (size & 1) {
*(p++) = buf[size - 1];
*p = 0x60;
} else {
*(p++) = 0;
*p = 0x40;
}
/* TODO: Raise early RX interrupt? */
s->int_level |= INT_RCV;
smc91c111_update(s);
return size;
}
static void smc91c111_cleanup(NetClientState *nc)
{
smc91c111_state *s = qemu_get_nic_opaque(nc);
s->nic = NULL;
}
static void eth_cleanup(NetClientState *nc)
{
struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
s->nic = NULL;
}
static void lan9118_set_link(NetClientState *nc)
{
phy_update_link(qemu_get_nic_opaque(nc));
}
static int
e1000e_nc_can_receive(NetClientState *nc)
{
E1000EState *s = qemu_get_nic_opaque(nc);
return e1000e_can_receive(&s->core);
}
