static void mips_qemu_write (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
if ((addr & 0xffff) == 0 && val == 42)
qemu_system_reset_request ();
else if ((addr & 0xffff) == 4 && val == 42)
qemu_system_shutdown_request ();
}
int handle_shutdown(kvm_context_t kvm, CPUState *env)
{
/* stop the current vcpu from going back to guest mode */
env->stopped = 1;
qemu_system_reset_request();
return 1;
}
static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
if ((addr & 0xffff) == 0 && val == 42)
qemu_system_reset_request ();
else if ((addr & 0xffff) == 4 && val == 42)
qemu_system_shutdown_request ();
}
static void mips_qemu_write (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
if ((addr & 0xffff) == 0 && val == 42)
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
else if ((addr & 0xffff) == 4 && val == 42)
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
}
static void outport_write(KBDState *s, uint32_t val)
{
DPRINTF("kbd: write outport=0x%02x\n", val);
s->outport = val;
qemu_set_irq(s->a20_out, (val >> 1) & 1);
if (!(val & 1)) {
qemu_system_reset_request();
}
}
static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
PIIX4PMState *s = opaque;
addr &= 0x3f;
switch(addr) {
case 0x00:
{
int64_t d;
int pmsts;
pmsts = get_pmsts(s);
if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
/* if TMRSTS is reset, then compute the new overflow time */
d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
get_ticks_per_sec());
s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
}
s->pmsts &= ~val;
pm_update_sci(s);
}
break;
case 0x02:
s->pmen = val;
pm_update_sci(s);
break;
case 0x04:
{
int sus_typ;
s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
if (val & ACPI_BITMASK_SLEEP_ENABLE) {
/* change suspend type */
sus_typ = (val >> 10) & 7;
switch(sus_typ) {
case 0: /* soft power off */
qemu_system_shutdown_request();
break;
case 1:
/* ACPI_BITMASK_WAKE_STATUS should be set on resume.
Pretend that resume was caused by power button */
s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
ACPI_BITMASK_POWER_BUTTON_STATUS);
qemu_system_reset_request();
if (s->cmos_s3) {
qemu_irq_raise(s->cmos_s3);
}
default:
break;
}
}
}
break;
default:
break;
}
static void rtas_system_reboot(PowerPCCPU *cpu, sPAPREnvironment *spapr,
uint32_t token, uint32_t nargs,
target_ulong args,
uint32_t nret, target_ulong rets)
{
if (nargs != 0 || nret != 1) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
qemu_system_reset_request();
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}
static void rtas_system_reboot(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t token, uint32_t nargs,
target_ulong args,
uint32_t nret, target_ulong rets)
{
if (nargs != 0 || nret != 1) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}
static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
PIIX4PMState *s = opaque;
addr &= 0x3f;
switch(addr) {
case 0x00:
{
int64_t d;
int pmsts;
pmsts = get_pmsts(s);
if (pmsts & val & TMROF_EN) {
/* if TMRSTS is reset, then compute the new overflow time */
d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ,
get_ticks_per_sec());
s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
}
s->pmsts &= ~val;
pm_update_sci(s);
}
break;
case 0x02:
s->pmen = val;
pm_update_sci(s);
break;
case 0x04:
{
int sus_typ;
s->pmcntrl = val & ~(SUS_EN);
if (val & SUS_EN) {
/* change suspend type */
sus_typ = (val >> 10) & 7;
switch(sus_typ) {
case 0: /* soft power off */
qemu_system_shutdown_request();
break;
case 1:
/* RSM_STS should be set on resume. Pretend that resume
was caused by power button */
s->pmsts |= (RSM_STS | PWRBTN_STS);
qemu_system_reset_request();
#if defined(TARGET_I386)
cmos_set_s3_resume();
#endif
default:
break;
}
}
}
break;
default:
break;
}
/*
* Check nested exceptions and change to double or triple fault if
* needed. It should only be called, if this is not an interrupt.
* Returns the new exception number.
*/
static int check_exception(CPUX86State *env, int intno, int *error_code)
{
int first_contributory = env->old_exception == 0 ||
(env->old_exception >= 10 &&
env->old_exception <= 13);
int second_contributory = intno == 0 ||
(intno >= 10 && intno <= 13);
qemu_log_mask(CPU_LOG_INT, "check_exception old: 0x%x new 0x%x\n",
env->old_exception, intno);
#if !defined(CONFIG_USER_ONLY)
if (env->old_exception == EXCP08_DBLE) {
if (env->hflags & HF_SVMI_MASK) {
cpu_vmexit(env, SVM_EXIT_SHUTDOWN, 0); /* does not return */
}
qemu_log_mask(CPU_LOG_RESET, "Triple fault\n");
#if 0
qemu_system_reset_request();
return EXCP_HLT;
#else
/*
* QEMU traditionally resets the machine on triple fault
* because programs written for 286 protected mode would exit
* protected mode by intentionally triple faulting the machine
* (after setting the boot vector to point to their code).
* This sucks for debugging programs that were written after
* 1985, so we instead halt the machine for inspection.
*/
return EXCP_TRIPLE;
#endif
}
#endif
if ((first_contributory && second_contributory)
|| (env->old_exception == EXCP0E_PAGE &&
(second_contributory || (intno == EXCP0E_PAGE)))) {
intno = EXCP08_DBLE;
*error_code = 0;
}
if (second_contributory || (intno == EXCP0E_PAGE) ||
(intno == EXCP08_DBLE)) {
env->old_exception = intno;
}
return intno;
}
static void hb_regs_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
uint32_t *regs = opaque;
if (offset == 0xf00) {
if (value == 1 || value == 2) {
qemu_system_reset_request();
} else if (value == 3) {
qemu_system_shutdown_request();
}
}
regs[offset/4] = value;
}
static void watchdog_hit(void *opaque)
{
struct etrax_timer *t = opaque;
if (t->wd_hits == 0) {
/* real hw gives a single tick before reseting but we are
a bit friendlier to compensate for our slower execution. */
ptimer_set_count(t->ptimer_wd, 10);
ptimer_run(t->ptimer_wd, 1);
qemu_irq_raise(t->nmi);
}
else
qemu_system_reset_request();
t->wd_hits++;
}
static void pxa2xx_timer_tick(void *opaque)
{
PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
PXA2xxTimerInfo *i = t->info;
if (i->irq_enabled & (1 << t->num)) {
i->events |= 1 << t->num;
qemu_irq_raise(t->irq);
}
if (t->num == 3)
if (i->reset3 & 1) {
i->reset3 = 0;
qemu_system_reset_request();
}
}
static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
{
if (value & 8) {
qemu_system_reset_request();
}
if ((s->cm_ctrl ^ value) & 1) {
/* (value & 1) != 0 means the green "MISC LED" is lit.
* We don't have any nice place to display LEDs. printf is a bad
* idea because Linux uses the LED as a heartbeat and the output
* will swamp anything else on the terminal.
*/
}
/* Note that the RESET bit [3] always reads as zero */
s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
integratorcm_do_remap(s);
}
static void mpc8544_guts_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
addr &= MPC8544_GUTS_MMIO_SIZE - 1;
switch (addr) {
case MPC8544_GUTS_ADDR_RSTCR:
if (value & MPC8544_GUTS_RSTCR_RESET) {
qemu_system_reset_request();
}
break;
default:
fprintf(stderr, "guts: Unknown register write: %x = %x\n",
(int)addr, (unsigned)value);
break;
}
}
static void xtfpga_fpga_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
XtfpgaFpgaState *s = opaque;
switch (addr) {
case 0x8: /*LEDs (off = 0, on = 1)*/
s->leds = val;
break;
case 0x10: /*board reset*/
if (val == 0xdead) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
break;
}
}
static void slavio_sysctrl_mem_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
trace_slavio_sysctrl_mem_writel(val);
switch (addr) {
case 0:
if (val & SYS_RESET) {
s->sysctrl = SYS_RESETSTAT;
qemu_system_reset_request();
}
break;
default:
break;
}
}
static void lx60_fpga_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
Lx60FpgaState *s = opaque;
switch (addr) {
case 0x8: /*LEDs (off = 0, on = 1)*/
s->leds = val;
break;
case 0x10: /*board reset*/
if (val == 0xdead) {
qemu_system_reset_request();
}
break;
}
}
static void pxa2xx_timer_tick(void *opaque)
{
struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque;
pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
if (i->irq_enabled & (1 << t->num)) {
t->level = 1;
i->events |= 1 << t->num;
qemu_irq_raise(t->irq);
}
if (t->num == 3)
if (i->reset3 & 1) {
i->reset3 = 0;
qemu_system_reset_request();
}
}
uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
uint64_t cpu_addr)
{
int cc = 0;
HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
__func__, order_code, r1, cpu_addr);
/* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
as parameter (input). Status (output) is always R1. */
switch (order_code) {
case SIGP_SET_ARCH:
/* switch arch */
break;
case SIGP_SENSE:
/* enumerate CPU status */
if (cpu_addr) {
/* XXX implement when SMP comes */
return 3;
}
env->regs[r1] &= 0xffffffff00000000ULL;
cc = 1;
break;
#if !defined(CONFIG_USER_ONLY)
case SIGP_RESTART:
qemu_system_reset_request();
cpu_loop_exit(env);
break;
case SIGP_STOP:
qemu_system_shutdown_request();
cpu_loop_exit(env);
break;
#endif
default:
/* unknown sigp */
fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
cc = 3;
}
return cc;
}
static void hb_regs_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
uint32_t *regs = opaque;
if (offset == 0xf00) {
if (value == 1 || value == 2) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
} else if (value == 3) {
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
}
}
if (offset / 4 >= NUM_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
"highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
return;
}
regs[offset / 4] = value;
}
static void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
{
KBDState *s = opaque;
#ifdef DEBUG_KBD
printf("kbd: write data=0x%02x\n", val);
#endif
switch(s->write_cmd) {
case 0:
ps2_write_keyboard(s->kbd, val);
break;
case KBD_CCMD_WRITE_MODE:
s->mode = val;
ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
/* ??? */
kbd_update_irq(s);
break;
case KBD_CCMD_WRITE_OBUF:
kbd_queue(s, val, 0);
break;
case KBD_CCMD_WRITE_AUX_OBUF:
kbd_queue(s, val, 1);
break;
case KBD_CCMD_WRITE_OUTPORT:
#ifdef TARGET_I386
ioport_set_a20((val >> 1) & 1);
#endif
if (!(val & 1)) {
qemu_system_reset_request();
}
break;
case KBD_CCMD_WRITE_MOUSE:
ps2_write_mouse(s->mouse, val);
break;
default:
break;
}
s->write_cmd = 0;
}
/*
* Check nested exceptions and change to double or triple fault if
* needed. It should only be called, if this is not an interrupt.
* Returns the new exception number.
*/
static int check_exception(CPUX86State *env, int intno, int *error_code)
{
int first_contributory = env->old_exception == 0 ||
(env->old_exception >= 10 &&
env->old_exception <= 13);
int second_contributory = intno == 0 ||
(intno >= 10 && intno <= 13);
qemu_log_mask(CPU_LOG_INT, "check_exception old: 0x%x new 0x%x\n",
env->old_exception, intno);
#if !defined(CONFIG_USER_ONLY)
if (env->old_exception == EXCP08_DBLE) {
if (env->hflags & HF_SVMI_MASK) {
cpu_vmexit(env, SVM_EXIT_SHUTDOWN, 0); /* does not return */
}
qemu_log_mask(CPU_LOG_RESET, "Triple fault\n");
qemu_system_reset_request(env->uc);
return EXCP_HLT;
}
#endif
if ((first_contributory && second_contributory)
|| (env->old_exception == EXCP0E_PAGE &&
(second_contributory || (intno == EXCP0E_PAGE)))) {
intno = EXCP08_DBLE;
*error_code = 0;
}
if (second_contributory || (intno == EXCP0E_PAGE) ||
(intno == EXCP08_DBLE)) {
env->old_exception = intno;
}
return intno;
}
static int ipmi_do_hw_op(IPMIInterface *s, enum ipmi_op op, int checkonly)
{
switch (op) {
case IPMI_RESET_CHASSIS:
if (checkonly) {
return 0;
}
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
return 0;
case IPMI_POWEROFF_CHASSIS:
if (checkonly) {
return 0;
}
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
return 0;
case IPMI_SEND_NMI:
if (checkonly) {
return 0;
}
qmp_inject_nmi(NULL);
return 0;
case IPMI_SHUTDOWN_VIA_ACPI_OVERTEMP:
if (checkonly) {
return 0;
}
qemu_system_powerdown_request();
return 0;
case IPMI_POWERCYCLE_CHASSIS:
case IPMI_PULSE_DIAG_IRQ:
case IPMI_POWERON_CHASSIS:
default:
return IPMI_CC_COMMAND_NOT_SUPPORTED;
}
}
void s390_reipl_request(void)
{
S390IPLState *ipl = get_ipl_device();
ipl->reipl_requested = true;
if (ipl->iplb_valid &&
!ipl->netboot &&
ipl->iplb.pbt == S390_IPL_TYPE_CCW &&
is_virtio_scsi_device(&ipl->iplb)) {
CcwDevice *ccw_dev = s390_get_ccw_device(get_boot_device(0));
if (ccw_dev &&
cpu_to_be16(ccw_dev->sch->devno) == ipl->iplb.ccw.devno &&
(ccw_dev->sch->ssid & 3) == ipl->iplb.ccw.ssid) {
/*
* this is the original boot device's SCSI
* so restore IPL parameter info from it
*/
ipl->iplb_valid = s390_gen_initial_iplb(ipl);
}
}
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
/**
* vexpress_cfgctrl_write:
* @s: arm_sysctl_state pointer
* @dcc, @function, @site, @position, @device: split out values from
* SYS_CFGCTRL register
* @val: data to write
*
* Handle a VExpress SYS_CFGCTRL register write. On success, return true.
* On failure, return false.
*/
static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc,
unsigned int function, unsigned int site,
unsigned int position, unsigned int device,
uint32_t val)
{
/* We don't support anything other than DCC 0, board stack position 0
* or sites other than motherboard/daughterboard:
*/
if (dcc != 0 || position != 0 ||
(site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
goto cfgctrl_unimp;
}
switch (function) {
case SYS_CFG_OSC:
if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) {
/* motherboard clock */
s->mb_clock[device] = val;
return true;
}
if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
/* daughterboard clock */
s->db_clock[device] = val;
return true;
}
break;
case SYS_CFG_MUXFPGA:
if (site == SYS_CFG_SITE_MB && device == 0) {
/* Select whether video output comes from motherboard
* or daughterboard: log and ignore as QEMU doesn't
* support this.
*/
qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output "
"not supported, ignoring\n");
return true;
}
break;
case SYS_CFG_SHUTDOWN:
if (site == SYS_CFG_SITE_MB && device == 0) {
qemu_system_shutdown_request();
return true;
}
break;
case SYS_CFG_REBOOT:
if (site == SYS_CFG_SITE_MB && device == 0) {
qemu_system_reset_request();
return true;
}
break;
case SYS_CFG_DVIMODE:
if (site == SYS_CFG_SITE_MB && device == 0) {
/* Selecting DVI mode is meaningless for QEMU: we will
* always display the output correctly according to the
* pixel height/width programmed into the CLCD controller.
*/
return true;
}
default:
break;
}
cfgctrl_unimp:
qemu_log_mask(LOG_UNIMP,
"arm_sysctl: Unimplemented SYS_CFGCTRL write of function "
"0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
function, dcc, site, position, device);
return false;
}
static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
uint32_t val)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
switch (offset) {
case 0x08: /* LED */
s->leds = val;
case 0x0c: /* OSC0 */
case 0x10: /* OSC1 */
case 0x14: /* OSC2 */
case 0x18: /* OSC3 */
case 0x1c: /* OSC4 */
/* ??? */
break;
case 0x20: /* LOCK */
if (val == LOCK_VALUE)
s->lockval = val;
else
s->lockval = val & 0x7fff;
break;
case 0x28: /* CFGDATA1 */
/* ??? Need to implement this. */
s->cfgdata1 = val;
break;
case 0x2c: /* CFGDATA2 */
/* ??? Need to implement this. */
s->cfgdata2 = val;
break;
case 0x30: /* FLAGSSET */
s->flags |= val;
break;
case 0x34: /* FLAGSCLR */
s->flags &= ~val;
break;
case 0x38: /* NVFLAGSSET */
s->nvflags |= val;
break;
case 0x3c: /* NVFLAGSCLR */
s->nvflags &= ~val;
break;
case 0x40: /* RESETCTL */
if (s->lockval == LOCK_VALUE) {
s->resetlevel = val;
if (val & 0x100)
qemu_system_reset_request ();
}
break;
case 0x44: /* PCICTL */
/* nothing to do. */
break;
case 0x4c: /* FLASH */
case 0x50: /* CLCD */
case 0x54: /* CLCDSER */
case 0x64: /* DMAPSR0 */
case 0x68: /* DMAPSR1 */
case 0x6c: /* DMAPSR2 */
case 0x70: /* IOSEL */
case 0x74: /* PLDCTL */
case 0x80: /* BUSID */
case 0x84: /* PROCID0 */
case 0x88: /* PROCID1 */
case 0x8c: /* OSCRESET0 */
case 0x90: /* OSCRESET1 */
case 0x94: /* OSCRESET2 */
case 0x98: /* OSCRESET3 */
case 0x9c: /* OSCRESET4 */
break;
default:
printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
return;
}
}
static void kbd_write_command(void *opaque, uint32_t addr, uint32_t val)
{
KBDState *s = opaque;
#ifdef DEBUG_KBD
printf("kbd: write cmd=0x%02x\n", val);
#endif
switch(val) {
case KBD_CCMD_READ_MODE:
kbd_queue(s, s->mode, 0);
break;
case KBD_CCMD_WRITE_MODE:
case KBD_CCMD_WRITE_OBUF:
case KBD_CCMD_WRITE_AUX_OBUF:
case KBD_CCMD_WRITE_MOUSE:
case KBD_CCMD_WRITE_OUTPORT:
s->write_cmd = val;
break;
case KBD_CCMD_MOUSE_DISABLE:
s->mode |= KBD_MODE_DISABLE_MOUSE;
break;
case KBD_CCMD_MOUSE_ENABLE:
s->mode &= ~KBD_MODE_DISABLE_MOUSE;
break;
case KBD_CCMD_TEST_MOUSE:
kbd_queue(s, 0x00, 0);
break;
case KBD_CCMD_SELF_TEST:
s->status |= KBD_STAT_SELFTEST;
kbd_queue(s, 0x55, 0);
break;
case KBD_CCMD_KBD_TEST:
kbd_queue(s, 0x00, 0);
break;
case KBD_CCMD_KBD_DISABLE:
s->mode |= KBD_MODE_DISABLE_KBD;
kbd_update_irq(s);
break;
case KBD_CCMD_KBD_ENABLE:
s->mode &= ~KBD_MODE_DISABLE_KBD;
kbd_update_irq(s);
break;
case KBD_CCMD_READ_INPORT:
kbd_queue(s, 0x00, 0);
break;
case KBD_CCMD_READ_OUTPORT:
/* XXX: check that */
#ifdef TARGET_I386
val = 0x01 | (ioport_get_a20() << 1);
#else
val = 0x01;
#endif
if (s->status & KBD_STAT_OBF)
val |= 0x10;
if (s->status & KBD_STAT_MOUSE_OBF)
val |= 0x20;
kbd_queue(s, val, 0);
break;
#ifdef TARGET_I386
case KBD_CCMD_ENABLE_A20:
ioport_set_a20(1);
break;
case KBD_CCMD_DISABLE_A20:
ioport_set_a20(0);
break;
#endif
case KBD_CCMD_RESET:
qemu_system_reset_request();
break;
case 0xff:
/* ignore that - I don't know what is its use */
break;
default:
fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", val);
break;
}
}
void qmp_system_reset(Error **errp)
{
qemu_system_reset_request();
}
static void arm_sysctl_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
switch (offset) {
case 0x08: /* LED */
s->leds = val;
break;
case 0x0c: /* OSC0 */
case 0x10: /* OSC1 */
case 0x14: /* OSC2 */
case 0x18: /* OSC3 */
case 0x1c: /* OSC4 */
/* ??? */
break;
case 0x20: /* LOCK */
if (val == LOCK_VALUE)
s->lockval = val;
else
s->lockval = val & 0x7fff;
break;
case 0x28: /* CFGDATA1 */
/* ??? Need to implement this. */
s->cfgdata1 = val;
break;
case 0x2c: /* CFGDATA2 */
/* ??? Need to implement this. */
s->cfgdata2 = val;
break;
case 0x30: /* FLAGSSET */
s->flags |= val;
break;
case 0x34: /* FLAGSCLR */
s->flags &= ~val;
break;
case 0x38: /* NVFLAGSSET */
s->nvflags |= val;
break;
case 0x3c: /* NVFLAGSCLR */
s->nvflags &= ~val;
break;
case 0x40: /* RESETCTL */
switch (board_id(s)) {
case BOARD_ID_PB926:
if (s->lockval == LOCK_VALUE) {
s->resetlevel = val;
if (val & 0x100) {
qemu_system_reset_request();
}
}
break;
case BOARD_ID_PBX:
case BOARD_ID_PBA8:
if (s->lockval == LOCK_VALUE) {
s->resetlevel = val;
if (val & 0x04) {
qemu_system_reset_request();
}
}
break;
case BOARD_ID_VEXPRESS:
case BOARD_ID_EB:
default:
/* reserved: RAZ/WI */
break;
}
break;
case 0x44: /* PCICTL */
/* nothing to do. */
break;
case 0x4c: /* FLASH */
break;
case 0x50: /* CLCD */
switch (board_id(s)) {
case BOARD_ID_PB926:
/* On 926 bits 13:8 are R/O, bits 1:0 control
* the mux that defines how to interpret the PL110
* graphics format, and other bits are r/w but we
* don't implement them to do anything.
*/
s->sys_clcd &= 0x3f00;
s->sys_clcd |= val & ~0x3f00;
qemu_set_irq(s->pl110_mux_ctrl, val & 3);
break;
case BOARD_ID_EB:
/* The EB is the same except that there is no mux since
* the EB has a PL111.
*/
s->sys_clcd &= 0x3f00;
s->sys_clcd |= val & ~0x3f00;
break;
case BOARD_ID_PBA8:
case BOARD_ID_PBX:
/* On PBA8 and PBX bit 7 is r/w and all other bits
* are either r/o or RAZ/WI.
*/
s->sys_clcd &= (1 << 7);
s->sys_clcd |= val & ~(1 << 7);
break;
case BOARD_ID_VEXPRESS:
default:
/* On VExpress this register is unimplemented and will RAZ/WI */
break;
}
break;
case 0x54: /* CLCDSER */
case 0x64: /* DMAPSR0 */
case 0x68: /* DMAPSR1 */
case 0x6c: /* DMAPSR2 */
case 0x70: /* IOSEL */
case 0x74: /* PLDCTL */
case 0x80: /* BUSID */
case 0x84: /* PROCID0 */
case 0x88: /* PROCID1 */
case 0x8c: /* OSCRESET0 */
case 0x90: /* OSCRESET1 */
case 0x94: /* OSCRESET2 */
case 0x98: /* OSCRESET3 */
case 0x9c: /* OSCRESET4 */
break;
case 0xa0: /* SYS_CFGDATA */
if (board_id(s) != BOARD_ID_VEXPRESS) {
goto bad_reg;
}
s->sys_cfgdata = val;
return;
case 0xa4: /* SYS_CFGCTRL */
if (board_id(s) != BOARD_ID_VEXPRESS) {
goto bad_reg;
}
/* Undefined bits [19:18] are RAZ/WI, and writing to
* the start bit just triggers the action; it always reads
* as zero.
*/
s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31));
if (val & (1 << 31)) {
/* Start bit set -- actually do something */
unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4);
unsigned int function = extract32(s->sys_cfgctrl, 20, 6);
unsigned int site = extract32(s->sys_cfgctrl, 16, 2);
unsigned int position = extract32(s->sys_cfgctrl, 12, 4);
unsigned int device = extract32(s->sys_cfgctrl, 0, 12);
s->sys_cfgstat = 1; /* complete */
if (s->sys_cfgctrl & (1 << 30)) {
if (!vexpress_cfgctrl_write(s, dcc, function, site, position,
device, s->sys_cfgdata)) {
s->sys_cfgstat |= 2; /* error */
}
} else {
uint32_t val;
if (!vexpress_cfgctrl_read(s, dcc, function, site, position,
device, &val)) {
s->sys_cfgstat |= 2; /* error */
} else {
s->sys_cfgdata = val;
}
}
}
s->sys_cfgctrl &= ~(1 << 31);
return;
case 0xa8: /* SYS_CFGSTAT */
if (board_id(s) != BOARD_ID_VEXPRESS) {
goto bad_reg;
}
s->sys_cfgstat = val & 3;
return;
default:
bad_reg:
qemu_log_mask(LOG_GUEST_ERROR,
"arm_sysctl_write: Bad register offset 0x%x\n",
(int)offset);
return;
}
}
