void acpi_pm1_evt_reset(ACPIREGS *ar) { ar->pm1.evt.sts = 0; ar->pm1.evt.en = 0; qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC, 0); qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_PMTIMER, 0); }
static void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val) { ar->pm1.evt.en = val; qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC, val & ACPI_BITMASK_RT_CLOCK_ENABLE); qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_PMTIMER, val & ACPI_BITMASK_TIMER_ENABLE); }
static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) { PIIX4PMState *s = opaque; addr &= 0x3f; switch(addr) { case 0x00: { int64_t d; int pmsts; pmsts = get_pmsts(s); if (pmsts & val & TMROF_EN) { /* if TMRSTS is reset, then compute the new overflow time */ d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec()); s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; } s->pmsts &= ~val; pm_update_sci(s); } break; case 0x02: s->pmen = val; qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC, val & RTC_EN); qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_PMTIMER, val & TMROF_EN); pm_update_sci(s); break; case 0x04: { int sus_typ; s->pmcntrl = val & ~(SUS_EN); if (val & SUS_EN) { /* change suspend type */ sus_typ = (val >> 10) & 7; switch(sus_typ) { case 0: /* soft power off */ qemu_system_shutdown_request(); break; case 1: qemu_system_suspend_request(); break; default: if (sus_typ == s->s4_val) { /* S4 request */ monitor_protocol_event(QEVENT_SUSPEND_DISK, NULL); qemu_system_shutdown_request(); } break; } } } break; default: break; }