static int qpnp_regulator_vs_clear_ocp(struct qpnp_regulator *vreg)
{
int rc;
rc = qpnp_vreg_masked_write(vreg, QPNP_COMMON_REG_ENABLE,
QPNP_COMMON_DISABLE, QPNP_COMMON_ENABLE_MASK,
&vreg->ctrl_reg[QPNP_COMMON_IDX_ENABLE]);
if (rc)
vreg_err(vreg, "qpnp_vreg_masked_write failed, rc=%d\n", rc);
vreg->vs_enable_time = ktime_get();
rc = qpnp_vreg_masked_write(vreg, QPNP_COMMON_REG_ENABLE,
QPNP_COMMON_ENABLE, QPNP_COMMON_ENABLE_MASK,
&vreg->ctrl_reg[QPNP_COMMON_IDX_ENABLE]);
if (rc)
vreg_err(vreg, "qpnp_vreg_masked_write failed, rc=%d\n", rc);
if (qpnp_vreg_debug_mask & QPNP_VREG_DEBUG_OCP) {
pr_info("%s: switch state toggled after OCP event\n",
vreg->rdesc.name);
}
return rc;
}
static int qpnp_regulator_common_set_mode(struct regulator_dev *rdev,
unsigned int mode)
{
struct qpnp_regulator *vreg = rdev_get_drvdata(rdev);
int rc = 0;
u8 val;
if (mode != REGULATOR_MODE_NORMAL && mode != REGULATOR_MODE_IDLE) {
vreg_err(vreg, "invalid mode: %u\n", mode);
return -EINVAL;
}
val = (mode == REGULATOR_MODE_NORMAL ? QPNP_COMMON_MODE_HPM_MASK : 0);
rc = qpnp_vreg_masked_write(vreg, QPNP_COMMON_REG_MODE, val,
QPNP_COMMON_MODE_HPM_MASK,
&vreg->ctrl_reg[QPNP_COMMON_IDX_MODE]);
if (rc)
vreg_err(vreg, "SPMI write failed, rc=%d\n", rc);
else
qpnp_vreg_show_state(rdev, QPNP_REGULATOR_ACTION_MODE);
return rc;
}
static int qpnp_regulator_boost_set_voltage(struct regulator_dev *rdev,
int min_uV, int max_uV, unsigned *selector)
{
struct qpnp_regulator *vreg = rdev_get_drvdata(rdev);
int rc, range_sel, voltage_sel;
rc = qpnp_regulator_select_voltage(vreg, min_uV, max_uV, &range_sel,
&voltage_sel);
if (rc) {
vreg_err(vreg, "could not set voltage, rc=%d\n", rc);
return rc;
}
/*
* Boost type regulators do not have range select register so only
* voltage set register needs to be written.
*/
rc = qpnp_vreg_masked_write(vreg, QPNP_COMMON_REG_VOLTAGE_SET,
voltage_sel, 0xFF, &vreg->ctrl_reg[QPNP_COMMON_IDX_VOLTAGE_SET]);
if (rc)
vreg_err(vreg, "SPMI write failed, rc=%d\n", rc);
else
qpnp_vreg_show_state(rdev, QPNP_REGULATOR_ACTION_VOLTAGE);
return rc;
}
/*
* Perform a masked read-modify-write to a PMIC register only if the new value
* differs from the value currently in the register. This removes redundant
* register writing.
*/
static int qpnp_vreg_masked_read_write(struct qpnp_regulator *vreg, u16 addr,
u8 val, u8 mask)
{
int rc;
u8 reg;
rc = qpnp_vreg_read(vreg, addr, ®, 1);
if (rc) {
vreg_err(vreg, "read failed; addr=0x%03X, rc=%d\n", addr, rc);
return rc;
}
return qpnp_vreg_masked_write(vreg, addr, val, mask, ®);
}
static int qpnp_regulator_common_disable(struct regulator_dev *rdev)
{
struct qpnp_regulator *vreg = rdev_get_drvdata(rdev);
int rc;
rc = qpnp_vreg_masked_write(vreg, QPNP_COMMON_REG_ENABLE,
QPNP_COMMON_DISABLE, QPNP_COMMON_ENABLE_MASK,
&vreg->ctrl_reg[QPNP_COMMON_IDX_ENABLE]);
if (rc)
vreg_err(vreg, "qpnp_vreg_masked_write failed, rc=%d\n", rc);
else
qpnp_vreg_show_state(rdev, QPNP_REGULATOR_ACTION_DISABLE);
return rc;
}