static int fsl_qspi_probe(struct udevice *bus) { u32 total_size; struct fsl_qspi_platdata *plat = dev_get_platdata(bus); struct fsl_qspi_priv *priv = dev_get_priv(bus); struct dm_spi_bus *dm_spi_bus; dm_spi_bus = bus->uclass_priv; dm_spi_bus->max_hz = plat->speed_hz; priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base; priv->flags = plat->flags; priv->speed_hz = plat->speed_hz; priv->amba_base[0] = plat->amba_base; priv->amba_total_size = plat->amba_total_size; priv->flash_num = plat->flash_num; priv->num_chipselect = plat->num_chipselect; qspi_write32(priv->flags, &priv->regs->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; /* * Any read access to non-implemented addresses will provide * undefined results. * * In case single die flash devices, TOP_ADDR_MEMA2 and * TOP_ADDR_MEMB2 should be initialized/programmed to * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, * setting the size of these devices to 0. This would ensure * that the complete memory map is assigned to only one flash device. */ qspi_write32(priv->flags, &priv->regs->sfa1ad, FSL_QSPI_FLASH_SIZE | priv->amba_base[0]); qspi_write32(priv->flags, &priv->regs->sfa2ad, FSL_QSPI_FLASH_SIZE | priv->amba_base[0]); qspi_write32(priv->flags, &priv->regs->sfb1ad, total_size | priv->amba_base[0]); qspi_write32(priv->flags, &priv->regs->sfb2ad, total_size | priv->amba_base[0]); qspi_set_lut(priv); #ifdef CONFIG_SYS_FSL_QSPI_AHB qspi_init_ahb_read(priv); #endif qspi_module_disable(priv, 0); return 0; }
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct fsl_qspi *qspi; struct fsl_qspi_regs *regs; u32 reg_val, smpr_val; u32 total_size, seq_id; if (bus >= ARRAY_SIZE(spi_bases)) return NULL; qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); if (!qspi) return NULL; qspi->reg_base = spi_bases[bus]; qspi->amba_base = amba_bases[bus]; qspi->slave.max_write_size = TX_BUFFER_SIZE; regs = (struct fsl_qspi_regs *)qspi->reg_base; qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); smpr_val = qspi_read32(®s->smpr); qspi_write32(®s->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK)); qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK); total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; qspi_write32(®s->sfa1ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base); qspi_write32(®s->sfa2ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base); qspi_write32(®s->sfb1ad, total_size | qspi->amba_base); qspi_write32(®s->sfb2ad, total_size | qspi->amba_base); qspi_set_lut(qspi); smpr_val = qspi_read32(®s->smpr); smpr_val &= ~QSPI_SMPR_DDRSMP_MASK; qspi_write32(®s->smpr, smpr_val); qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK); seq_id = 0; reg_val = qspi_read32(®s->bfgencr); reg_val &= ~QSPI_BFGENCR_SEQID_MASK; reg_val |= (seq_id << QSPI_BFGENCR_SEQID_SHIFT); reg_val &= ~QSPI_BFGENCR_PAR_EN_MASK; qspi_write32(®s->bfgencr, reg_val); return &qspi->slave; }
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct fsl_qspi *qspi; struct fsl_qspi_regs *regs; u32 total_size; if (bus >= ARRAY_SIZE(spi_bases)) return NULL; if (cs >= FSL_QSPI_FLASH_NUM) return NULL; qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); if (!qspi) return NULL; #ifdef CONFIG_SYS_FSL_QSPI_BE qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG; #endif regs = (struct fsl_qspi_regs *)spi_bases[bus]; qspi->priv.regs = regs; /* * According cs, use different amba_base to choose the * corresponding flash devices. * * If not, only one flash device is used even if passing * different cs using `sf probe` */ qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE; qspi->slave.max_write_size = TX_BUFFER_SIZE; qspi_write32(qspi->priv.flags, ®s->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); qspi_cfg_smpr(&qspi->priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; /* * Any read access to non-implemented addresses will provide * undefined results. * * In case single die flash devices, TOP_ADDR_MEMA2 and * TOP_ADDR_MEMB2 should be initialized/programmed to * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, * setting the size of these devices to 0. This would ensure * that the complete memory map is assigned to only one flash device. */ qspi_write32(qspi->priv.flags, ®s->sfa1ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]); qspi_write32(qspi->priv.flags, ®s->sfa2ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]); qspi_write32(qspi->priv.flags, ®s->sfb1ad, total_size | amba_bases[bus]); qspi_write32(qspi->priv.flags, ®s->sfb2ad, total_size | amba_bases[bus]); qspi_set_lut(&qspi->priv); #ifdef CONFIG_SYS_FSL_QSPI_AHB qspi_init_ahb_read(&qspi->priv); #endif qspi_module_disable(&qspi->priv, 0); return &qspi->slave; }